xref: /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala (revision 367512b707c976b7ff3fa2e0a4cf1b35a5c1d3c2) 
1package xiangshan.mem
2
3import chisel3._
4import chisel3.util._
5import utils._
6import xiangshan._
7import xiangshan.cache._
8import xiangshan.cache.{DCacheWordIO, DCacheLineIO, TlbRequestIO, MemoryOpConstants}
9import xiangshan.backend.LSUOpType
10import xiangshan.mem._
11import xiangshan.backend.roq.RoqPtr
12
13class ExceptionAddrIO extends XSBundle {
14  val lsIdx = Input(new LSIdx)
15  val isStore = Input(Bool())
16  val vaddr = Output(UInt(VAddrBits.W))
17}
18
19class FwdEntry extends XSBundle {
20  val mask = Vec(8, Bool())
21  val data = Vec(8, UInt(8.W))
22}
23
24// inflight miss block reqs
25class InflightBlockInfo extends XSBundle {
26  val block_addr = UInt(PAddrBits.W)
27  val valid = Bool()
28}
29
30class LsqEnqIO extends XSBundle {
31  val canAccept = Output(Bool())
32  val needAlloc = Vec(RenameWidth, Input(Bool()))
33  val req = Vec(RenameWidth, Flipped(ValidIO(new MicroOp)))
34  val resp = Vec(RenameWidth, Output(new LSIdx))
35}
36
37// Load / Store Queue Wrapper for XiangShan Out of Order LSU
38class LsqWrappper extends XSModule with HasDCacheParameters {
39  val io = IO(new Bundle() {
40    val enq = new LsqEnqIO
41    val brqRedirect = Input(Valid(new Redirect))
42    val loadIn = Vec(LoadPipelineWidth, Flipped(Valid(new LsPipelineBundle)))
43    val storeIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle)))
44    val sbuffer = Vec(StorePipelineWidth, Decoupled(new DCacheWordReq))
45    val ldout = Vec(2, DecoupledIO(new ExuOutput)) // writeback int load
46    val mmioStout = DecoupledIO(new ExuOutput) // writeback uncached store
47    val forward = Vec(LoadPipelineWidth, Flipped(new LoadForwardQueryIO))
48    val commits = Flipped(new RoqCommitIO)
49    val rollback = Output(Valid(new Redirect))
50    val dcache = Flipped(ValidIO(new Refill))
51    val uncache = new DCacheWordIO
52    val roqDeqPtr = Input(new RoqPtr)
53    val exceptionAddr = new ExceptionAddrIO
54  })
55
56  val loadQueue = Module(new LoadQueue)
57  val storeQueue = Module(new StoreQueue)
58
59  // io.enq logic
60  // LSQ: send out canAccept when both load queue and store queue are ready
61  // Dispatch: send instructions to LSQ only when they are ready
62  io.enq.canAccept := loadQueue.io.enq.canAccept && storeQueue.io.enq.canAccept
63  loadQueue.io.enq.sqCanAccept := storeQueue.io.enq.canAccept
64  storeQueue.io.enq.lqCanAccept := loadQueue.io.enq.canAccept
65  for (i <- 0 until RenameWidth) {
66    val isStore = CommitType.lsInstIsStore(io.enq.req(i).bits.ctrl.commitType)
67
68    loadQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i) && !isStore
69    loadQueue.io.enq.req(i).valid  := !isStore && io.enq.req(i).valid
70    loadQueue.io.enq.req(i).bits  := io.enq.req(i).bits
71
72    storeQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i) && isStore
73    storeQueue.io.enq.req(i).valid :=  isStore && io.enq.req(i).valid
74    storeQueue.io.enq.req(i).bits := io.enq.req(i).bits
75
76    io.enq.resp(i).lqIdx := loadQueue.io.enq.resp(i)
77    io.enq.resp(i).sqIdx := storeQueue.io.enq.resp(i)
78  }
79
80  // load queue wiring
81  loadQueue.io.brqRedirect <> io.brqRedirect
82  loadQueue.io.loadIn <> io.loadIn
83  loadQueue.io.storeIn <> io.storeIn
84  loadQueue.io.ldout <> io.ldout
85  loadQueue.io.commits <> io.commits
86  loadQueue.io.rollback <> io.rollback
87  loadQueue.io.dcache <> io.dcache
88  loadQueue.io.roqDeqPtr <> io.roqDeqPtr
89  loadQueue.io.exceptionAddr.lsIdx := io.exceptionAddr.lsIdx
90  loadQueue.io.exceptionAddr.isStore := DontCare
91
92  // store queue wiring
93  // storeQueue.io <> DontCare
94  storeQueue.io.brqRedirect <> io.brqRedirect
95  storeQueue.io.storeIn <> io.storeIn
96  storeQueue.io.sbuffer <> io.sbuffer
97  storeQueue.io.mmioStout <> io.mmioStout
98  storeQueue.io.commits <> io.commits
99  storeQueue.io.roqDeqPtr <> io.roqDeqPtr
100  storeQueue.io.exceptionAddr.lsIdx := io.exceptionAddr.lsIdx
101  storeQueue.io.exceptionAddr.isStore := DontCare
102
103  loadQueue.io.load_s1 <> io.forward
104  storeQueue.io.forward <> io.forward // overlap forwardMask & forwardData, DO NOT CHANGE SEQUENCE
105
106  io.exceptionAddr.vaddr := Mux(io.exceptionAddr.isStore, storeQueue.io.exceptionAddr.vaddr, loadQueue.io.exceptionAddr.vaddr)
107
108  // naive uncache arbiter
109  val s_idle :: s_load :: s_store :: Nil = Enum(3)
110  val uncacheState = RegInit(s_idle)
111
112  switch(uncacheState){
113    is(s_idle){
114      when(io.uncache.req.fire()){
115        uncacheState := Mux(loadQueue.io.uncache.req.valid, s_load, s_store)
116      }
117    }
118    is(s_load){
119      when(io.uncache.resp.fire()){
120        uncacheState := s_idle
121      }
122    }
123    is(s_store){
124      when(io.uncache.resp.fire()){
125        uncacheState := s_idle
126      }
127    }
128  }
129
130  loadQueue.io.uncache := DontCare
131  storeQueue.io.uncache := DontCare
132  loadQueue.io.uncache.resp.valid := false.B
133  storeQueue.io.uncache.resp.valid := false.B
134  when(loadQueue.io.uncache.req.valid){
135    io.uncache.req <> loadQueue.io.uncache.req
136  }.otherwise{
137    io.uncache.req <> storeQueue.io.uncache.req
138  }
139  when(uncacheState === s_load){
140    io.uncache.resp <> loadQueue.io.uncache.resp
141  }.otherwise{
142    io.uncache.resp <> storeQueue.io.uncache.resp
143  }
144
145  assert(!(loadQueue.io.uncache.req.valid && storeQueue.io.uncache.req.valid))
146  assert(!(loadQueue.io.uncache.resp.valid && storeQueue.io.uncache.resp.valid))
147  assert(!((loadQueue.io.uncache.resp.valid || storeQueue.io.uncache.resp.valid) && uncacheState === s_idle))
148
149}
150