1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.cache._ 25import xiangshan.cache.{DCacheWordIO, DCacheLineIO, MemoryOpConstants} 26import xiangshan.cache.mmu.{TlbRequestIO} 27import xiangshan.mem._ 28import xiangshan.backend.rob.RobLsqIO 29 30class ExceptionAddrIO(implicit p: Parameters) extends XSBundle { 31 val isStore = Input(Bool()) 32 val vaddr = Output(UInt(VAddrBits.W)) 33} 34 35class FwdEntry extends Bundle { 36 val validFast = Bool() // validFast is generated the same cycle with query 37 val valid = Bool() // valid is generated 1 cycle after query request 38 val data = UInt(8.W) // data is generated 1 cycle after query request 39} 40 41// inflight miss block reqs 42class InflightBlockInfo(implicit p: Parameters) extends XSBundle { 43 val block_addr = UInt(PAddrBits.W) 44 val valid = Bool() 45} 46 47class LsqEnqIO(implicit p: Parameters) extends XSBundle { 48 val canAccept = Output(Bool()) 49 val needAlloc = Vec(exuParameters.LsExuCnt, Input(UInt(2.W))) 50 val req = Vec(exuParameters.LsExuCnt, Flipped(ValidIO(new MicroOp))) 51 val resp = Vec(exuParameters.LsExuCnt, Output(new LSIdx)) 52} 53 54// Load / Store Queue Wrapper for XiangShan Out of Order LSU 55class LsqWrappper(implicit p: Parameters) extends XSModule with HasDCacheParameters { 56 val io = IO(new Bundle() { 57 val hartId = Input(UInt(8.W)) 58 val enq = new LsqEnqIO 59 val brqRedirect = Flipped(ValidIO(new Redirect)) 60 val loadIn = Vec(LoadPipelineWidth, Flipped(Valid(new LsPipelineBundle))) 61 val storeIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) 62 val storeInRe = Vec(StorePipelineWidth, Input(new LsPipelineBundle())) 63 val storeDataIn = Vec(StorePipelineWidth, Flipped(Valid(new StoreDataBundle))) // store data, send to sq from rs 64 val loadDataForwarded = Vec(LoadPipelineWidth, Input(Bool())) 65 val needReplayFromRS = Vec(LoadPipelineWidth, Input(Bool())) 66 val sbuffer = Vec(StorePipelineWidth, Decoupled(new DCacheWordReqWithVaddr)) 67 val ldout = Vec(2, DecoupledIO(new ExuOutput)) // writeback int load 68 val mmioStout = DecoupledIO(new ExuOutput) // writeback uncached store 69 val forward = Vec(LoadPipelineWidth, Flipped(new PipeLoadForwardQueryIO)) 70 val loadViolationQuery = Vec(LoadPipelineWidth, Flipped(new LoadViolationQueryIO)) 71 val rob = Flipped(new RobLsqIO) 72 val rollback = Output(Valid(new Redirect)) 73 val dcache = Flipped(ValidIO(new Refill)) 74 val release = Flipped(ValidIO(new Release)) 75 val uncache = new DCacheWordIO 76 val exceptionAddr = new ExceptionAddrIO 77 val sqempty = Output(Bool()) 78 val issuePtrExt = Output(new SqPtr) 79 val sqFull = Output(Bool()) 80 val lqFull = Output(Bool()) 81 }) 82 83 val loadQueue = Module(new LoadQueue) 84 val storeQueue = Module(new StoreQueue) 85 86 storeQueue.io.hartId := io.hartId 87 88 // io.enq logic 89 // LSQ: send out canAccept when both load queue and store queue are ready 90 // Dispatch: send instructions to LSQ only when they are ready 91 io.enq.canAccept := loadQueue.io.enq.canAccept && storeQueue.io.enq.canAccept 92 loadQueue.io.enq.sqCanAccept := storeQueue.io.enq.canAccept 93 storeQueue.io.enq.lqCanAccept := loadQueue.io.enq.canAccept 94 for (i <- io.enq.req.indices) { 95 loadQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(0) 96 loadQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(0) && io.enq.req(i).valid 97 loadQueue.io.enq.req(i).bits := io.enq.req(i).bits 98 loadQueue.io.enq.req(i).bits.sqIdx := storeQueue.io.enq.resp(i) 99 100 storeQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(1) 101 storeQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(1) && io.enq.req(i).valid 102 storeQueue.io.enq.req(i).bits := io.enq.req(i).bits 103 storeQueue.io.enq.req(i).bits := io.enq.req(i).bits 104 storeQueue.io.enq.req(i).bits.lqIdx := loadQueue.io.enq.resp(i) 105 106 io.enq.resp(i).lqIdx := loadQueue.io.enq.resp(i) 107 io.enq.resp(i).sqIdx := storeQueue.io.enq.resp(i) 108 } 109 110 // load queue wiring 111 loadQueue.io.brqRedirect <> io.brqRedirect 112 loadQueue.io.loadIn <> io.loadIn 113 loadQueue.io.storeIn <> io.storeIn 114 loadQueue.io.loadDataForwarded <> io.loadDataForwarded 115 loadQueue.io.needReplayFromRS <> io.needReplayFromRS 116 loadQueue.io.ldout <> io.ldout 117 loadQueue.io.rob <> io.rob 118 loadQueue.io.rollback <> io.rollback 119 loadQueue.io.dcache <> io.dcache 120 loadQueue.io.release <> io.release 121 loadQueue.io.exceptionAddr.isStore := DontCare 122 123 // store queue wiring 124 // storeQueue.io <> DontCare 125 storeQueue.io.brqRedirect <> io.brqRedirect 126 storeQueue.io.storeIn <> io.storeIn 127 storeQueue.io.storeInRe <> io.storeInRe 128 storeQueue.io.storeDataIn <> io.storeDataIn 129 storeQueue.io.sbuffer <> io.sbuffer 130 storeQueue.io.mmioStout <> io.mmioStout 131 storeQueue.io.rob <> io.rob 132 storeQueue.io.exceptionAddr.isStore := DontCare 133 storeQueue.io.issuePtrExt <> io.issuePtrExt 134 135 loadQueue.io.load_s1 <> io.forward 136 storeQueue.io.forward <> io.forward // overlap forwardMask & forwardData, DO NOT CHANGE SEQUENCE 137 138 loadQueue.io.loadViolationQuery <> io.loadViolationQuery 139 140 storeQueue.io.sqempty <> io.sqempty 141 142 // rob commits for lsq is delayed for two cycles, which causes the delayed update for deqPtr in lq/sq 143 // s0: commit 144 // s1: exception find 145 // s2: exception triggered 146 // s3: ptr updated & new address 147 // address will be used at the next cycle after exception is triggered 148 io.exceptionAddr.vaddr := Mux(RegNext(io.exceptionAddr.isStore), storeQueue.io.exceptionAddr.vaddr, loadQueue.io.exceptionAddr.vaddr) 149 150 // naive uncache arbiter 151 val s_idle :: s_load :: s_store :: Nil = Enum(3) 152 val pendingstate = RegInit(s_idle) 153 154 switch(pendingstate){ 155 is(s_idle){ 156 when(io.uncache.req.fire()){ 157 pendingstate := Mux(loadQueue.io.uncache.req.valid, s_load, s_store) 158 } 159 } 160 is(s_load){ 161 when(io.uncache.resp.fire()){ 162 pendingstate := s_idle 163 } 164 } 165 is(s_store){ 166 when(io.uncache.resp.fire()){ 167 pendingstate := s_idle 168 } 169 } 170 } 171 172 loadQueue.io.uncache := DontCare 173 storeQueue.io.uncache := DontCare 174 loadQueue.io.uncache.resp.valid := false.B 175 storeQueue.io.uncache.resp.valid := false.B 176 when(loadQueue.io.uncache.req.valid){ 177 io.uncache.req <> loadQueue.io.uncache.req 178 }.otherwise{ 179 io.uncache.req <> storeQueue.io.uncache.req 180 } 181 when(pendingstate === s_load){ 182 io.uncache.resp <> loadQueue.io.uncache.resp 183 }.otherwise{ 184 io.uncache.resp <> storeQueue.io.uncache.resp 185 } 186 187 assert(!(loadQueue.io.uncache.req.valid && storeQueue.io.uncache.req.valid)) 188 assert(!(loadQueue.io.uncache.resp.valid && storeQueue.io.uncache.resp.valid)) 189 assert(!((loadQueue.io.uncache.resp.valid || storeQueue.io.uncache.resp.valid) && pendingstate === s_idle)) 190 191 io.lqFull := loadQueue.io.lqFull 192 io.sqFull := storeQueue.io.sqFull 193 194 val ldq_perf = loadQueue.perfEvents.map(_._1).zip(loadQueue.perfinfo.perfEvents.perf_events) 195 val stq_perf = storeQueue.perfEvents.map(_._1).zip(storeQueue.perfinfo.perfEvents.perf_events) 196 val perfEvents = ldq_perf ++ stq_perf 197 val perf_list = storeQueue.perfinfo.perfEvents.perf_events ++ loadQueue.perfinfo.perfEvents.perf_events 198 val perfinfo = IO(new Bundle(){ 199 val perfEvents = Output(new PerfEventsBundle(perf_list.length)) 200 }) 201 perfinfo.perfEvents.perf_events := perf_list 202} 203