1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: 9* http://license.coscl.org.cn/MulanPSL2 10* 11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14* 15* See the Mulan PSL v2 for more details. 16***************************************************************************************/ 17 18package xiangshan.mem 19 20 21import org.chipsalliance.cde.config.Parameters 22import chisel3._ 23import chisel3.util._ 24import utility._ 25import utils._ 26import xiangshan._ 27import xiangshan.backend.Bundles.{DynInst, MemExuInput} 28import xiangshan.backend.rob.RobPtr 29import xiangshan.cache._ 30import xiangshan.backend.fu.FenceToSbuffer 31import xiangshan.cache.wpu.ReplayCarry 32import xiangshan.mem.prefetch.PrefetchReqBundle 33import math._ 34 35object genWmask { 36 def apply(addr: UInt, sizeEncode: UInt): UInt = { 37 (LookupTree(sizeEncode, List( 38 "b00".U -> 0x1.U, //0001 << addr(2:0) 39 "b01".U -> 0x3.U, //0011 40 "b10".U -> 0xf.U, //1111 41 "b11".U -> 0xff.U //11111111 42 )) << addr(2, 0)).asUInt 43 } 44} 45 46object genVWmask { 47 def apply(addr: UInt, sizeEncode: UInt): UInt = { 48 (LookupTree(sizeEncode, List( 49 "b00".U -> 0x1.U, //0001 << addr(2:0) 50 "b01".U -> 0x3.U, //0011 51 "b10".U -> 0xf.U, //1111 52 "b11".U -> 0xff.U //11111111 53 )) << addr(3, 0)).asUInt 54 } 55} 56 57object genWdata { 58 def apply(data: UInt, sizeEncode: UInt): UInt = { 59 LookupTree(sizeEncode, List( 60 "b00".U -> Fill(16, data(7, 0)), 61 "b01".U -> Fill(8, data(15, 0)), 62 "b10".U -> Fill(4, data(31, 0)), 63 "b11".U -> Fill(2, data(63,0)) 64 )) 65 } 66} 67 68object shiftDataToLow { 69 def apply(addr: UInt,data : UInt): UInt = { 70 Mux(addr(3), (data >> 64).asUInt,data) 71 } 72} 73object shiftMaskToLow { 74 def apply(addr: UInt,mask: UInt): UInt = { 75 Mux(addr(3),(mask >> 8).asUInt,mask) 76 } 77} 78 79class LsPipelineBundle(implicit p: Parameters) extends XSBundle 80 with HasDCacheParameters 81 with HasVLSUParameters { 82 val uop = new DynInst 83 val vaddr = UInt(VAddrBits.W) 84 val paddr = UInt(PAddrBits.W) 85 val gpaddr = UInt(GPAddrBits.W) 86 // val func = UInt(6.W) 87 val mask = UInt((VLEN/8).W) 88 val data = UInt((VLEN+1).W) 89 val wlineflag = Bool() // store write the whole cache line 90 91 val miss = Bool() 92 val tlbMiss = Bool() 93 val ptwBack = Bool() 94 val af = Bool() 95 val mmio = Bool() 96 val atomic = Bool() 97 98 val forwardMask = Vec(VLEN/8, Bool()) 99 val forwardData = Vec(VLEN/8, UInt(8.W)) 100 101 // prefetch 102 val isPrefetch = Bool() 103 val isHWPrefetch = Bool() 104 def isSWPrefetch = isPrefetch && !isHWPrefetch 105 106 // misalignBuffer 107 val isFrmMisAlignBuf = Bool() 108 109 // vector 110 val isvec = Bool() 111 val isLastElem = Bool() 112 val is128bit = Bool() 113 val uop_unit_stride_fof = Bool() 114 val usSecondInv = Bool() 115 val elemIdx = UInt(elemIdxBits.W) 116 val alignedType = UInt(alignTypeBits.W) 117 val mbIndex = UInt(max(vlmBindexBits, vsmBindexBits).W) 118 // val rob_idx_valid = Vec(2,Bool()) 119 // val inner_idx = Vec(2,UInt(3.W)) 120 // val rob_idx = Vec(2,new RobPtr) 121 val reg_offset = UInt(vOffsetBits.W) 122 val elemIdxInsideVd = UInt(elemIdxBits.W) 123 // val offset = Vec(2,UInt(4.W)) 124 val vecActive = Bool() // 1: vector active element or scala mem operation, 0: vector not active element 125 val is_first_ele = Bool() 126 // val flowPtr = new VlflowPtr() // VLFlowQueue ptr 127 // val sflowPtr = new VsFlowPtr() // VSFlowQueue ptr 128 129 // For debug usage 130 val isFirstIssue = Bool() 131 val hasROBEntry = Bool() 132 133 // For load replay 134 val isLoadReplay = Bool() 135 val isFastPath = Bool() 136 val isFastReplay = Bool() 137 val replayCarry = new ReplayCarry(nWays) 138 139 // For dcache miss load 140 val mshrid = UInt(log2Up(cfg.nMissEntries).W) 141 val handledByMSHR = Bool() 142 val replacementUpdated = Bool() 143 val missDbUpdated = Bool() 144 145 val forward_tlDchannel = Bool() 146 val dcacheRequireReplay = Bool() 147 val delayedLoadError = Bool() 148 val lateKill = Bool() 149 val feedbacked = Bool() 150 val ldCancel = ValidUndirectioned(UInt(log2Ceil(LoadPipelineWidth).W)) 151 // loadQueueReplay index. 152 val schedIndex = UInt(log2Up(LoadQueueReplaySize).W) 153 // hardware prefetch and fast replay no need to query tlb 154 val tlbNoQuery = Bool() 155} 156 157class LdPrefetchTrainBundle(implicit p: Parameters) extends LsPipelineBundle { 158 val meta_prefetch = UInt(L1PfSourceBits.W) 159 val meta_access = Bool() 160 161 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false, enable: Bool = true.B) = { 162 if (latch) vaddr := RegEnable(input.vaddr, enable) else vaddr := input.vaddr 163 if (latch) paddr := RegEnable(input.paddr, enable) else paddr := input.paddr 164 if (latch) gpaddr := RegEnable(input.gpaddr, enable) else gpaddr := input.gpaddr 165 if (latch) mask := RegEnable(input.mask, enable) else mask := input.mask 166 if (latch) data := RegEnable(input.data, enable) else data := input.data 167 if (latch) uop := RegEnable(input.uop, enable) else uop := input.uop 168 if (latch) wlineflag := RegEnable(input.wlineflag, enable) else wlineflag := input.wlineflag 169 if (latch) miss := RegEnable(input.miss, enable) else miss := input.miss 170 if (latch) tlbMiss := RegEnable(input.tlbMiss, enable) else tlbMiss := input.tlbMiss 171 if (latch) ptwBack := RegEnable(input.ptwBack, enable) else ptwBack := input.ptwBack 172 if (latch) af := RegEnable(input.af, enable) else af := input.af 173 if (latch) mmio := RegEnable(input.mmio, enable) else mmio := input.mmio 174 if (latch) forwardMask := RegEnable(input.forwardMask, enable) else forwardMask := input.forwardMask 175 if (latch) forwardData := RegEnable(input.forwardData, enable) else forwardData := input.forwardData 176 if (latch) isPrefetch := RegEnable(input.isPrefetch, enable) else isPrefetch := input.isPrefetch 177 if (latch) isHWPrefetch := RegEnable(input.isHWPrefetch, enable) else isHWPrefetch := input.isHWPrefetch 178 if (latch) isFrmMisAlignBuf := RegEnable(input.isFrmMisAlignBuf, enable) else isFrmMisAlignBuf := input.isFrmMisAlignBuf 179 if (latch) isFirstIssue := RegEnable(input.isFirstIssue, enable) else isFirstIssue := input.isFirstIssue 180 if (latch) hasROBEntry := RegEnable(input.hasROBEntry, enable) else hasROBEntry := input.hasROBEntry 181 if (latch) dcacheRequireReplay := RegEnable(input.dcacheRequireReplay, enable) else dcacheRequireReplay := input.dcacheRequireReplay 182 if (latch) schedIndex := RegEnable(input.schedIndex, enable) else schedIndex := input.schedIndex 183 if (latch) tlbNoQuery := RegEnable(input.tlbNoQuery, enable) else tlbNoQuery := input.tlbNoQuery 184 if (latch) isvec := RegEnable(input.isvec, enable) else isvec := input.isvec 185 if (latch) isLastElem := RegEnable(input.isLastElem, enable) else isLastElem := input.isLastElem 186 if (latch) is128bit := RegEnable(input.is128bit, enable) else is128bit := input.is128bit 187 if (latch) vecActive := RegEnable(input.vecActive, enable) else vecActive := input.vecActive 188 if (latch) is_first_ele := RegEnable(input.is_first_ele, enable) else is_first_ele := input.is_first_ele 189 if (latch) uop_unit_stride_fof := RegEnable(input.uop_unit_stride_fof, enable) else uop_unit_stride_fof := input.uop_unit_stride_fof 190 if (latch) usSecondInv := RegEnable(input.usSecondInv, enable) else usSecondInv := input.usSecondInv 191 if (latch) reg_offset := RegEnable(input.reg_offset, enable) else reg_offset := input.reg_offset 192 if (latch) elemIdx := RegEnable(input.elemIdx, enable) else elemIdx := input.elemIdx 193 if (latch) alignedType := RegEnable(input.alignedType, enable) else alignedType := input.alignedType 194 if (latch) mbIndex := RegEnable(input.mbIndex, enable) else mbIndex := input.mbIndex 195 if (latch) elemIdxInsideVd := RegEnable(input.elemIdxInsideVd, enable) else elemIdxInsideVd := input.elemIdxInsideVd 196 // if (latch) flowPtr := RegEnable(input.flowPtr, enable) else flowPtr := input.flowPtr 197 // if (latch) sflowPtr := RegEnable(input.sflowPtr, enable) else sflowPtr := input.sflowPtr 198 199 meta_prefetch := DontCare 200 meta_access := DontCare 201 forward_tlDchannel := DontCare 202 mshrid := DontCare 203 replayCarry := DontCare 204 atomic := DontCare 205 isLoadReplay := DontCare 206 isFastPath := DontCare 207 isFastReplay := DontCare 208 handledByMSHR := DontCare 209 replacementUpdated := DontCare 210 missDbUpdated := DontCare 211 delayedLoadError := DontCare 212 lateKill := DontCare 213 feedbacked := DontCare 214 ldCancel := DontCare 215 } 216 217 def asPrefetchReqBundle(): PrefetchReqBundle = { 218 val res = Wire(new PrefetchReqBundle) 219 res.vaddr := this.vaddr 220 res.paddr := this.paddr 221 res.pc := this.uop.pc 222 res.miss := this.miss 223 res.pfHitStream := isFromStream(this.meta_prefetch) 224 225 res 226 } 227} 228 229class StPrefetchTrainBundle(implicit p: Parameters) extends LdPrefetchTrainBundle {} 230 231class LqWriteBundle(implicit p: Parameters) extends LsPipelineBundle { 232 // load inst replay informations 233 val rep_info = new LoadToLsqReplayIO 234 // queue entry data, except flag bits, will be updated if writeQueue is true, 235 // valid bit in LqWriteBundle will be ignored 236 val data_wen_dup = Vec(6, Bool()) // dirty reg dup 237 238 239 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false, enable: Bool = true.B) = { 240 if(latch) vaddr := RegEnable(input.vaddr, enable) else vaddr := input.vaddr 241 if(latch) paddr := RegEnable(input.paddr, enable) else paddr := input.paddr 242 if(latch) gpaddr := RegEnable(input.gpaddr, enable) else gpaddr := input.gpaddr 243 if(latch) mask := RegEnable(input.mask, enable) else mask := input.mask 244 if(latch) data := RegEnable(input.data, enable) else data := input.data 245 if(latch) uop := RegEnable(input.uop, enable) else uop := input.uop 246 if(latch) wlineflag := RegEnable(input.wlineflag, enable) else wlineflag := input.wlineflag 247 if(latch) miss := RegEnable(input.miss, enable) else miss := input.miss 248 if(latch) tlbMiss := RegEnable(input.tlbMiss, enable) else tlbMiss := input.tlbMiss 249 if(latch) ptwBack := RegEnable(input.ptwBack, enable) else ptwBack := input.ptwBack 250 if(latch) mmio := RegEnable(input.mmio, enable) else mmio := input.mmio 251 if(latch) atomic := RegEnable(input.atomic, enable) else atomic := input.atomic 252 if(latch) forwardMask := RegEnable(input.forwardMask, enable) else forwardMask := input.forwardMask 253 if(latch) forwardData := RegEnable(input.forwardData, enable) else forwardData := input.forwardData 254 if(latch) isPrefetch := RegEnable(input.isPrefetch, enable) else isPrefetch := input.isPrefetch 255 if(latch) isHWPrefetch := RegEnable(input.isHWPrefetch, enable) else isHWPrefetch := input.isHWPrefetch 256 if(latch) isFrmMisAlignBuf := RegEnable(input.isFrmMisAlignBuf, enable) else isFrmMisAlignBuf := input.isFrmMisAlignBuf 257 if(latch) isFirstIssue := RegEnable(input.isFirstIssue, enable) else isFirstIssue := input.isFirstIssue 258 if(latch) hasROBEntry := RegEnable(input.hasROBEntry, enable) else hasROBEntry := input.hasROBEntry 259 if(latch) isLoadReplay := RegEnable(input.isLoadReplay, enable) else isLoadReplay := input.isLoadReplay 260 if(latch) isFastPath := RegEnable(input.isFastPath, enable) else isFastPath := input.isFastPath 261 if(latch) isFastReplay := RegEnable(input.isFastReplay, enable) else isFastReplay := input.isFastReplay 262 if(latch) mshrid := RegEnable(input.mshrid, enable) else mshrid := input.mshrid 263 if(latch) forward_tlDchannel := RegEnable(input.forward_tlDchannel, enable) else forward_tlDchannel := input.forward_tlDchannel 264 if(latch) replayCarry := RegEnable(input.replayCarry, enable) else replayCarry := input.replayCarry 265 if(latch) dcacheRequireReplay := RegEnable(input.dcacheRequireReplay, enable) else dcacheRequireReplay := input.dcacheRequireReplay 266 if(latch) schedIndex := RegEnable(input.schedIndex, enable) else schedIndex := input.schedIndex 267 if(latch) handledByMSHR := RegEnable(input.handledByMSHR, enable) else handledByMSHR := input.handledByMSHR 268 if(latch) replacementUpdated := RegEnable(input.replacementUpdated, enable) else replacementUpdated := input.replacementUpdated 269 if(latch) missDbUpdated := RegEnable(input.missDbUpdated, enable) else missDbUpdated := input.missDbUpdated 270 if(latch) delayedLoadError := RegEnable(input.delayedLoadError, enable) else delayedLoadError := input.delayedLoadError 271 if(latch) lateKill := RegEnable(input.lateKill, enable) else lateKill := input.lateKill 272 if(latch) feedbacked := RegEnable(input.feedbacked, enable) else feedbacked := input.feedbacked 273 if(latch) isvec := RegEnable(input.isvec, enable) else isvec := input.isvec 274 if(latch) is128bit := RegEnable(input.is128bit, enable) else is128bit := input.is128bit 275 if(latch) vecActive := RegEnable(input.vecActive, enable) else vecActive := input.vecActive 276 if(latch) uop_unit_stride_fof := RegEnable(input.uop_unit_stride_fof, enable) else uop_unit_stride_fof := input.uop_unit_stride_fof 277 if(latch) reg_offset := RegEnable(input.reg_offset, enable) else reg_offset := input.reg_offset 278 if(latch) mbIndex := RegEnable(input.mbIndex, enable) else mbIndex := input.mbIndex 279 if(latch) elemIdxInsideVd := RegEnable(input.elemIdxInsideVd, enable) else elemIdxInsideVd := input.elemIdxInsideVd 280 281 rep_info := DontCare 282 data_wen_dup := DontCare 283 } 284} 285 286class SqWriteBundle(implicit p: Parameters) extends LsPipelineBundle { 287 val need_rep = Bool() 288} 289 290class LoadForwardQueryIO(implicit p: Parameters) extends XSBundle { 291 val vaddr = Output(UInt(VAddrBits.W)) 292 val paddr = Output(UInt(PAddrBits.W)) 293 val mask = Output(UInt((VLEN/8).W)) 294 val uop = Output(new DynInst) // for replay 295 val pc = Output(UInt(VAddrBits.W)) //for debug 296 val valid = Output(Bool()) 297 298 val forwardMaskFast = Input(Vec((VLEN/8), Bool())) // resp to load_s1 299 val forwardMask = Input(Vec((VLEN/8), Bool())) // resp to load_s2 300 val forwardData = Input(Vec((VLEN/8), UInt(8.W))) // resp to load_s2 301 302 // val lqIdx = Output(UInt(LoadQueueIdxWidth.W)) 303 val sqIdx = Output(new SqPtr) 304 305 // dataInvalid suggests store to load forward found forward should happen, 306 // but data is not available for now. If dataInvalid, load inst should 307 // be replayed from RS. Feedback type should be RSFeedbackType.dataInvalid 308 val dataInvalid = Input(Bool()) // Addr match, but data is not valid for now 309 310 // matchInvalid suggests in store to load forward logic, paddr cam result does 311 // to equal to vaddr cam result. If matchInvalid, a microarchitectural exception 312 // should be raised to flush SQ and committed sbuffer. 313 val matchInvalid = Input(Bool()) // resp to load_s2 314 315 // addrInvalid suggests store to load forward found forward should happen, 316 // but address (SSID) is not available for now. If addrInvalid, load inst should 317 // be replayed from RS. Feedback type should be RSFeedbackType.addrInvalid 318 val addrInvalid = Input(Bool()) 319} 320 321// LoadForwardQueryIO used in load pipeline 322// 323// Difference between PipeLoadForwardQueryIO and LoadForwardQueryIO: 324// PipeIO use predecoded sqIdxMask for better forward timing 325class PipeLoadForwardQueryIO(implicit p: Parameters) extends LoadForwardQueryIO { 326 // val sqIdx = Output(new SqPtr) // for debug, should not be used in pipeline for timing reasons 327 // sqIdxMask is calcuated in earlier stage for better timing 328 val sqIdxMask = Output(UInt(StoreQueueSize.W)) 329 330 // dataInvalid: addr match, but data is not valid for now 331 val dataInvalidFast = Input(Bool()) // resp to load_s1 332 // val dataInvalid = Input(Bool()) // resp to load_s2 333 val dataInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 334 val addrInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 335} 336 337// Query load queue for ld-ld violation 338// 339// Req should be send in load_s1 340// Resp will be generated 1 cycle later 341// 342// Note that query req may be !ready, as dcache is releasing a block 343// If it happens, a replay from rs is needed. 344class LoadNukeQueryReq(implicit p: Parameters) extends XSBundle { // provide lqIdx 345 val uop = new DynInst 346 // mask: load's data mask. 347 val mask = UInt((VLEN/8).W) 348 349 // paddr: load's paddr. 350 val paddr = UInt(PAddrBits.W) 351 // dataInvalid: load data is invalid. 352 val data_valid = Bool() 353} 354 355class LoadNukeQueryResp(implicit p: Parameters) extends XSBundle { 356 // rep_frm_fetch: ld-ld violation check success, replay from fetch. 357 val rep_frm_fetch = Bool() 358} 359 360class LoadNukeQueryIO(implicit p: Parameters) extends XSBundle { 361 val req = Decoupled(new LoadNukeQueryReq) 362 val resp = Flipped(Valid(new LoadNukeQueryResp)) 363 val revoke = Output(Bool()) 364} 365 366class StoreNukeQueryIO(implicit p: Parameters) extends XSBundle { 367 // robIdx: Requestor's (a store instruction) rob index for match logic. 368 val robIdx = new RobPtr 369 370 // paddr: requestor's (a store instruction) physical address for match logic. 371 val paddr = UInt(PAddrBits.W) 372 373 // mask: requestor's (a store instruction) data width mask for match logic. 374 val mask = UInt((VLEN/8).W) 375 376 // matchLine: if store is vector 128-bits, load unit need to compare 128-bits vaddr. 377 val matchLine = Bool() 378} 379 380class StoreMaBufToSqControlIO(implicit p: Parameters) extends XSBundle { 381 // from storeMisalignBuffer to storeQueue, control it's sbuffer write 382 val control = Output(new XSBundle { 383 // control sq to write-into sb 384 val writeSb = Bool() 385 val wdata = UInt(VLEN.W) 386 val wmask = UInt((VLEN / 8).W) 387 val paddr = UInt(PAddrBits.W) 388 val vaddr = UInt(VAddrBits.W) 389 val last = Bool() 390 val hasException = Bool() 391 // remove this entry in sq 392 val removeSq = Bool() 393 }) 394 // from storeQueue to storeMisalignBuffer, provide detail info of this store 395 val storeInfo = Input(new XSBundle { 396 val data = UInt(VLEN.W) 397 // is the data of the unaligned store ready at sq? 398 val dataReady = Bool() 399 // complete a data transfer from sq to sb 400 val completeSbTrans = Bool() 401 }) 402} 403 404// Store byte valid mask write bundle 405// 406// Store byte valid mask write to SQ takes 2 cycles 407class StoreMaskBundle(implicit p: Parameters) extends XSBundle { 408 val sqIdx = new SqPtr 409 val mask = UInt((VLEN/8).W) 410} 411 412class LoadDataFromDcacheBundle(implicit p: Parameters) extends DCacheBundle { 413 // old dcache: optimize data sram read fanout 414 // val bankedDcacheData = Vec(DCacheBanks, UInt(64.W)) 415 // val bank_oh = UInt(DCacheBanks.W) 416 417 // new dcache 418 val respDcacheData = UInt(VLEN.W) 419 val forwardMask = Vec(VLEN/8, Bool()) 420 val forwardData = Vec(VLEN/8, UInt(8.W)) 421 val uop = new DynInst // for data selection, only fwen and fuOpType are used 422 val addrOffset = UInt(4.W) // for data selection 423 424 // forward tilelink D channel 425 val forward_D = Bool() 426 val forwardData_D = Vec(VLEN/8, UInt(8.W)) 427 428 // forward mshr data 429 val forward_mshr = Bool() 430 val forwardData_mshr = Vec(VLEN/8, UInt(8.W)) 431 432 val forward_result_valid = Bool() 433 434 def mergeTLData(): UInt = { 435 // merge TL D or MSHR data at load s2 436 val dcache_data = respDcacheData 437 val use_D = forward_D && forward_result_valid 438 val use_mshr = forward_mshr && forward_result_valid 439 Mux( 440 use_D || use_mshr, 441 Mux( 442 use_D, 443 forwardData_D.asUInt, 444 forwardData_mshr.asUInt 445 ), 446 dcache_data 447 ) 448 } 449 450 def mergeLsqFwdData(dcacheData: UInt): UInt = { 451 // merge dcache and lsq forward data at load s3 452 val rdataVec = VecInit((0 until VLEN / 8).map(j => 453 Mux(forwardMask(j), forwardData(j), dcacheData(8*(j+1)-1, 8*j)) 454 )) 455 rdataVec.asUInt 456 } 457} 458 459// Load writeback data from load queue (refill) 460class LoadDataFromLQBundle(implicit p: Parameters) extends XSBundle { 461 val lqData = UInt(64.W) // load queue has merged data 462 val uop = new DynInst // for data selection, only fwen and fuOpType are used 463 val addrOffset = UInt(3.W) // for data selection 464 465 def mergedData(): UInt = { 466 lqData 467 } 468} 469 470// Bundle for load / store wait waking up 471class MemWaitUpdateReq(implicit p: Parameters) extends XSBundle { 472 val robIdx = Vec(backendParams.StaExuCnt, ValidIO(new RobPtr)) 473 val sqIdx = Vec(backendParams.StdCnt, ValidIO(new SqPtr)) 474} 475 476object AddPipelineReg { 477 class PipelineRegModule[T <: Data](gen: T) extends Module { 478 val io = IO(new Bundle() { 479 val in = Flipped(DecoupledIO(gen.cloneType)) 480 val out = DecoupledIO(gen.cloneType) 481 val isFlush = Input(Bool()) 482 }) 483 484 val valid = RegInit(false.B) 485 valid.suggestName("pipeline_reg_valid") 486 when (io.out.fire) { valid := false.B } 487 when (io.in.fire) { valid := true.B } 488 when (io.isFlush) { valid := false.B } 489 490 io.in.ready := !valid || io.out.ready 491 io.out.bits := RegEnable(io.in.bits, io.in.fire) 492 io.out.valid := valid //&& !isFlush 493 } 494 495 def apply[T <: Data] 496 (left: DecoupledIO[T], right: DecoupledIO[T], isFlush: Bool, 497 moduleName: Option[String] = None 498 ): Unit = { 499 val pipelineReg = Module(new PipelineRegModule[T](left.bits.cloneType)) 500 if(moduleName.nonEmpty) pipelineReg.suggestName(moduleName.get) 501 pipelineReg.io.in <> left 502 right <> pipelineReg.io.out 503 pipelineReg.io.isFlush := isFlush 504 } 505}