1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: 9* http://license.coscl.org.cn/MulanPSL2 10* 11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14* 15* See the Mulan PSL v2 for more details. 16***************************************************************************************/ 17 18package xiangshan.mem 19 20 21import org.chipsalliance.cde.config.Parameters 22import chisel3._ 23import chisel3.util._ 24import utility._ 25import utils._ 26import xiangshan._ 27import xiangshan.backend.Bundles.{DynInst, MemExuInput} 28import xiangshan.backend.rob.RobPtr 29import xiangshan.cache._ 30import xiangshan.backend.fu.FenceToSbuffer 31import xiangshan.cache.wpu.ReplayCarry 32import xiangshan.mem.prefetch.PrefetchReqBundle 33import math._ 34 35object genWmask { 36 def apply(addr: UInt, sizeEncode: UInt): UInt = { 37 (LookupTree(sizeEncode, List( 38 "b00".U -> 0x1.U, //0001 << addr(2:0) 39 "b01".U -> 0x3.U, //0011 40 "b10".U -> 0xf.U, //1111 41 "b11".U -> 0xff.U //11111111 42 )) << addr(2, 0)).asUInt 43 } 44} 45 46object genVWmask { 47 def apply(addr: UInt, sizeEncode: UInt): UInt = { 48 (LookupTree(sizeEncode, List( 49 "b00".U -> 0x1.U, //0001 << addr(2:0) 50 "b01".U -> 0x3.U, //0011 51 "b10".U -> 0xf.U, //1111 52 "b11".U -> 0xff.U //11111111 53 )) << addr(3, 0)).asUInt 54 } 55} 56 57object genWdata { 58 def apply(data: UInt, sizeEncode: UInt): UInt = { 59 LookupTree(sizeEncode, List( 60 "b00".U -> Fill(16, data(7, 0)), 61 "b01".U -> Fill(8, data(15, 0)), 62 "b10".U -> Fill(4, data(31, 0)), 63 "b11".U -> Fill(2, data(63,0)) 64 )) 65 } 66} 67 68object shiftDataToLow { 69 def apply(addr: UInt,data : UInt): UInt = { 70 Mux(addr(3), (data >> 64).asUInt,data) 71 } 72} 73object shiftMaskToLow { 74 def apply(addr: UInt,mask: UInt): UInt = { 75 Mux(addr(3),(mask >> 8).asUInt,mask) 76 } 77} 78 79class LsPipelineBundle(implicit p: Parameters) extends XSBundle 80 with HasDCacheParameters 81 with HasVLSUParameters { 82 val uop = new DynInst 83 val vaddr = UInt(VAddrBits.W) 84 // For exception vaddr generate 85 val fullva = UInt(XLEN.W) 86 val vaNeedExt = Bool() 87 val isHyper = Bool() 88 val paddr = UInt(PAddrBits.W) 89 val gpaddr = UInt(XLEN.W) 90 val isForVSnonLeafPTE = Bool() 91 // val func = UInt(6.W) 92 val mask = UInt((VLEN/8).W) 93 val data = UInt((VLEN+1).W) 94 val wlineflag = Bool() // store write the whole cache line 95 96 val miss = Bool() 97 val tlbMiss = Bool() 98 val ptwBack = Bool() 99 val af = Bool() 100 val mmio = Bool() 101 val atomic = Bool() 102 103 val forwardMask = Vec(VLEN/8, Bool()) 104 val forwardData = Vec(VLEN/8, UInt(8.W)) 105 106 // prefetch 107 val isPrefetch = Bool() 108 val isHWPrefetch = Bool() 109 def isSWPrefetch = isPrefetch && !isHWPrefetch 110 111 // misalignBuffer 112 val isFrmMisAlignBuf = Bool() 113 114 // vector 115 val isvec = Bool() 116 val isLastElem = Bool() 117 val is128bit = Bool() 118 val uop_unit_stride_fof = Bool() 119 val usSecondInv = Bool() 120 val elemIdx = UInt(elemIdxBits.W) 121 val alignedType = UInt(alignTypeBits.W) 122 val mbIndex = UInt(max(vlmBindexBits, vsmBindexBits).W) 123 // val rob_idx_valid = Vec(2,Bool()) 124 // val inner_idx = Vec(2,UInt(3.W)) 125 // val rob_idx = Vec(2,new RobPtr) 126 val reg_offset = UInt(vOffsetBits.W) 127 val elemIdxInsideVd = UInt(elemIdxBits.W) 128 // val offset = Vec(2,UInt(4.W)) 129 val vecActive = Bool() // 1: vector active element or scala mem operation, 0: vector not active element 130 val is_first_ele = Bool() 131 val vecBaseVaddr = UInt(VAddrBits.W) 132 val vecVaddrOffset = UInt(VAddrBits.W) 133 val vecTriggerMask = UInt((VLEN/8).W) 134 // val flowPtr = new VlflowPtr() // VLFlowQueue ptr 135 // val sflowPtr = new VsFlowPtr() // VSFlowQueue ptr 136 137 // For debug usage 138 val isFirstIssue = Bool() 139 val hasROBEntry = Bool() 140 141 // For load replay 142 val isLoadReplay = Bool() 143 val isFastPath = Bool() 144 val isFastReplay = Bool() 145 val replayCarry = new ReplayCarry(nWays) 146 147 // For dcache miss load 148 val mshrid = UInt(log2Up(cfg.nMissEntries).W) 149 val handledByMSHR = Bool() 150 val replacementUpdated = Bool() 151 val missDbUpdated = Bool() 152 153 val forward_tlDchannel = Bool() 154 val dcacheRequireReplay = Bool() 155 val delayedLoadError = Bool() 156 val lateKill = Bool() 157 val feedbacked = Bool() 158 val ldCancel = ValidUndirectioned(UInt(log2Ceil(LoadPipelineWidth).W)) 159 // loadQueueReplay index. 160 val schedIndex = UInt(log2Up(LoadQueueReplaySize).W) 161 // hardware prefetch and fast replay no need to query tlb 162 val tlbNoQuery = Bool() 163} 164 165class LdPrefetchTrainBundle(implicit p: Parameters) extends LsPipelineBundle { 166 val meta_prefetch = UInt(L1PfSourceBits.W) 167 val meta_access = Bool() 168 169 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false, enable: Bool = true.B) = { 170 if (latch) vaddr := RegEnable(input.vaddr, enable) else vaddr := input.vaddr 171 if (latch) fullva := RegEnable(input.fullva, enable) else fullva := input.fullva 172 if (latch) vaNeedExt := RegEnable(input.vaNeedExt, enable) else vaNeedExt := input.vaNeedExt 173 if (latch) isHyper := RegEnable(input.isHyper, enable) else isHyper := input.isHyper 174 if (latch) paddr := RegEnable(input.paddr, enable) else paddr := input.paddr 175 if (latch) gpaddr := RegEnable(input.gpaddr, enable) else gpaddr := input.gpaddr 176 if (latch) isForVSnonLeafPTE := RegEnable(input.isForVSnonLeafPTE, enable) else isForVSnonLeafPTE := input.isForVSnonLeafPTE 177 if (latch) mask := RegEnable(input.mask, enable) else mask := input.mask 178 if (latch) data := RegEnable(input.data, enable) else data := input.data 179 if (latch) uop := RegEnable(input.uop, enable) else uop := input.uop 180 if (latch) wlineflag := RegEnable(input.wlineflag, enable) else wlineflag := input.wlineflag 181 if (latch) miss := RegEnable(input.miss, enable) else miss := input.miss 182 if (latch) tlbMiss := RegEnable(input.tlbMiss, enable) else tlbMiss := input.tlbMiss 183 if (latch) ptwBack := RegEnable(input.ptwBack, enable) else ptwBack := input.ptwBack 184 if (latch) af := RegEnable(input.af, enable) else af := input.af 185 if (latch) mmio := RegEnable(input.mmio, enable) else mmio := input.mmio 186 if (latch) forwardMask := RegEnable(input.forwardMask, enable) else forwardMask := input.forwardMask 187 if (latch) forwardData := RegEnable(input.forwardData, enable) else forwardData := input.forwardData 188 if (latch) isPrefetch := RegEnable(input.isPrefetch, enable) else isPrefetch := input.isPrefetch 189 if (latch) isHWPrefetch := RegEnable(input.isHWPrefetch, enable) else isHWPrefetch := input.isHWPrefetch 190 if (latch) isFrmMisAlignBuf := RegEnable(input.isFrmMisAlignBuf, enable) else isFrmMisAlignBuf := input.isFrmMisAlignBuf 191 if (latch) isFirstIssue := RegEnable(input.isFirstIssue, enable) else isFirstIssue := input.isFirstIssue 192 if (latch) hasROBEntry := RegEnable(input.hasROBEntry, enable) else hasROBEntry := input.hasROBEntry 193 if (latch) dcacheRequireReplay := RegEnable(input.dcacheRequireReplay, enable) else dcacheRequireReplay := input.dcacheRequireReplay 194 if (latch) schedIndex := RegEnable(input.schedIndex, enable) else schedIndex := input.schedIndex 195 if (latch) tlbNoQuery := RegEnable(input.tlbNoQuery, enable) else tlbNoQuery := input.tlbNoQuery 196 if (latch) isvec := RegEnable(input.isvec, enable) else isvec := input.isvec 197 if (latch) isLastElem := RegEnable(input.isLastElem, enable) else isLastElem := input.isLastElem 198 if (latch) is128bit := RegEnable(input.is128bit, enable) else is128bit := input.is128bit 199 if (latch) vecActive := RegEnable(input.vecActive, enable) else vecActive := input.vecActive 200 if (latch) is_first_ele := RegEnable(input.is_first_ele, enable) else is_first_ele := input.is_first_ele 201 if (latch) uop_unit_stride_fof := RegEnable(input.uop_unit_stride_fof, enable) else uop_unit_stride_fof := input.uop_unit_stride_fof 202 if (latch) usSecondInv := RegEnable(input.usSecondInv, enable) else usSecondInv := input.usSecondInv 203 if (latch) reg_offset := RegEnable(input.reg_offset, enable) else reg_offset := input.reg_offset 204 if (latch) elemIdx := RegEnable(input.elemIdx, enable) else elemIdx := input.elemIdx 205 if (latch) alignedType := RegEnable(input.alignedType, enable) else alignedType := input.alignedType 206 if (latch) mbIndex := RegEnable(input.mbIndex, enable) else mbIndex := input.mbIndex 207 if (latch) elemIdxInsideVd := RegEnable(input.elemIdxInsideVd, enable) else elemIdxInsideVd := input.elemIdxInsideVd 208 if (latch) vecBaseVaddr := RegEnable(input.vecBaseVaddr, enable) else vecBaseVaddr := input.vecBaseVaddr 209 if (latch) vecVaddrOffset := RegEnable(input.vecVaddrOffset, enable) else vecVaddrOffset := input.vecVaddrOffset 210 if (latch) vecTriggerMask := RegEnable(input.vecTriggerMask, enable) else vecTriggerMask := input.vecTriggerMask 211 // if (latch) flowPtr := RegEnable(input.flowPtr, enable) else flowPtr := input.flowPtr 212 // if (latch) sflowPtr := RegEnable(input.sflowPtr, enable) else sflowPtr := input.sflowPtr 213 214 meta_prefetch := DontCare 215 meta_access := DontCare 216 forward_tlDchannel := DontCare 217 mshrid := DontCare 218 replayCarry := DontCare 219 atomic := DontCare 220 isLoadReplay := DontCare 221 isFastPath := DontCare 222 isFastReplay := DontCare 223 handledByMSHR := DontCare 224 replacementUpdated := DontCare 225 missDbUpdated := DontCare 226 delayedLoadError := DontCare 227 lateKill := DontCare 228 feedbacked := DontCare 229 ldCancel := DontCare 230 } 231 232 def asPrefetchReqBundle(): PrefetchReqBundle = { 233 val res = Wire(new PrefetchReqBundle) 234 res.vaddr := this.vaddr 235 res.paddr := this.paddr 236 res.pc := this.uop.pc 237 res.miss := this.miss 238 res.pfHitStream := isFromStream(this.meta_prefetch) 239 240 res 241 } 242} 243 244class StPrefetchTrainBundle(implicit p: Parameters) extends LdPrefetchTrainBundle {} 245 246class LqWriteBundle(implicit p: Parameters) extends LsPipelineBundle { 247 // load inst replay informations 248 val rep_info = new LoadToLsqReplayIO 249 // queue entry data, except flag bits, will be updated if writeQueue is true, 250 // valid bit in LqWriteBundle will be ignored 251 val data_wen_dup = Vec(6, Bool()) // dirty reg dup 252 253 254 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false, enable: Bool = true.B) = { 255 if(latch) vaddr := RegEnable(input.vaddr, enable) else vaddr := input.vaddr 256 if(latch) fullva := RegEnable(input.fullva, enable) else fullva := input.fullva 257 if(latch) vaNeedExt := RegEnable(input.vaNeedExt, enable) else vaNeedExt := input.vaNeedExt 258 if(latch) isHyper := RegEnable(input.isHyper, enable) else isHyper := input.isHyper 259 if(latch) paddr := RegEnable(input.paddr, enable) else paddr := input.paddr 260 if(latch) gpaddr := RegEnable(input.gpaddr, enable) else gpaddr := input.gpaddr 261 if(latch) isForVSnonLeafPTE := RegEnable(input.isForVSnonLeafPTE, enable) else isForVSnonLeafPTE := input.isForVSnonLeafPTE 262 if(latch) mask := RegEnable(input.mask, enable) else mask := input.mask 263 if(latch) data := RegEnable(input.data, enable) else data := input.data 264 if(latch) uop := RegEnable(input.uop, enable) else uop := input.uop 265 if(latch) wlineflag := RegEnable(input.wlineflag, enable) else wlineflag := input.wlineflag 266 if(latch) miss := RegEnable(input.miss, enable) else miss := input.miss 267 if(latch) tlbMiss := RegEnable(input.tlbMiss, enable) else tlbMiss := input.tlbMiss 268 if(latch) ptwBack := RegEnable(input.ptwBack, enable) else ptwBack := input.ptwBack 269 if(latch) mmio := RegEnable(input.mmio, enable) else mmio := input.mmio 270 if(latch) atomic := RegEnable(input.atomic, enable) else atomic := input.atomic 271 if(latch) forwardMask := RegEnable(input.forwardMask, enable) else forwardMask := input.forwardMask 272 if(latch) forwardData := RegEnable(input.forwardData, enable) else forwardData := input.forwardData 273 if(latch) isPrefetch := RegEnable(input.isPrefetch, enable) else isPrefetch := input.isPrefetch 274 if(latch) isHWPrefetch := RegEnable(input.isHWPrefetch, enable) else isHWPrefetch := input.isHWPrefetch 275 if(latch) isFrmMisAlignBuf := RegEnable(input.isFrmMisAlignBuf, enable) else isFrmMisAlignBuf := input.isFrmMisAlignBuf 276 if(latch) isFirstIssue := RegEnable(input.isFirstIssue, enable) else isFirstIssue := input.isFirstIssue 277 if(latch) hasROBEntry := RegEnable(input.hasROBEntry, enable) else hasROBEntry := input.hasROBEntry 278 if(latch) isLoadReplay := RegEnable(input.isLoadReplay, enable) else isLoadReplay := input.isLoadReplay 279 if(latch) isFastPath := RegEnable(input.isFastPath, enable) else isFastPath := input.isFastPath 280 if(latch) isFastReplay := RegEnable(input.isFastReplay, enable) else isFastReplay := input.isFastReplay 281 if(latch) mshrid := RegEnable(input.mshrid, enable) else mshrid := input.mshrid 282 if(latch) forward_tlDchannel := RegEnable(input.forward_tlDchannel, enable) else forward_tlDchannel := input.forward_tlDchannel 283 if(latch) replayCarry := RegEnable(input.replayCarry, enable) else replayCarry := input.replayCarry 284 if(latch) dcacheRequireReplay := RegEnable(input.dcacheRequireReplay, enable) else dcacheRequireReplay := input.dcacheRequireReplay 285 if(latch) schedIndex := RegEnable(input.schedIndex, enable) else schedIndex := input.schedIndex 286 if(latch) handledByMSHR := RegEnable(input.handledByMSHR, enable) else handledByMSHR := input.handledByMSHR 287 if(latch) replacementUpdated := RegEnable(input.replacementUpdated, enable) else replacementUpdated := input.replacementUpdated 288 if(latch) missDbUpdated := RegEnable(input.missDbUpdated, enable) else missDbUpdated := input.missDbUpdated 289 if(latch) delayedLoadError := RegEnable(input.delayedLoadError, enable) else delayedLoadError := input.delayedLoadError 290 if(latch) lateKill := RegEnable(input.lateKill, enable) else lateKill := input.lateKill 291 if(latch) feedbacked := RegEnable(input.feedbacked, enable) else feedbacked := input.feedbacked 292 if(latch) isvec := RegEnable(input.isvec, enable) else isvec := input.isvec 293 if(latch) is128bit := RegEnable(input.is128bit, enable) else is128bit := input.is128bit 294 if(latch) vecActive := RegEnable(input.vecActive, enable) else vecActive := input.vecActive 295 if(latch) uop_unit_stride_fof := RegEnable(input.uop_unit_stride_fof, enable) else uop_unit_stride_fof := input.uop_unit_stride_fof 296 if(latch) reg_offset := RegEnable(input.reg_offset, enable) else reg_offset := input.reg_offset 297 if(latch) mbIndex := RegEnable(input.mbIndex, enable) else mbIndex := input.mbIndex 298 if(latch) elemIdxInsideVd := RegEnable(input.elemIdxInsideVd, enable) else elemIdxInsideVd := input.elemIdxInsideVd 299 300 rep_info := DontCare 301 data_wen_dup := DontCare 302 } 303} 304 305class SqWriteBundle(implicit p: Parameters) extends LsPipelineBundle { 306 val need_rep = Bool() 307} 308 309class LoadForwardQueryIO(implicit p: Parameters) extends XSBundle { 310 val vaddr = Output(UInt(VAddrBits.W)) 311 val paddr = Output(UInt(PAddrBits.W)) 312 val mask = Output(UInt((VLEN/8).W)) 313 val uop = Output(new DynInst) // for replay 314 val pc = Output(UInt(VAddrBits.W)) //for debug 315 val valid = Output(Bool()) 316 317 val forwardMaskFast = Input(Vec((VLEN/8), Bool())) // resp to load_s1 318 val forwardMask = Input(Vec((VLEN/8), Bool())) // resp to load_s2 319 val forwardData = Input(Vec((VLEN/8), UInt(8.W))) // resp to load_s2 320 321 // val lqIdx = Output(UInt(LoadQueueIdxWidth.W)) 322 val sqIdx = Output(new SqPtr) 323 324 // dataInvalid suggests store to load forward found forward should happen, 325 // but data is not available for now. If dataInvalid, load inst should 326 // be replayed from RS. Feedback type should be RSFeedbackType.dataInvalid 327 val dataInvalid = Input(Bool()) // Addr match, but data is not valid for now 328 329 // matchInvalid suggests in store to load forward logic, paddr cam result does 330 // to equal to vaddr cam result. If matchInvalid, a microarchitectural exception 331 // should be raised to flush SQ and committed sbuffer. 332 val matchInvalid = Input(Bool()) // resp to load_s2 333 334 // addrInvalid suggests store to load forward found forward should happen, 335 // but address (SSID) is not available for now. If addrInvalid, load inst should 336 // be replayed from RS. Feedback type should be RSFeedbackType.addrInvalid 337 val addrInvalid = Input(Bool()) 338} 339 340// LoadForwardQueryIO used in load pipeline 341// 342// Difference between PipeLoadForwardQueryIO and LoadForwardQueryIO: 343// PipeIO use predecoded sqIdxMask for better forward timing 344class PipeLoadForwardQueryIO(implicit p: Parameters) extends LoadForwardQueryIO { 345 // val sqIdx = Output(new SqPtr) // for debug, should not be used in pipeline for timing reasons 346 // sqIdxMask is calcuated in earlier stage for better timing 347 val sqIdxMask = Output(UInt(StoreQueueSize.W)) 348 349 // dataInvalid: addr match, but data is not valid for now 350 val dataInvalidFast = Input(Bool()) // resp to load_s1 351 // val dataInvalid = Input(Bool()) // resp to load_s2 352 val dataInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 353 val addrInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 354} 355 356// Query load queue for ld-ld violation 357// 358// Req should be send in load_s1 359// Resp will be generated 1 cycle later 360// 361// Note that query req may be !ready, as dcache is releasing a block 362// If it happens, a replay from rs is needed. 363class LoadNukeQueryReq(implicit p: Parameters) extends XSBundle { // provide lqIdx 364 val uop = new DynInst 365 // mask: load's data mask. 366 val mask = UInt((VLEN/8).W) 367 368 // paddr: load's paddr. 369 val paddr = UInt(PAddrBits.W) 370 // dataInvalid: load data is invalid. 371 val data_valid = Bool() 372} 373 374class LoadNukeQueryResp(implicit p: Parameters) extends XSBundle { 375 // rep_frm_fetch: ld-ld violation check success, replay from fetch. 376 val rep_frm_fetch = Bool() 377} 378 379class LoadNukeQueryIO(implicit p: Parameters) extends XSBundle { 380 val req = Decoupled(new LoadNukeQueryReq) 381 val resp = Flipped(Valid(new LoadNukeQueryResp)) 382 val revoke = Output(Bool()) 383} 384 385class StoreNukeQueryIO(implicit p: Parameters) extends XSBundle { 386 // robIdx: Requestor's (a store instruction) rob index for match logic. 387 val robIdx = new RobPtr 388 389 // paddr: requestor's (a store instruction) physical address for match logic. 390 val paddr = UInt(PAddrBits.W) 391 392 // mask: requestor's (a store instruction) data width mask for match logic. 393 val mask = UInt((VLEN/8).W) 394 395 // matchLine: if store is vector 128-bits, load unit need to compare 128-bits vaddr. 396 val matchLine = Bool() 397} 398 399class StoreMaBufToSqControlIO(implicit p: Parameters) extends XSBundle { 400 // from storeMisalignBuffer to storeQueue, control it's sbuffer write 401 val control = Output(new XSBundle { 402 // control sq to write-into sb 403 val writeSb = Bool() 404 val wdata = UInt(VLEN.W) 405 val wmask = UInt((VLEN / 8).W) 406 val paddr = UInt(PAddrBits.W) 407 val vaddr = UInt(VAddrBits.W) 408 val last = Bool() 409 val hasException = Bool() 410 // remove this entry in sq 411 val removeSq = Bool() 412 }) 413 // from storeQueue to storeMisalignBuffer, provide detail info of this store 414 val storeInfo = Input(new XSBundle { 415 val data = UInt(VLEN.W) 416 // is the data of the unaligned store ready at sq? 417 val dataReady = Bool() 418 // complete a data transfer from sq to sb 419 val completeSbTrans = Bool() 420 }) 421} 422 423// Store byte valid mask write bundle 424// 425// Store byte valid mask write to SQ takes 2 cycles 426class StoreMaskBundle(implicit p: Parameters) extends XSBundle { 427 val sqIdx = new SqPtr 428 val mask = UInt((VLEN/8).W) 429} 430 431class LoadDataFromDcacheBundle(implicit p: Parameters) extends DCacheBundle { 432 // old dcache: optimize data sram read fanout 433 // val bankedDcacheData = Vec(DCacheBanks, UInt(64.W)) 434 // val bank_oh = UInt(DCacheBanks.W) 435 436 // new dcache 437 val respDcacheData = UInt(VLEN.W) 438 val forwardMask = Vec(VLEN/8, Bool()) 439 val forwardData = Vec(VLEN/8, UInt(8.W)) 440 val uop = new DynInst // for data selection, only fwen and fuOpType are used 441 val addrOffset = UInt(4.W) // for data selection 442 443 // forward tilelink D channel 444 val forward_D = Bool() 445 val forwardData_D = Vec(VLEN/8, UInt(8.W)) 446 447 // forward mshr data 448 val forward_mshr = Bool() 449 val forwardData_mshr = Vec(VLEN/8, UInt(8.W)) 450 451 val forward_result_valid = Bool() 452 453 def mergeTLData(): UInt = { 454 // merge TL D or MSHR data at load s2 455 val dcache_data = respDcacheData 456 val use_D = forward_D && forward_result_valid 457 val use_mshr = forward_mshr && forward_result_valid 458 Mux( 459 use_D || use_mshr, 460 Mux( 461 use_D, 462 forwardData_D.asUInt, 463 forwardData_mshr.asUInt 464 ), 465 dcache_data 466 ) 467 } 468 469 def mergeLsqFwdData(dcacheData: UInt): UInt = { 470 // merge dcache and lsq forward data at load s3 471 val rdataVec = VecInit((0 until VLEN / 8).map(j => 472 Mux(forwardMask(j), forwardData(j), dcacheData(8*(j+1)-1, 8*j)) 473 )) 474 rdataVec.asUInt 475 } 476} 477 478// Load writeback data from load queue (refill) 479class LoadDataFromLQBundle(implicit p: Parameters) extends XSBundle { 480 val lqData = UInt(64.W) // load queue has merged data 481 val uop = new DynInst // for data selection, only fwen and fuOpType are used 482 val addrOffset = UInt(3.W) // for data selection 483 484 def mergedData(): UInt = { 485 lqData 486 } 487} 488 489// Bundle for load / store wait waking up 490class MemWaitUpdateReq(implicit p: Parameters) extends XSBundle { 491 val robIdx = Vec(backendParams.StaExuCnt, ValidIO(new RobPtr)) 492 val sqIdx = Vec(backendParams.StdCnt, ValidIO(new SqPtr)) 493} 494 495object AddPipelineReg { 496 class PipelineRegModule[T <: Data](gen: T) extends Module { 497 val io = IO(new Bundle() { 498 val in = Flipped(DecoupledIO(gen.cloneType)) 499 val out = DecoupledIO(gen.cloneType) 500 val isFlush = Input(Bool()) 501 }) 502 503 val valid = RegInit(false.B) 504 valid.suggestName("pipeline_reg_valid") 505 when (io.out.fire) { valid := false.B } 506 when (io.in.fire) { valid := true.B } 507 when (io.isFlush) { valid := false.B } 508 509 io.in.ready := !valid || io.out.ready 510 io.out.bits := RegEnable(io.in.bits, io.in.fire) 511 io.out.valid := valid //&& !isFlush 512 } 513 514 def apply[T <: Data] 515 (left: DecoupledIO[T], right: DecoupledIO[T], isFlush: Bool, 516 moduleName: Option[String] = None 517 ): Unit = { 518 val pipelineReg = Module(new PipelineRegModule[T](left.bits.cloneType)) 519 if(moduleName.nonEmpty) pipelineReg.suggestName(moduleName.get) 520 pipelineReg.io.in <> left 521 right <> pipelineReg.io.out 522 pipelineReg.io.isFlush := isFlush 523 } 524}