1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: 9* http://license.coscl.org.cn/MulanPSL2 10* 11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14* 15* See the Mulan PSL v2 for more details. 16***************************************************************************************/ 17 18package xiangshan.mem 19 20 21import org.chipsalliance.cde.config.Parameters 22import chisel3._ 23import chisel3.util._ 24import utility._ 25import utils._ 26import xiangshan._ 27import xiangshan.backend.Bundles.{DynInst, MemExuInput} 28import xiangshan.backend.rob.RobPtr 29import xiangshan.cache._ 30import xiangshan.backend.fu.FenceToSbuffer 31import xiangshan.cache.wpu.ReplayCarry 32import xiangshan.mem.prefetch.PrefetchReqBundle 33import math._ 34 35object genWmask { 36 def apply(addr: UInt, sizeEncode: UInt): UInt = { 37 (LookupTree(sizeEncode, List( 38 "b00".U -> 0x1.U, //0001 << addr(2:0) 39 "b01".U -> 0x3.U, //0011 40 "b10".U -> 0xf.U, //1111 41 "b11".U -> 0xff.U //11111111 42 )) << addr(2, 0)).asUInt 43 } 44} 45 46object genVWmask { 47 def apply(addr: UInt, sizeEncode: UInt): UInt = { 48 (LookupTree(sizeEncode, List( 49 "b00".U -> 0x1.U, //0001 << addr(2:0) 50 "b01".U -> 0x3.U, //0011 51 "b10".U -> 0xf.U, //1111 52 "b11".U -> 0xff.U //11111111 53 )) << addr(3, 0)).asUInt 54 } 55} 56 57object shiftDataToLow { 58 def apply(addr: UInt, data : UInt): UInt = { 59 Mux(addr(3), (data >> 64).asUInt, data) 60 } 61} 62object shiftMaskToLow { 63 def apply(addr: UInt, mask: UInt): UInt = { 64 Mux(addr(3), (mask >> 8).asUInt, mask) 65 } 66} 67object shiftDataToHigh { 68 def apply(addr: UInt, data : UInt): UInt = { 69 Mux(addr(3), (data << 64).asUInt, data) 70 } 71} 72object shiftMaskToHigh { 73 def apply(addr: UInt, mask: UInt): UInt = { 74 Mux(addr(3), (mask << 8).asUInt, mask) 75 } 76} 77 78class LsPipelineBundle(implicit p: Parameters) extends XSBundle 79 with HasDCacheParameters 80 with HasVLSUParameters { 81 val uop = new DynInst 82 val vaddr = UInt(VAddrBits.W) 83 // For exception vaddr generate 84 val fullva = UInt(XLEN.W) 85 val vaNeedExt = Bool() 86 val isHyper = Bool() 87 val paddr = UInt(PAddrBits.W) 88 val gpaddr = UInt(XLEN.W) 89 val isForVSnonLeafPTE = Bool() 90 // val func = UInt(6.W) 91 val mask = UInt((VLEN/8).W) 92 val data = UInt((VLEN+1).W) 93 val wlineflag = Bool() // store write the whole cache line 94 95 val miss = Bool() 96 val tlbMiss = Bool() 97 val ptwBack = Bool() 98 val af = Bool() 99 val nc = Bool() 100 val mmio = Bool() 101 val atomic = Bool() 102 103 val forwardMask = Vec(VLEN/8, Bool()) 104 val forwardData = Vec(VLEN/8, UInt(8.W)) 105 106 // prefetch 107 val isPrefetch = Bool() 108 val isHWPrefetch = Bool() 109 def isSWPrefetch = isPrefetch && !isHWPrefetch 110 111 // misalignBuffer 112 val isFrmMisAlignBuf = Bool() 113 114 // vector 115 val isvec = Bool() 116 val isLastElem = Bool() 117 val is128bit = Bool() 118 val uop_unit_stride_fof = Bool() 119 val usSecondInv = Bool() 120 val elemIdx = UInt(elemIdxBits.W) 121 val alignedType = UInt(alignTypeBits.W) 122 val mbIndex = UInt(max(vlmBindexBits, vsmBindexBits).W) 123 // val rob_idx_valid = Vec(2,Bool()) 124 // val inner_idx = Vec(2,UInt(3.W)) 125 // val rob_idx = Vec(2,new RobPtr) 126 val reg_offset = UInt(vOffsetBits.W) 127 val elemIdxInsideVd = UInt(elemIdxBits.W) 128 // val offset = Vec(2,UInt(4.W)) 129 val vecActive = Bool() // 1: vector active element or scala mem operation, 0: vector not active element 130 val is_first_ele = Bool() 131 val vecBaseVaddr = UInt(VAddrBits.W) 132 val vecVaddrOffset = UInt(VAddrBits.W) 133 val vecTriggerMask = UInt((VLEN/8).W) 134 // val flowPtr = new VlflowPtr() // VLFlowQueue ptr 135 // val sflowPtr = new VsFlowPtr() // VSFlowQueue ptr 136 137 // For debug usage 138 val isFirstIssue = Bool() 139 val hasROBEntry = Bool() 140 141 // For load replay 142 val isLoadReplay = Bool() 143 val isFastPath = Bool() 144 val isFastReplay = Bool() 145 val replayCarry = new ReplayCarry(nWays) 146 147 // For dcache miss load 148 val mshrid = UInt(log2Up(cfg.nMissEntries).W) 149 val handledByMSHR = Bool() 150 val replacementUpdated = Bool() 151 val missDbUpdated = Bool() 152 153 val forward_tlDchannel = Bool() 154 val dcacheRequireReplay = Bool() 155 val delayedLoadError = Bool() 156 val lateKill = Bool() 157 val feedbacked = Bool() 158 val ldCancel = ValidUndirectioned(UInt(log2Ceil(LoadPipelineWidth).W)) 159 // loadQueueReplay index. 160 val schedIndex = UInt(log2Up(LoadQueueReplaySize).W) 161 // hardware prefetch and fast replay no need to query tlb 162 val tlbNoQuery = Bool() 163} 164 165class LdPrefetchTrainBundle(implicit p: Parameters) extends LsPipelineBundle { 166 val meta_prefetch = UInt(L1PfSourceBits.W) 167 val meta_access = Bool() 168 169 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false, enable: Bool = true.B) = { 170 if (latch) vaddr := RegEnable(input.vaddr, enable) else vaddr := input.vaddr 171 if (latch) fullva := RegEnable(input.fullva, enable) else fullva := input.fullva 172 if (latch) vaNeedExt := RegEnable(input.vaNeedExt, enable) else vaNeedExt := input.vaNeedExt 173 if (latch) isHyper := RegEnable(input.isHyper, enable) else isHyper := input.isHyper 174 if (latch) paddr := RegEnable(input.paddr, enable) else paddr := input.paddr 175 if (latch) gpaddr := RegEnable(input.gpaddr, enable) else gpaddr := input.gpaddr 176 if (latch) isForVSnonLeafPTE := RegEnable(input.isForVSnonLeafPTE, enable) else isForVSnonLeafPTE := input.isForVSnonLeafPTE 177 if (latch) mask := RegEnable(input.mask, enable) else mask := input.mask 178 if (latch) data := RegEnable(input.data, enable) else data := input.data 179 if (latch) uop := RegEnable(input.uop, enable) else uop := input.uop 180 if (latch) wlineflag := RegEnable(input.wlineflag, enable) else wlineflag := input.wlineflag 181 if (latch) miss := RegEnable(input.miss, enable) else miss := input.miss 182 if (latch) tlbMiss := RegEnable(input.tlbMiss, enable) else tlbMiss := input.tlbMiss 183 if (latch) ptwBack := RegEnable(input.ptwBack, enable) else ptwBack := input.ptwBack 184 if (latch) af := RegEnable(input.af, enable) else af := input.af 185 if (latch) nc := RegEnable(input.nc, enable) else nc := input.nc 186 if (latch) mmio := RegEnable(input.mmio, enable) else mmio := input.mmio 187 if (latch) forwardMask := RegEnable(input.forwardMask, enable) else forwardMask := input.forwardMask 188 if (latch) forwardData := RegEnable(input.forwardData, enable) else forwardData := input.forwardData 189 if (latch) isPrefetch := RegEnable(input.isPrefetch, enable) else isPrefetch := input.isPrefetch 190 if (latch) isHWPrefetch := RegEnable(input.isHWPrefetch, enable) else isHWPrefetch := input.isHWPrefetch 191 if (latch) isFrmMisAlignBuf := RegEnable(input.isFrmMisAlignBuf, enable) else isFrmMisAlignBuf := input.isFrmMisAlignBuf 192 if (latch) isFirstIssue := RegEnable(input.isFirstIssue, enable) else isFirstIssue := input.isFirstIssue 193 if (latch) hasROBEntry := RegEnable(input.hasROBEntry, enable) else hasROBEntry := input.hasROBEntry 194 if (latch) dcacheRequireReplay := RegEnable(input.dcacheRequireReplay, enable) else dcacheRequireReplay := input.dcacheRequireReplay 195 if (latch) schedIndex := RegEnable(input.schedIndex, enable) else schedIndex := input.schedIndex 196 if (latch) tlbNoQuery := RegEnable(input.tlbNoQuery, enable) else tlbNoQuery := input.tlbNoQuery 197 if (latch) isvec := RegEnable(input.isvec, enable) else isvec := input.isvec 198 if (latch) isLastElem := RegEnable(input.isLastElem, enable) else isLastElem := input.isLastElem 199 if (latch) is128bit := RegEnable(input.is128bit, enable) else is128bit := input.is128bit 200 if (latch) vecActive := RegEnable(input.vecActive, enable) else vecActive := input.vecActive 201 if (latch) is_first_ele := RegEnable(input.is_first_ele, enable) else is_first_ele := input.is_first_ele 202 if (latch) uop_unit_stride_fof := RegEnable(input.uop_unit_stride_fof, enable) else uop_unit_stride_fof := input.uop_unit_stride_fof 203 if (latch) usSecondInv := RegEnable(input.usSecondInv, enable) else usSecondInv := input.usSecondInv 204 if (latch) reg_offset := RegEnable(input.reg_offset, enable) else reg_offset := input.reg_offset 205 if (latch) elemIdx := RegEnable(input.elemIdx, enable) else elemIdx := input.elemIdx 206 if (latch) alignedType := RegEnable(input.alignedType, enable) else alignedType := input.alignedType 207 if (latch) mbIndex := RegEnable(input.mbIndex, enable) else mbIndex := input.mbIndex 208 if (latch) elemIdxInsideVd := RegEnable(input.elemIdxInsideVd, enable) else elemIdxInsideVd := input.elemIdxInsideVd 209 if (latch) vecBaseVaddr := RegEnable(input.vecBaseVaddr, enable) else vecBaseVaddr := input.vecBaseVaddr 210 if (latch) vecVaddrOffset := RegEnable(input.vecVaddrOffset, enable) else vecVaddrOffset := input.vecVaddrOffset 211 if (latch) vecTriggerMask := RegEnable(input.vecTriggerMask, enable) else vecTriggerMask := input.vecTriggerMask 212 // if (latch) flowPtr := RegEnable(input.flowPtr, enable) else flowPtr := input.flowPtr 213 // if (latch) sflowPtr := RegEnable(input.sflowPtr, enable) else sflowPtr := input.sflowPtr 214 215 meta_prefetch := DontCare 216 meta_access := DontCare 217 forward_tlDchannel := DontCare 218 mshrid := DontCare 219 replayCarry := DontCare 220 atomic := DontCare 221 isLoadReplay := DontCare 222 isFastPath := DontCare 223 isFastReplay := DontCare 224 handledByMSHR := DontCare 225 replacementUpdated := DontCare 226 missDbUpdated := DontCare 227 delayedLoadError := DontCare 228 lateKill := DontCare 229 feedbacked := DontCare 230 ldCancel := DontCare 231 } 232 233 def asPrefetchReqBundle(): PrefetchReqBundle = { 234 val res = Wire(new PrefetchReqBundle) 235 res.vaddr := this.vaddr 236 res.paddr := this.paddr 237 res.pc := this.uop.pc 238 res.miss := this.miss 239 res.pfHitStream := isFromStream(this.meta_prefetch) 240 241 res 242 } 243} 244 245class StPrefetchTrainBundle(implicit p: Parameters) extends LdPrefetchTrainBundle {} 246 247class LqWriteBundle(implicit p: Parameters) extends LsPipelineBundle { 248 // load inst replay informations 249 val rep_info = new LoadToLsqReplayIO 250 // queue entry data, except flag bits, will be updated if writeQueue is true, 251 // valid bit in LqWriteBundle will be ignored 252 val data_wen_dup = Vec(6, Bool()) // dirty reg dup 253 254 255 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false, enable: Bool = true.B) = { 256 if(latch) vaddr := RegEnable(input.vaddr, enable) else vaddr := input.vaddr 257 if(latch) fullva := RegEnable(input.fullva, enable) else fullva := input.fullva 258 if(latch) vaNeedExt := RegEnable(input.vaNeedExt, enable) else vaNeedExt := input.vaNeedExt 259 if(latch) isHyper := RegEnable(input.isHyper, enable) else isHyper := input.isHyper 260 if(latch) paddr := RegEnable(input.paddr, enable) else paddr := input.paddr 261 if(latch) gpaddr := RegEnable(input.gpaddr, enable) else gpaddr := input.gpaddr 262 if(latch) isForVSnonLeafPTE := RegEnable(input.isForVSnonLeafPTE, enable) else isForVSnonLeafPTE := input.isForVSnonLeafPTE 263 if(latch) mask := RegEnable(input.mask, enable) else mask := input.mask 264 if(latch) data := RegEnable(input.data, enable) else data := input.data 265 if(latch) uop := RegEnable(input.uop, enable) else uop := input.uop 266 if(latch) wlineflag := RegEnable(input.wlineflag, enable) else wlineflag := input.wlineflag 267 if(latch) miss := RegEnable(input.miss, enable) else miss := input.miss 268 if(latch) tlbMiss := RegEnable(input.tlbMiss, enable) else tlbMiss := input.tlbMiss 269 if(latch) ptwBack := RegEnable(input.ptwBack, enable) else ptwBack := input.ptwBack 270 if(latch) mmio := RegEnable(input.mmio, enable) else mmio := input.mmio 271 if(latch) atomic := RegEnable(input.atomic, enable) else atomic := input.atomic 272 if(latch) forwardMask := RegEnable(input.forwardMask, enable) else forwardMask := input.forwardMask 273 if(latch) forwardData := RegEnable(input.forwardData, enable) else forwardData := input.forwardData 274 if(latch) isPrefetch := RegEnable(input.isPrefetch, enable) else isPrefetch := input.isPrefetch 275 if(latch) isHWPrefetch := RegEnable(input.isHWPrefetch, enable) else isHWPrefetch := input.isHWPrefetch 276 if(latch) isFrmMisAlignBuf := RegEnable(input.isFrmMisAlignBuf, enable) else isFrmMisAlignBuf := input.isFrmMisAlignBuf 277 if(latch) isFirstIssue := RegEnable(input.isFirstIssue, enable) else isFirstIssue := input.isFirstIssue 278 if(latch) hasROBEntry := RegEnable(input.hasROBEntry, enable) else hasROBEntry := input.hasROBEntry 279 if(latch) isLoadReplay := RegEnable(input.isLoadReplay, enable) else isLoadReplay := input.isLoadReplay 280 if(latch) isFastPath := RegEnable(input.isFastPath, enable) else isFastPath := input.isFastPath 281 if(latch) isFastReplay := RegEnable(input.isFastReplay, enable) else isFastReplay := input.isFastReplay 282 if(latch) mshrid := RegEnable(input.mshrid, enable) else mshrid := input.mshrid 283 if(latch) forward_tlDchannel := RegEnable(input.forward_tlDchannel, enable) else forward_tlDchannel := input.forward_tlDchannel 284 if(latch) replayCarry := RegEnable(input.replayCarry, enable) else replayCarry := input.replayCarry 285 if(latch) dcacheRequireReplay := RegEnable(input.dcacheRequireReplay, enable) else dcacheRequireReplay := input.dcacheRequireReplay 286 if(latch) schedIndex := RegEnable(input.schedIndex, enable) else schedIndex := input.schedIndex 287 if(latch) handledByMSHR := RegEnable(input.handledByMSHR, enable) else handledByMSHR := input.handledByMSHR 288 if(latch) replacementUpdated := RegEnable(input.replacementUpdated, enable) else replacementUpdated := input.replacementUpdated 289 if(latch) missDbUpdated := RegEnable(input.missDbUpdated, enable) else missDbUpdated := input.missDbUpdated 290 if(latch) delayedLoadError := RegEnable(input.delayedLoadError, enable) else delayedLoadError := input.delayedLoadError 291 if(latch) lateKill := RegEnable(input.lateKill, enable) else lateKill := input.lateKill 292 if(latch) feedbacked := RegEnable(input.feedbacked, enable) else feedbacked := input.feedbacked 293 if(latch) isvec := RegEnable(input.isvec, enable) else isvec := input.isvec 294 if(latch) is128bit := RegEnable(input.is128bit, enable) else is128bit := input.is128bit 295 if(latch) vecActive := RegEnable(input.vecActive, enable) else vecActive := input.vecActive 296 if(latch) uop_unit_stride_fof := RegEnable(input.uop_unit_stride_fof, enable) else uop_unit_stride_fof := input.uop_unit_stride_fof 297 if(latch) reg_offset := RegEnable(input.reg_offset, enable) else reg_offset := input.reg_offset 298 if(latch) mbIndex := RegEnable(input.mbIndex, enable) else mbIndex := input.mbIndex 299 if(latch) elemIdxInsideVd := RegEnable(input.elemIdxInsideVd, enable) else elemIdxInsideVd := input.elemIdxInsideVd 300 301 rep_info := DontCare 302 data_wen_dup := DontCare 303 } 304} 305 306class SqWriteBundle(implicit p: Parameters) extends LsPipelineBundle { 307 val need_rep = Bool() 308} 309 310class LoadForwardQueryIO(implicit p: Parameters) extends XSBundle { 311 val vaddr = Output(UInt(VAddrBits.W)) 312 val paddr = Output(UInt(PAddrBits.W)) 313 val mask = Output(UInt((VLEN/8).W)) 314 val uop = Output(new DynInst) // for replay 315 val pc = Output(UInt(VAddrBits.W)) //for debug 316 val valid = Output(Bool()) 317 318 val forwardMaskFast = Input(Vec((VLEN/8), Bool())) // resp to load_s1 319 val forwardMask = Input(Vec((VLEN/8), Bool())) // resp to load_s2 320 val forwardData = Input(Vec((VLEN/8), UInt(8.W))) // resp to load_s2 321 322 // val lqIdx = Output(UInt(LoadQueueIdxWidth.W)) 323 val sqIdx = Output(new SqPtr) 324 325 // dataInvalid suggests store to load forward found forward should happen, 326 // but data is not available for now. If dataInvalid, load inst should 327 // be replayed from RS. Feedback type should be RSFeedbackType.dataInvalid 328 val dataInvalid = Input(Bool()) // Addr match, but data is not valid for now 329 330 // matchInvalid suggests in store to load forward logic, paddr cam result does 331 // to equal to vaddr cam result. If matchInvalid, a microarchitectural exception 332 // should be raised to flush SQ and committed sbuffer. 333 val matchInvalid = Input(Bool()) // resp to load_s2 334 335 // addrInvalid suggests store to load forward found forward should happen, 336 // but address (SSID) is not available for now. If addrInvalid, load inst should 337 // be replayed from RS. Feedback type should be RSFeedbackType.addrInvalid 338 val addrInvalid = Input(Bool()) 339} 340 341// LoadForwardQueryIO used in load pipeline 342// 343// Difference between PipeLoadForwardQueryIO and LoadForwardQueryIO: 344// PipeIO use predecoded sqIdxMask for better forward timing 345class PipeLoadForwardQueryIO(implicit p: Parameters) extends LoadForwardQueryIO { 346 // val sqIdx = Output(new SqPtr) // for debug, should not be used in pipeline for timing reasons 347 // sqIdxMask is calcuated in earlier stage for better timing 348 val sqIdxMask = Output(UInt(StoreQueueSize.W)) 349 350 // dataInvalid: addr match, but data is not valid for now 351 val dataInvalidFast = Input(Bool()) // resp to load_s1 352 // val dataInvalid = Input(Bool()) // resp to load_s2 353 val dataInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 354 val addrInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 355} 356 357// Query load queue for ld-ld violation 358// 359// Req should be send in load_s1 360// Resp will be generated 1 cycle later 361// 362// Note that query req may be !ready, as dcache is releasing a block 363// If it happens, a replay from rs is needed. 364class LoadNukeQueryReq(implicit p: Parameters) extends XSBundle { // provide lqIdx 365 val uop = new DynInst 366 // mask: load's data mask. 367 val mask = UInt((VLEN/8).W) 368 369 // paddr: load's paddr. 370 val paddr = UInt(PAddrBits.W) 371 // dataInvalid: load data is invalid. 372 val data_valid = Bool() 373 // nc: is NC access 374 val is_nc = Bool() 375} 376 377class LoadNukeQueryResp(implicit p: Parameters) extends XSBundle { 378 // rep_frm_fetch: ld-ld violation check success, replay from fetch. 379 val rep_frm_fetch = Bool() 380} 381 382class LoadNukeQueryIO(implicit p: Parameters) extends XSBundle { 383 val req = Decoupled(new LoadNukeQueryReq) 384 val resp = Flipped(Valid(new LoadNukeQueryResp)) 385 val revoke = Output(Bool()) 386} 387 388class StoreNukeQueryIO(implicit p: Parameters) extends XSBundle { 389 // robIdx: Requestor's (a store instruction) rob index for match logic. 390 val robIdx = new RobPtr 391 392 // paddr: requestor's (a store instruction) physical address for match logic. 393 val paddr = UInt(PAddrBits.W) 394 395 // mask: requestor's (a store instruction) data width mask for match logic. 396 val mask = UInt((VLEN/8).W) 397 398 // matchLine: if store is vector 128-bits, load unit need to compare 128-bits vaddr. 399 val matchLine = Bool() 400} 401 402class StoreMaBufToSqControlIO(implicit p: Parameters) extends XSBundle { 403 // from storeMisalignBuffer to storeQueue, control it's sbuffer write 404 val control = Output(new XSBundle { 405 // control sq to write-into sb 406 val writeSb = Bool() 407 val wdata = UInt(VLEN.W) 408 val wmask = UInt((VLEN / 8).W) 409 val paddr = UInt(PAddrBits.W) 410 val vaddr = UInt(VAddrBits.W) 411 val last = Bool() 412 val hasException = Bool() 413 // remove this entry in sq 414 val removeSq = Bool() 415 }) 416 // from storeQueue to storeMisalignBuffer, provide detail info of this store 417 val storeInfo = Input(new XSBundle { 418 val data = UInt(VLEN.W) 419 // is the data of the unaligned store ready at sq? 420 val dataReady = Bool() 421 // complete a data transfer from sq to sb 422 val completeSbTrans = Bool() 423 }) 424} 425 426// Store byte valid mask write bundle 427// 428// Store byte valid mask write to SQ takes 2 cycles 429class StoreMaskBundle(implicit p: Parameters) extends XSBundle { 430 val sqIdx = new SqPtr 431 val mask = UInt((VLEN/8).W) 432} 433 434class LoadDataFromDcacheBundle(implicit p: Parameters) extends DCacheBundle { 435 // old dcache: optimize data sram read fanout 436 // val bankedDcacheData = Vec(DCacheBanks, UInt(64.W)) 437 // val bank_oh = UInt(DCacheBanks.W) 438 439 // new dcache 440 val respDcacheData = UInt(VLEN.W) 441 val forwardMask = Vec(VLEN/8, Bool()) 442 val forwardData = Vec(VLEN/8, UInt(8.W)) 443 val uop = new DynInst // for data selection, only fwen and fuOpType are used 444 val addrOffset = UInt(4.W) // for data selection 445 446 // forward tilelink D channel 447 val forward_D = Bool() 448 val forwardData_D = Vec(VLEN/8, UInt(8.W)) 449 450 // forward mshr data 451 val forward_mshr = Bool() 452 val forwardData_mshr = Vec(VLEN/8, UInt(8.W)) 453 454 val forward_result_valid = Bool() 455 456 def mergeTLData(): UInt = { 457 // merge TL D or MSHR data at load s2 458 val dcache_data = respDcacheData 459 val use_D = forward_D && forward_result_valid 460 val use_mshr = forward_mshr && forward_result_valid 461 Mux( 462 use_D || use_mshr, 463 Mux( 464 use_D, 465 forwardData_D.asUInt, 466 forwardData_mshr.asUInt 467 ), 468 dcache_data 469 ) 470 } 471 472 def mergeLsqFwdData(dcacheData: UInt): UInt = { 473 // merge dcache and lsq forward data at load s3 474 val rdataVec = VecInit((0 until VLEN / 8).map(j => 475 Mux(forwardMask(j), forwardData(j), dcacheData(8*(j+1)-1, 8*j)) 476 )) 477 rdataVec.asUInt 478 } 479} 480 481// Load writeback data from load queue (refill) 482class LoadDataFromLQBundle(implicit p: Parameters) extends XSBundle { 483 val lqData = UInt(64.W) // load queue has merged data 484 val uop = new DynInst // for data selection, only fwen and fuOpType are used 485 val addrOffset = UInt(3.W) // for data selection 486 487 def mergedData(): UInt = { 488 lqData 489 } 490} 491 492// Bundle for load / store wait waking up 493class MemWaitUpdateReq(implicit p: Parameters) extends XSBundle { 494 val robIdx = Vec(backendParams.StaExuCnt, ValidIO(new RobPtr)) 495 val sqIdx = Vec(backendParams.StdCnt, ValidIO(new SqPtr)) 496} 497 498object AddPipelineReg { 499 class PipelineRegModule[T <: Data](gen: T) extends Module { 500 val io = IO(new Bundle() { 501 val in = Flipped(DecoupledIO(gen.cloneType)) 502 val out = DecoupledIO(gen.cloneType) 503 val isFlush = Input(Bool()) 504 }) 505 506 val valid = RegInit(false.B) 507 valid.suggestName("pipeline_reg_valid") 508 when (io.out.fire) { valid := false.B } 509 when (io.in.fire) { valid := true.B } 510 when (io.isFlush) { valid := false.B } 511 512 io.in.ready := !valid || io.out.ready 513 io.out.bits := RegEnable(io.in.bits, io.in.fire) 514 io.out.valid := valid //&& !isFlush 515 } 516 517 def apply[T <: Data] 518 (left: DecoupledIO[T], right: DecoupledIO[T], isFlush: Bool, 519 moduleName: Option[String] = None 520 ): Unit = { 521 val pipelineReg = Module(new PipelineRegModule[T](left.bits.cloneType)) 522 if(moduleName.nonEmpty) pipelineReg.suggestName(moduleName.get) 523 pipelineReg.io.in <> left 524 right <> pipelineReg.io.out 525 pipelineReg.io.isFlush := isFlush 526 } 527}