1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: 9* http://license.coscl.org.cn/MulanPSL2 10* 11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14* 15* See the Mulan PSL v2 for more details. 16***************************************************************************************/ 17 18package xiangshan.mem 19 20 21import org.chipsalliance.cde.config.Parameters 22import chisel3._ 23import chisel3.util._ 24import utility._ 25import utils._ 26import xiangshan._ 27import xiangshan.backend.Bundles.{DynInst, MemExuInput} 28import xiangshan.backend.rob.RobPtr 29import xiangshan.cache._ 30import xiangshan.backend.fu.FenceToSbuffer 31import xiangshan.cache.wpu.ReplayCarry 32import xiangshan.mem.prefetch.PrefetchReqBundle 33import math._ 34 35object genWmask { 36 def apply(addr: UInt, sizeEncode: UInt): UInt = { 37 (LookupTree(sizeEncode, List( 38 "b00".U -> 0x1.U, //0001 << addr(2:0) 39 "b01".U -> 0x3.U, //0011 40 "b10".U -> 0xf.U, //1111 41 "b11".U -> 0xff.U //11111111 42 )) << addr(2, 0)).asUInt 43 } 44} 45 46object genVWmask { 47 def apply(addr: UInt, sizeEncode: UInt): UInt = { 48 (LookupTree(sizeEncode, List( 49 "b00".U -> 0x1.U, //0001 << addr(2:0) 50 "b01".U -> 0x3.U, //0011 51 "b10".U -> 0xf.U, //1111 52 "b11".U -> 0xff.U //11111111 53 )) << addr(3, 0)).asUInt 54 } 55} 56 57object genWdata { 58 def apply(data: UInt, sizeEncode: UInt): UInt = { 59 LookupTree(sizeEncode, List( 60 "b00".U -> Fill(16, data(7, 0)), 61 "b01".U -> Fill(8, data(15, 0)), 62 "b10".U -> Fill(4, data(31, 0)), 63 "b11".U -> Fill(2, data(63,0)) 64 )) 65 } 66} 67 68object shiftDataToLow { 69 def apply(addr: UInt, data : UInt): UInt = { 70 Mux(addr(3), (data >> 64).asUInt, data) 71 } 72} 73object shiftMaskToLow { 74 def apply(addr: UInt, mask: UInt): UInt = { 75 Mux(addr(3), (mask >> 8).asUInt, mask) 76 } 77} 78object shiftDataToHigh { 79 def apply(addr: UInt, data : UInt): UInt = { 80 Mux(addr(3), (data << 64).asUInt, data) 81 } 82} 83object shiftMaskToHigh { 84 def apply(addr: UInt, mask: UInt): UInt = { 85 Mux(addr(3), (mask << 8).asUInt, mask) 86 } 87} 88 89class LsPipelineBundle(implicit p: Parameters) extends XSBundle 90 with HasDCacheParameters 91 with HasVLSUParameters { 92 val uop = new DynInst 93 val vaddr = UInt(VAddrBits.W) 94 // For exception vaddr generate 95 val fullva = UInt(XLEN.W) 96 val vaNeedExt = Bool() 97 val isHyper = Bool() 98 val paddr = UInt(PAddrBits.W) 99 val gpaddr = UInt(XLEN.W) 100 val isForVSnonLeafPTE = Bool() 101 // val func = UInt(6.W) 102 val mask = UInt((VLEN/8).W) 103 val data = UInt((VLEN+1).W) 104 val wlineflag = Bool() // store write the whole cache line 105 106 val miss = Bool() 107 val tlbMiss = Bool() 108 val ptwBack = Bool() 109 val af = Bool() 110 val nc = Bool() 111 val mmio = Bool() 112 val atomic = Bool() 113 114 val forwardMask = Vec(VLEN/8, Bool()) 115 val forwardData = Vec(VLEN/8, UInt(8.W)) 116 117 // prefetch 118 val isPrefetch = Bool() 119 val isHWPrefetch = Bool() 120 def isSWPrefetch = isPrefetch && !isHWPrefetch 121 122 // misalignBuffer 123 val isFrmMisAlignBuf = Bool() 124 125 // vector 126 val isvec = Bool() 127 val isLastElem = Bool() 128 val is128bit = Bool() 129 val uop_unit_stride_fof = Bool() 130 val usSecondInv = Bool() 131 val elemIdx = UInt(elemIdxBits.W) 132 val alignedType = UInt(alignTypeBits.W) 133 val mbIndex = UInt(max(vlmBindexBits, vsmBindexBits).W) 134 // val rob_idx_valid = Vec(2,Bool()) 135 // val inner_idx = Vec(2,UInt(3.W)) 136 // val rob_idx = Vec(2,new RobPtr) 137 val reg_offset = UInt(vOffsetBits.W) 138 val elemIdxInsideVd = UInt(elemIdxBits.W) 139 // val offset = Vec(2,UInt(4.W)) 140 val vecActive = Bool() // 1: vector active element or scala mem operation, 0: vector not active element 141 val is_first_ele = Bool() 142 val vecBaseVaddr = UInt(VAddrBits.W) 143 val vecVaddrOffset = UInt(VAddrBits.W) 144 val vecTriggerMask = UInt((VLEN/8).W) 145 // val flowPtr = new VlflowPtr() // VLFlowQueue ptr 146 // val sflowPtr = new VsFlowPtr() // VSFlowQueue ptr 147 148 // For debug usage 149 val isFirstIssue = Bool() 150 val hasROBEntry = Bool() 151 152 // For load replay 153 val isLoadReplay = Bool() 154 val isFastPath = Bool() 155 val isFastReplay = Bool() 156 val replayCarry = new ReplayCarry(nWays) 157 158 // For dcache miss load 159 val mshrid = UInt(log2Up(cfg.nMissEntries).W) 160 val handledByMSHR = Bool() 161 val replacementUpdated = Bool() 162 val missDbUpdated = Bool() 163 164 val forward_tlDchannel = Bool() 165 val dcacheRequireReplay = Bool() 166 val delayedLoadError = Bool() 167 val lateKill = Bool() 168 val feedbacked = Bool() 169 val ldCancel = ValidUndirectioned(UInt(log2Ceil(LoadPipelineWidth).W)) 170 // loadQueueReplay index. 171 val schedIndex = UInt(log2Up(LoadQueueReplaySize).W) 172 // hardware prefetch and fast replay no need to query tlb 173 val tlbNoQuery = Bool() 174} 175 176class LdPrefetchTrainBundle(implicit p: Parameters) extends LsPipelineBundle { 177 val meta_prefetch = UInt(L1PfSourceBits.W) 178 val meta_access = Bool() 179 180 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false, enable: Bool = true.B) = { 181 if (latch) vaddr := RegEnable(input.vaddr, enable) else vaddr := input.vaddr 182 if (latch) fullva := RegEnable(input.fullva, enable) else fullva := input.fullva 183 if (latch) vaNeedExt := RegEnable(input.vaNeedExt, enable) else vaNeedExt := input.vaNeedExt 184 if (latch) isHyper := RegEnable(input.isHyper, enable) else isHyper := input.isHyper 185 if (latch) paddr := RegEnable(input.paddr, enable) else paddr := input.paddr 186 if (latch) gpaddr := RegEnable(input.gpaddr, enable) else gpaddr := input.gpaddr 187 if (latch) isForVSnonLeafPTE := RegEnable(input.isForVSnonLeafPTE, enable) else isForVSnonLeafPTE := input.isForVSnonLeafPTE 188 if (latch) mask := RegEnable(input.mask, enable) else mask := input.mask 189 if (latch) data := RegEnable(input.data, enable) else data := input.data 190 if (latch) uop := RegEnable(input.uop, enable) else uop := input.uop 191 if (latch) wlineflag := RegEnable(input.wlineflag, enable) else wlineflag := input.wlineflag 192 if (latch) miss := RegEnable(input.miss, enable) else miss := input.miss 193 if (latch) tlbMiss := RegEnable(input.tlbMiss, enable) else tlbMiss := input.tlbMiss 194 if (latch) ptwBack := RegEnable(input.ptwBack, enable) else ptwBack := input.ptwBack 195 if (latch) af := RegEnable(input.af, enable) else af := input.af 196 if (latch) nc := RegEnable(input.nc, enable) else nc := input.nc 197 if (latch) mmio := RegEnable(input.mmio, enable) else mmio := input.mmio 198 if (latch) forwardMask := RegEnable(input.forwardMask, enable) else forwardMask := input.forwardMask 199 if (latch) forwardData := RegEnable(input.forwardData, enable) else forwardData := input.forwardData 200 if (latch) isPrefetch := RegEnable(input.isPrefetch, enable) else isPrefetch := input.isPrefetch 201 if (latch) isHWPrefetch := RegEnable(input.isHWPrefetch, enable) else isHWPrefetch := input.isHWPrefetch 202 if (latch) isFrmMisAlignBuf := RegEnable(input.isFrmMisAlignBuf, enable) else isFrmMisAlignBuf := input.isFrmMisAlignBuf 203 if (latch) isFirstIssue := RegEnable(input.isFirstIssue, enable) else isFirstIssue := input.isFirstIssue 204 if (latch) hasROBEntry := RegEnable(input.hasROBEntry, enable) else hasROBEntry := input.hasROBEntry 205 if (latch) dcacheRequireReplay := RegEnable(input.dcacheRequireReplay, enable) else dcacheRequireReplay := input.dcacheRequireReplay 206 if (latch) schedIndex := RegEnable(input.schedIndex, enable) else schedIndex := input.schedIndex 207 if (latch) tlbNoQuery := RegEnable(input.tlbNoQuery, enable) else tlbNoQuery := input.tlbNoQuery 208 if (latch) isvec := RegEnable(input.isvec, enable) else isvec := input.isvec 209 if (latch) isLastElem := RegEnable(input.isLastElem, enable) else isLastElem := input.isLastElem 210 if (latch) is128bit := RegEnable(input.is128bit, enable) else is128bit := input.is128bit 211 if (latch) vecActive := RegEnable(input.vecActive, enable) else vecActive := input.vecActive 212 if (latch) is_first_ele := RegEnable(input.is_first_ele, enable) else is_first_ele := input.is_first_ele 213 if (latch) uop_unit_stride_fof := RegEnable(input.uop_unit_stride_fof, enable) else uop_unit_stride_fof := input.uop_unit_stride_fof 214 if (latch) usSecondInv := RegEnable(input.usSecondInv, enable) else usSecondInv := input.usSecondInv 215 if (latch) reg_offset := RegEnable(input.reg_offset, enable) else reg_offset := input.reg_offset 216 if (latch) elemIdx := RegEnable(input.elemIdx, enable) else elemIdx := input.elemIdx 217 if (latch) alignedType := RegEnable(input.alignedType, enable) else alignedType := input.alignedType 218 if (latch) mbIndex := RegEnable(input.mbIndex, enable) else mbIndex := input.mbIndex 219 if (latch) elemIdxInsideVd := RegEnable(input.elemIdxInsideVd, enable) else elemIdxInsideVd := input.elemIdxInsideVd 220 if (latch) vecBaseVaddr := RegEnable(input.vecBaseVaddr, enable) else vecBaseVaddr := input.vecBaseVaddr 221 if (latch) vecVaddrOffset := RegEnable(input.vecVaddrOffset, enable) else vecVaddrOffset := input.vecVaddrOffset 222 if (latch) vecTriggerMask := RegEnable(input.vecTriggerMask, enable) else vecTriggerMask := input.vecTriggerMask 223 // if (latch) flowPtr := RegEnable(input.flowPtr, enable) else flowPtr := input.flowPtr 224 // if (latch) sflowPtr := RegEnable(input.sflowPtr, enable) else sflowPtr := input.sflowPtr 225 226 meta_prefetch := DontCare 227 meta_access := DontCare 228 forward_tlDchannel := DontCare 229 mshrid := DontCare 230 replayCarry := DontCare 231 atomic := DontCare 232 isLoadReplay := DontCare 233 isFastPath := DontCare 234 isFastReplay := DontCare 235 handledByMSHR := DontCare 236 replacementUpdated := DontCare 237 missDbUpdated := DontCare 238 delayedLoadError := DontCare 239 lateKill := DontCare 240 feedbacked := DontCare 241 ldCancel := DontCare 242 } 243 244 def asPrefetchReqBundle(): PrefetchReqBundle = { 245 val res = Wire(new PrefetchReqBundle) 246 res.vaddr := this.vaddr 247 res.paddr := this.paddr 248 res.pc := this.uop.pc 249 res.miss := this.miss 250 res.pfHitStream := isFromStream(this.meta_prefetch) 251 252 res 253 } 254} 255 256class StPrefetchTrainBundle(implicit p: Parameters) extends LdPrefetchTrainBundle {} 257 258class LqWriteBundle(implicit p: Parameters) extends LsPipelineBundle { 259 // load inst replay informations 260 val rep_info = new LoadToLsqReplayIO 261 // queue entry data, except flag bits, will be updated if writeQueue is true, 262 // valid bit in LqWriteBundle will be ignored 263 val data_wen_dup = Vec(6, Bool()) // dirty reg dup 264 265 266 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false, enable: Bool = true.B) = { 267 if(latch) vaddr := RegEnable(input.vaddr, enable) else vaddr := input.vaddr 268 if(latch) fullva := RegEnable(input.fullva, enable) else fullva := input.fullva 269 if(latch) vaNeedExt := RegEnable(input.vaNeedExt, enable) else vaNeedExt := input.vaNeedExt 270 if(latch) isHyper := RegEnable(input.isHyper, enable) else isHyper := input.isHyper 271 if(latch) paddr := RegEnable(input.paddr, enable) else paddr := input.paddr 272 if(latch) gpaddr := RegEnable(input.gpaddr, enable) else gpaddr := input.gpaddr 273 if(latch) isForVSnonLeafPTE := RegEnable(input.isForVSnonLeafPTE, enable) else isForVSnonLeafPTE := input.isForVSnonLeafPTE 274 if(latch) mask := RegEnable(input.mask, enable) else mask := input.mask 275 if(latch) data := RegEnable(input.data, enable) else data := input.data 276 if(latch) uop := RegEnable(input.uop, enable) else uop := input.uop 277 if(latch) wlineflag := RegEnable(input.wlineflag, enable) else wlineflag := input.wlineflag 278 if(latch) miss := RegEnable(input.miss, enable) else miss := input.miss 279 if(latch) tlbMiss := RegEnable(input.tlbMiss, enable) else tlbMiss := input.tlbMiss 280 if(latch) ptwBack := RegEnable(input.ptwBack, enable) else ptwBack := input.ptwBack 281 if(latch) mmio := RegEnable(input.mmio, enable) else mmio := input.mmio 282 if(latch) atomic := RegEnable(input.atomic, enable) else atomic := input.atomic 283 if(latch) forwardMask := RegEnable(input.forwardMask, enable) else forwardMask := input.forwardMask 284 if(latch) forwardData := RegEnable(input.forwardData, enable) else forwardData := input.forwardData 285 if(latch) isPrefetch := RegEnable(input.isPrefetch, enable) else isPrefetch := input.isPrefetch 286 if(latch) isHWPrefetch := RegEnable(input.isHWPrefetch, enable) else isHWPrefetch := input.isHWPrefetch 287 if(latch) isFrmMisAlignBuf := RegEnable(input.isFrmMisAlignBuf, enable) else isFrmMisAlignBuf := input.isFrmMisAlignBuf 288 if(latch) isFirstIssue := RegEnable(input.isFirstIssue, enable) else isFirstIssue := input.isFirstIssue 289 if(latch) hasROBEntry := RegEnable(input.hasROBEntry, enable) else hasROBEntry := input.hasROBEntry 290 if(latch) isLoadReplay := RegEnable(input.isLoadReplay, enable) else isLoadReplay := input.isLoadReplay 291 if(latch) isFastPath := RegEnable(input.isFastPath, enable) else isFastPath := input.isFastPath 292 if(latch) isFastReplay := RegEnable(input.isFastReplay, enable) else isFastReplay := input.isFastReplay 293 if(latch) mshrid := RegEnable(input.mshrid, enable) else mshrid := input.mshrid 294 if(latch) forward_tlDchannel := RegEnable(input.forward_tlDchannel, enable) else forward_tlDchannel := input.forward_tlDchannel 295 if(latch) replayCarry := RegEnable(input.replayCarry, enable) else replayCarry := input.replayCarry 296 if(latch) dcacheRequireReplay := RegEnable(input.dcacheRequireReplay, enable) else dcacheRequireReplay := input.dcacheRequireReplay 297 if(latch) schedIndex := RegEnable(input.schedIndex, enable) else schedIndex := input.schedIndex 298 if(latch) handledByMSHR := RegEnable(input.handledByMSHR, enable) else handledByMSHR := input.handledByMSHR 299 if(latch) replacementUpdated := RegEnable(input.replacementUpdated, enable) else replacementUpdated := input.replacementUpdated 300 if(latch) missDbUpdated := RegEnable(input.missDbUpdated, enable) else missDbUpdated := input.missDbUpdated 301 if(latch) delayedLoadError := RegEnable(input.delayedLoadError, enable) else delayedLoadError := input.delayedLoadError 302 if(latch) lateKill := RegEnable(input.lateKill, enable) else lateKill := input.lateKill 303 if(latch) feedbacked := RegEnable(input.feedbacked, enable) else feedbacked := input.feedbacked 304 if(latch) isvec := RegEnable(input.isvec, enable) else isvec := input.isvec 305 if(latch) is128bit := RegEnable(input.is128bit, enable) else is128bit := input.is128bit 306 if(latch) vecActive := RegEnable(input.vecActive, enable) else vecActive := input.vecActive 307 if(latch) uop_unit_stride_fof := RegEnable(input.uop_unit_stride_fof, enable) else uop_unit_stride_fof := input.uop_unit_stride_fof 308 if(latch) reg_offset := RegEnable(input.reg_offset, enable) else reg_offset := input.reg_offset 309 if(latch) mbIndex := RegEnable(input.mbIndex, enable) else mbIndex := input.mbIndex 310 if(latch) elemIdxInsideVd := RegEnable(input.elemIdxInsideVd, enable) else elemIdxInsideVd := input.elemIdxInsideVd 311 312 rep_info := DontCare 313 data_wen_dup := DontCare 314 } 315} 316 317class SqWriteBundle(implicit p: Parameters) extends LsPipelineBundle { 318 val need_rep = Bool() 319} 320 321class LoadForwardQueryIO(implicit p: Parameters) extends XSBundle { 322 val vaddr = Output(UInt(VAddrBits.W)) 323 val paddr = Output(UInt(PAddrBits.W)) 324 val mask = Output(UInt((VLEN/8).W)) 325 val uop = Output(new DynInst) // for replay 326 val pc = Output(UInt(VAddrBits.W)) //for debug 327 val valid = Output(Bool()) 328 329 val forwardMaskFast = Input(Vec((VLEN/8), Bool())) // resp to load_s1 330 val forwardMask = Input(Vec((VLEN/8), Bool())) // resp to load_s2 331 val forwardData = Input(Vec((VLEN/8), UInt(8.W))) // resp to load_s2 332 333 // val lqIdx = Output(UInt(LoadQueueIdxWidth.W)) 334 val sqIdx = Output(new SqPtr) 335 336 // dataInvalid suggests store to load forward found forward should happen, 337 // but data is not available for now. If dataInvalid, load inst should 338 // be replayed from RS. Feedback type should be RSFeedbackType.dataInvalid 339 val dataInvalid = Input(Bool()) // Addr match, but data is not valid for now 340 341 // matchInvalid suggests in store to load forward logic, paddr cam result does 342 // to equal to vaddr cam result. If matchInvalid, a microarchitectural exception 343 // should be raised to flush SQ and committed sbuffer. 344 val matchInvalid = Input(Bool()) // resp to load_s2 345 346 // addrInvalid suggests store to load forward found forward should happen, 347 // but address (SSID) is not available for now. If addrInvalid, load inst should 348 // be replayed from RS. Feedback type should be RSFeedbackType.addrInvalid 349 val addrInvalid = Input(Bool()) 350} 351 352// LoadForwardQueryIO used in load pipeline 353// 354// Difference between PipeLoadForwardQueryIO and LoadForwardQueryIO: 355// PipeIO use predecoded sqIdxMask for better forward timing 356class PipeLoadForwardQueryIO(implicit p: Parameters) extends LoadForwardQueryIO { 357 // val sqIdx = Output(new SqPtr) // for debug, should not be used in pipeline for timing reasons 358 // sqIdxMask is calcuated in earlier stage for better timing 359 val sqIdxMask = Output(UInt(StoreQueueSize.W)) 360 361 // dataInvalid: addr match, but data is not valid for now 362 val dataInvalidFast = Input(Bool()) // resp to load_s1 363 // val dataInvalid = Input(Bool()) // resp to load_s2 364 val dataInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 365 val addrInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 366} 367 368// Query load queue for ld-ld violation 369// 370// Req should be send in load_s1 371// Resp will be generated 1 cycle later 372// 373// Note that query req may be !ready, as dcache is releasing a block 374// If it happens, a replay from rs is needed. 375class LoadNukeQueryReq(implicit p: Parameters) extends XSBundle { // provide lqIdx 376 val uop = new DynInst 377 // mask: load's data mask. 378 val mask = UInt((VLEN/8).W) 379 380 // paddr: load's paddr. 381 val paddr = UInt(PAddrBits.W) 382 // dataInvalid: load data is invalid. 383 val data_valid = Bool() 384 // nc: is NC access 385 val is_nc = Bool() 386} 387 388class LoadNukeQueryResp(implicit p: Parameters) extends XSBundle { 389 // rep_frm_fetch: ld-ld violation check success, replay from fetch. 390 val rep_frm_fetch = Bool() 391} 392 393class LoadNukeQueryIO(implicit p: Parameters) extends XSBundle { 394 val req = Decoupled(new LoadNukeQueryReq) 395 val resp = Flipped(Valid(new LoadNukeQueryResp)) 396 val revoke = Output(Bool()) 397} 398 399class StoreNukeQueryIO(implicit p: Parameters) extends XSBundle { 400 // robIdx: Requestor's (a store instruction) rob index for match logic. 401 val robIdx = new RobPtr 402 403 // paddr: requestor's (a store instruction) physical address for match logic. 404 val paddr = UInt(PAddrBits.W) 405 406 // mask: requestor's (a store instruction) data width mask for match logic. 407 val mask = UInt((VLEN/8).W) 408 409 // matchLine: if store is vector 128-bits, load unit need to compare 128-bits vaddr. 410 val matchLine = Bool() 411} 412 413class StoreMaBufToSqControlIO(implicit p: Parameters) extends XSBundle { 414 // from storeMisalignBuffer to storeQueue, control it's sbuffer write 415 val control = Output(new XSBundle { 416 // control sq to write-into sb 417 val writeSb = Bool() 418 val wdata = UInt(VLEN.W) 419 val wmask = UInt((VLEN / 8).W) 420 val paddr = UInt(PAddrBits.W) 421 val vaddr = UInt(VAddrBits.W) 422 val last = Bool() 423 val hasException = Bool() 424 // remove this entry in sq 425 val removeSq = Bool() 426 }) 427 // from storeQueue to storeMisalignBuffer, provide detail info of this store 428 val storeInfo = Input(new XSBundle { 429 val data = UInt(VLEN.W) 430 // is the data of the unaligned store ready at sq? 431 val dataReady = Bool() 432 // complete a data transfer from sq to sb 433 val completeSbTrans = Bool() 434 }) 435} 436 437// Store byte valid mask write bundle 438// 439// Store byte valid mask write to SQ takes 2 cycles 440class StoreMaskBundle(implicit p: Parameters) extends XSBundle { 441 val sqIdx = new SqPtr 442 val mask = UInt((VLEN/8).W) 443} 444 445class LoadDataFromDcacheBundle(implicit p: Parameters) extends DCacheBundle { 446 // old dcache: optimize data sram read fanout 447 // val bankedDcacheData = Vec(DCacheBanks, UInt(64.W)) 448 // val bank_oh = UInt(DCacheBanks.W) 449 450 // new dcache 451 val respDcacheData = UInt(VLEN.W) 452 val forwardMask = Vec(VLEN/8, Bool()) 453 val forwardData = Vec(VLEN/8, UInt(8.W)) 454 val uop = new DynInst // for data selection, only fwen and fuOpType are used 455 val addrOffset = UInt(4.W) // for data selection 456 457 // forward tilelink D channel 458 val forward_D = Bool() 459 val forwardData_D = Vec(VLEN/8, UInt(8.W)) 460 461 // forward mshr data 462 val forward_mshr = Bool() 463 val forwardData_mshr = Vec(VLEN/8, UInt(8.W)) 464 465 val forward_result_valid = Bool() 466 467 def mergeTLData(): UInt = { 468 // merge TL D or MSHR data at load s2 469 val dcache_data = respDcacheData 470 val use_D = forward_D && forward_result_valid 471 val use_mshr = forward_mshr && forward_result_valid 472 Mux( 473 use_D || use_mshr, 474 Mux( 475 use_D, 476 forwardData_D.asUInt, 477 forwardData_mshr.asUInt 478 ), 479 dcache_data 480 ) 481 } 482 483 def mergeLsqFwdData(dcacheData: UInt): UInt = { 484 // merge dcache and lsq forward data at load s3 485 val rdataVec = VecInit((0 until VLEN / 8).map(j => 486 Mux(forwardMask(j), forwardData(j), dcacheData(8*(j+1)-1, 8*j)) 487 )) 488 rdataVec.asUInt 489 } 490} 491 492// Load writeback data from load queue (refill) 493class LoadDataFromLQBundle(implicit p: Parameters) extends XSBundle { 494 val lqData = UInt(64.W) // load queue has merged data 495 val uop = new DynInst // for data selection, only fwen and fuOpType are used 496 val addrOffset = UInt(3.W) // for data selection 497 498 def mergedData(): UInt = { 499 lqData 500 } 501} 502 503// Bundle for load / store wait waking up 504class MemWaitUpdateReq(implicit p: Parameters) extends XSBundle { 505 val robIdx = Vec(backendParams.StaExuCnt, ValidIO(new RobPtr)) 506 val sqIdx = Vec(backendParams.StdCnt, ValidIO(new SqPtr)) 507} 508 509object AddPipelineReg { 510 class PipelineRegModule[T <: Data](gen: T) extends Module { 511 val io = IO(new Bundle() { 512 val in = Flipped(DecoupledIO(gen.cloneType)) 513 val out = DecoupledIO(gen.cloneType) 514 val isFlush = Input(Bool()) 515 }) 516 517 val valid = RegInit(false.B) 518 valid.suggestName("pipeline_reg_valid") 519 when (io.out.fire) { valid := false.B } 520 when (io.in.fire) { valid := true.B } 521 when (io.isFlush) { valid := false.B } 522 523 io.in.ready := !valid || io.out.ready 524 io.out.bits := RegEnable(io.in.bits, io.in.fire) 525 io.out.valid := valid //&& !isFlush 526 } 527 528 def apply[T <: Data] 529 (left: DecoupledIO[T], right: DecoupledIO[T], isFlush: Bool, 530 moduleName: Option[String] = None 531 ): Unit = { 532 val pipelineReg = Module(new PipelineRegModule[T](left.bits.cloneType)) 533 if(moduleName.nonEmpty) pipelineReg.suggestName(moduleName.get) 534 pipelineReg.io.in <> left 535 right <> pipelineReg.io.out 536 pipelineReg.io.isFlush := isFlush 537 } 538}