1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: 9* http://license.coscl.org.cn/MulanPSL2 10* 11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14* 15* See the Mulan PSL v2 for more details. 16***************************************************************************************/ 17 18package xiangshan.mem 19 20 21import org.chipsalliance.cde.config.Parameters 22import chisel3._ 23import chisel3.util._ 24import utility._ 25import utils._ 26import xiangshan._ 27import xiangshan.backend.Bundles._ 28import xiangshan.backend.rob.RobPtr 29import xiangshan.backend.fu.FenceToSbuffer 30import xiangshan.backend.fu.vector.Bundles._ 31import xiangshan.backend.Bundles._ 32import xiangshan.mem.prefetch.PrefetchReqBundle 33import xiangshan.cache._ 34import xiangshan.cache.wpu.ReplayCarry 35import xiangshan.cache.mmu._ 36import math._ 37 38object Bundles { 39 40 class LsPipelineBundle(implicit p: Parameters) extends XSBundle 41 with HasDCacheParameters 42 with HasVLSUParameters { 43 val uop = new DynInst 44 val vaddr = UInt(VAddrBits.W) 45 // For exception vaddr generate 46 val fullva = UInt(XLEN.W) 47 val vaNeedExt = Bool() 48 val isHyper = Bool() 49 val paddr = UInt(PAddrBits.W) 50 val gpaddr = UInt(XLEN.W) 51 val isForVSnonLeafPTE = Bool() 52 // val func = UInt(6.W) 53 val mask = UInt((VLEN/8).W) 54 val data = UInt((VLEN+1).W) 55 val wlineflag = Bool() // store write the whole cache line 56 57 val miss = Bool() 58 val tlbMiss = Bool() 59 val ptwBack = Bool() 60 val af = Bool() 61 val nc = Bool() 62 val mmio = Bool() 63 val memBackTypeMM = Bool() // 1: main memory, 0: IO 64 val atomic = Bool() 65 val hasException = Bool() 66 67 val forwardMask = Vec(VLEN/8, Bool()) 68 val forwardData = Vec(VLEN/8, UInt(8.W)) 69 70 // prefetch 71 val isPrefetch = Bool() 72 val isHWPrefetch = Bool() 73 def isSWPrefetch = isPrefetch && !isHWPrefetch 74 75 // misalignBuffer 76 val isFrmMisAlignBuf = Bool() 77 78 // vector 79 val isvec = Bool() 80 val isLastElem = Bool() 81 val is128bit = Bool() 82 val uop_unit_stride_fof = Bool() 83 val usSecondInv = Bool() 84 val elemIdx = UInt(elemIdxBits.W) 85 val alignedType = UInt(alignTypeBits.W) 86 val mbIndex = UInt(max(vlmBindexBits, vsmBindexBits).W) 87 // val rob_idx_valid = Vec(2,Bool()) 88 // val inner_idx = Vec(2,UInt(3.W)) 89 // val rob_idx = Vec(2,new RobPtr) 90 val reg_offset = UInt(vOffsetBits.W) 91 val elemIdxInsideVd = UInt(elemIdxBits.W) 92 // val offset = Vec(2,UInt(4.W)) 93 val vecActive = Bool() // 1: vector active element or scala mem operation, 0: vector not active element 94 val is_first_ele = Bool() 95 val vecBaseVaddr = UInt(VAddrBits.W) 96 val vecVaddrOffset = UInt(VAddrBits.W) 97 val vecTriggerMask = UInt((VLEN/8).W) 98 // val flowPtr = new VlflowPtr() // VLFlowQueue ptr 99 // val sflowPtr = new VsFlowPtr() // VSFlowQueue ptr 100 101 // For debug usage 102 val isFirstIssue = Bool() 103 val hasROBEntry = Bool() 104 105 // For load replay 106 val isLoadReplay = Bool() 107 val isFastPath = Bool() 108 val isFastReplay = Bool() 109 val replayCarry = new ReplayCarry(nWays) 110 111 // For dcache miss load 112 val mshrid = UInt(log2Up(cfg.nMissEntries).W) 113 val handledByMSHR = Bool() 114 val replacementUpdated = Bool() 115 val missDbUpdated = Bool() 116 117 val forward_tlDchannel = Bool() 118 val dcacheRequireReplay = Bool() 119 val delayedLoadError = Bool() 120 val lateKill = Bool() 121 val feedbacked = Bool() 122 val ldCancel = ValidUndirectioned(UInt(log2Ceil(LoadPipelineWidth).W)) 123 // loadQueueReplay index. 124 val schedIndex = UInt(log2Up(LoadQueueReplaySize).W) 125 // hardware prefetch and fast replay no need to query tlb 126 val tlbNoQuery = Bool() 127 128 // misalign 129 val isMisalign = Bool() 130 val isFinalSplit = Bool() 131 val misalignWith16Byte = Bool() 132 val misalignNeedWakeUp = Bool() 133 val updateAddrValid = Bool() 134 } 135 136 class LdPrefetchTrainBundle(implicit p: Parameters) extends LsPipelineBundle { 137 val meta_prefetch = UInt(L1PfSourceBits.W) 138 val meta_access = Bool() 139 140 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false, enable: Bool = true.B) = { 141 if (latch) vaddr := RegEnable(input.vaddr, enable) else vaddr := input.vaddr 142 if (latch) fullva := RegEnable(input.fullva, enable) else fullva := input.fullva 143 if (latch) vaNeedExt := RegEnable(input.vaNeedExt, enable) else vaNeedExt := input.vaNeedExt 144 if (latch) isHyper := RegEnable(input.isHyper, enable) else isHyper := input.isHyper 145 if (latch) paddr := RegEnable(input.paddr, enable) else paddr := input.paddr 146 if (latch) gpaddr := RegEnable(input.gpaddr, enable) else gpaddr := input.gpaddr 147 if (latch) isForVSnonLeafPTE := RegEnable(input.isForVSnonLeafPTE, enable) else isForVSnonLeafPTE := input.isForVSnonLeafPTE 148 if (latch) mask := RegEnable(input.mask, enable) else mask := input.mask 149 if (latch) data := RegEnable(input.data, enable) else data := input.data 150 if (latch) uop := RegEnable(input.uop, enable) else uop := input.uop 151 if (latch) wlineflag := RegEnable(input.wlineflag, enable) else wlineflag := input.wlineflag 152 if (latch) miss := RegEnable(input.miss, enable) else miss := input.miss 153 if (latch) tlbMiss := RegEnable(input.tlbMiss, enable) else tlbMiss := input.tlbMiss 154 if (latch) ptwBack := RegEnable(input.ptwBack, enable) else ptwBack := input.ptwBack 155 if (latch) af := RegEnable(input.af, enable) else af := input.af 156 if (latch) nc := RegEnable(input.nc, enable) else nc := input.nc 157 if (latch) mmio := RegEnable(input.mmio, enable) else mmio := input.mmio 158 if (latch) memBackTypeMM := RegEnable(input.memBackTypeMM, enable) else memBackTypeMM := input.memBackTypeMM 159 if (latch) forwardMask := RegEnable(input.forwardMask, enable) else forwardMask := input.forwardMask 160 if (latch) forwardData := RegEnable(input.forwardData, enable) else forwardData := input.forwardData 161 if (latch) isPrefetch := RegEnable(input.isPrefetch, enable) else isPrefetch := input.isPrefetch 162 if (latch) isHWPrefetch := RegEnable(input.isHWPrefetch, enable) else isHWPrefetch := input.isHWPrefetch 163 if (latch) isFrmMisAlignBuf := RegEnable(input.isFrmMisAlignBuf, enable) else isFrmMisAlignBuf := input.isFrmMisAlignBuf 164 if (latch) isFirstIssue := RegEnable(input.isFirstIssue, enable) else isFirstIssue := input.isFirstIssue 165 if (latch) hasROBEntry := RegEnable(input.hasROBEntry, enable) else hasROBEntry := input.hasROBEntry 166 if (latch) dcacheRequireReplay := RegEnable(input.dcacheRequireReplay, enable) else dcacheRequireReplay := input.dcacheRequireReplay 167 if (latch) schedIndex := RegEnable(input.schedIndex, enable) else schedIndex := input.schedIndex 168 if (latch) tlbNoQuery := RegEnable(input.tlbNoQuery, enable) else tlbNoQuery := input.tlbNoQuery 169 if (latch) isvec := RegEnable(input.isvec, enable) else isvec := input.isvec 170 if (latch) isLastElem := RegEnable(input.isLastElem, enable) else isLastElem := input.isLastElem 171 if (latch) is128bit := RegEnable(input.is128bit, enable) else is128bit := input.is128bit 172 if (latch) vecActive := RegEnable(input.vecActive, enable) else vecActive := input.vecActive 173 if (latch) is_first_ele := RegEnable(input.is_first_ele, enable) else is_first_ele := input.is_first_ele 174 if (latch) uop_unit_stride_fof := RegEnable(input.uop_unit_stride_fof, enable) else uop_unit_stride_fof := input.uop_unit_stride_fof 175 if (latch) usSecondInv := RegEnable(input.usSecondInv, enable) else usSecondInv := input.usSecondInv 176 if (latch) reg_offset := RegEnable(input.reg_offset, enable) else reg_offset := input.reg_offset 177 if (latch) elemIdx := RegEnable(input.elemIdx, enable) else elemIdx := input.elemIdx 178 if (latch) alignedType := RegEnable(input.alignedType, enable) else alignedType := input.alignedType 179 if (latch) mbIndex := RegEnable(input.mbIndex, enable) else mbIndex := input.mbIndex 180 if (latch) elemIdxInsideVd := RegEnable(input.elemIdxInsideVd, enable) else elemIdxInsideVd := input.elemIdxInsideVd 181 if (latch) vecBaseVaddr := RegEnable(input.vecBaseVaddr, enable) else vecBaseVaddr := input.vecBaseVaddr 182 if (latch) vecVaddrOffset := RegEnable(input.vecVaddrOffset, enable) else vecVaddrOffset := input.vecVaddrOffset 183 if (latch) vecTriggerMask := RegEnable(input.vecTriggerMask, enable) else vecTriggerMask := input.vecTriggerMask 184 // if (latch) flowPtr := RegEnable(input.flowPtr, enable) else flowPtr := input.flowPtr 185 // if (latch) sflowPtr := RegEnable(input.sflowPtr, enable) else sflowPtr := input.sflowPtr 186 187 meta_prefetch := DontCare 188 meta_access := DontCare 189 forward_tlDchannel := DontCare 190 mshrid := DontCare 191 replayCarry := DontCare 192 atomic := DontCare 193 isLoadReplay := DontCare 194 isFastPath := DontCare 195 isFastReplay := DontCare 196 handledByMSHR := DontCare 197 replacementUpdated := DontCare 198 missDbUpdated := DontCare 199 delayedLoadError := DontCare 200 lateKill := DontCare 201 feedbacked := DontCare 202 ldCancel := DontCare 203 } 204 205 def asPrefetchReqBundle(): PrefetchReqBundle = { 206 val res = Wire(new PrefetchReqBundle) 207 res.vaddr := this.vaddr 208 res.paddr := this.paddr 209 res.pc := this.uop.pc 210 res.miss := this.miss 211 res.pfHitStream := isFromStream(this.meta_prefetch) 212 213 res 214 } 215 } 216 217 class StPrefetchTrainBundle(implicit p: Parameters) extends LdPrefetchTrainBundle {} 218 219 class LqWriteBundle(implicit p: Parameters) extends LsPipelineBundle { 220 // load inst replay informations 221 val rep_info = new LoadToLsqReplayIO 222 val nc_with_data = Bool() // nc access with data 223 // queue entry data, except flag bits, will be updated if writeQueue is true, 224 // valid bit in LqWriteBundle will be ignored 225 val data_wen_dup = Vec(6, Bool()) // dirty reg dup 226 227 228 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false, enable: Bool = true.B) = { 229 if(latch) vaddr := RegEnable(input.vaddr, enable) else vaddr := input.vaddr 230 if(latch) fullva := RegEnable(input.fullva, enable) else fullva := input.fullva 231 if(latch) vaNeedExt := RegEnable(input.vaNeedExt, enable) else vaNeedExt := input.vaNeedExt 232 if(latch) isHyper := RegEnable(input.isHyper, enable) else isHyper := input.isHyper 233 if(latch) paddr := RegEnable(input.paddr, enable) else paddr := input.paddr 234 if(latch) gpaddr := RegEnable(input.gpaddr, enable) else gpaddr := input.gpaddr 235 if(latch) isForVSnonLeafPTE := RegEnable(input.isForVSnonLeafPTE, enable) else isForVSnonLeafPTE := input.isForVSnonLeafPTE 236 if(latch) mask := RegEnable(input.mask, enable) else mask := input.mask 237 if(latch) data := RegEnable(input.data, enable) else data := input.data 238 if(latch) uop := RegEnable(input.uop, enable) else uop := input.uop 239 if(latch) wlineflag := RegEnable(input.wlineflag, enable) else wlineflag := input.wlineflag 240 if(latch) miss := RegEnable(input.miss, enable) else miss := input.miss 241 if(latch) tlbMiss := RegEnable(input.tlbMiss, enable) else tlbMiss := input.tlbMiss 242 if(latch) ptwBack := RegEnable(input.ptwBack, enable) else ptwBack := input.ptwBack 243 if(latch) mmio := RegEnable(input.mmio, enable) else mmio := input.mmio 244 if(latch) atomic := RegEnable(input.atomic, enable) else atomic := input.atomic 245 if(latch) forwardMask := RegEnable(input.forwardMask, enable) else forwardMask := input.forwardMask 246 if(latch) forwardData := RegEnable(input.forwardData, enable) else forwardData := input.forwardData 247 if(latch) isPrefetch := RegEnable(input.isPrefetch, enable) else isPrefetch := input.isPrefetch 248 if(latch) isHWPrefetch := RegEnable(input.isHWPrefetch, enable) else isHWPrefetch := input.isHWPrefetch 249 if(latch) isFrmMisAlignBuf := RegEnable(input.isFrmMisAlignBuf, enable) else isFrmMisAlignBuf := input.isFrmMisAlignBuf 250 if(latch) isFirstIssue := RegEnable(input.isFirstIssue, enable) else isFirstIssue := input.isFirstIssue 251 if(latch) hasROBEntry := RegEnable(input.hasROBEntry, enable) else hasROBEntry := input.hasROBEntry 252 if(latch) isLoadReplay := RegEnable(input.isLoadReplay, enable) else isLoadReplay := input.isLoadReplay 253 if(latch) isFastPath := RegEnable(input.isFastPath, enable) else isFastPath := input.isFastPath 254 if(latch) isFastReplay := RegEnable(input.isFastReplay, enable) else isFastReplay := input.isFastReplay 255 if(latch) mshrid := RegEnable(input.mshrid, enable) else mshrid := input.mshrid 256 if(latch) forward_tlDchannel := RegEnable(input.forward_tlDchannel, enable) else forward_tlDchannel := input.forward_tlDchannel 257 if(latch) replayCarry := RegEnable(input.replayCarry, enable) else replayCarry := input.replayCarry 258 if(latch) dcacheRequireReplay := RegEnable(input.dcacheRequireReplay, enable) else dcacheRequireReplay := input.dcacheRequireReplay 259 if(latch) schedIndex := RegEnable(input.schedIndex, enable) else schedIndex := input.schedIndex 260 if(latch) handledByMSHR := RegEnable(input.handledByMSHR, enable) else handledByMSHR := input.handledByMSHR 261 if(latch) replacementUpdated := RegEnable(input.replacementUpdated, enable) else replacementUpdated := input.replacementUpdated 262 if(latch) missDbUpdated := RegEnable(input.missDbUpdated, enable) else missDbUpdated := input.missDbUpdated 263 if(latch) delayedLoadError := RegEnable(input.delayedLoadError, enable) else delayedLoadError := input.delayedLoadError 264 if(latch) lateKill := RegEnable(input.lateKill, enable) else lateKill := input.lateKill 265 if(latch) feedbacked := RegEnable(input.feedbacked, enable) else feedbacked := input.feedbacked 266 if(latch) isvec := RegEnable(input.isvec, enable) else isvec := input.isvec 267 if(latch) is128bit := RegEnable(input.is128bit, enable) else is128bit := input.is128bit 268 if(latch) vecActive := RegEnable(input.vecActive, enable) else vecActive := input.vecActive 269 if(latch) uop_unit_stride_fof := RegEnable(input.uop_unit_stride_fof, enable) else uop_unit_stride_fof := input.uop_unit_stride_fof 270 if(latch) reg_offset := RegEnable(input.reg_offset, enable) else reg_offset := input.reg_offset 271 if(latch) mbIndex := RegEnable(input.mbIndex, enable) else mbIndex := input.mbIndex 272 if(latch) elemIdxInsideVd := RegEnable(input.elemIdxInsideVd, enable) else elemIdxInsideVd := input.elemIdxInsideVd 273 274 rep_info := DontCare 275 data_wen_dup := DontCare 276 } 277 } 278 279 class SqWriteBundle(implicit p: Parameters) extends LsPipelineBundle { 280 val need_rep = Bool() 281 } 282 283 class LoadForwardQueryIO(implicit p: Parameters) extends XSBundle { 284 val vaddr = Output(UInt(VAddrBits.W)) 285 val paddr = Output(UInt(PAddrBits.W)) 286 val mask = Output(UInt((VLEN/8).W)) 287 val uop = Output(new DynInst) // for replay 288 val pc = Output(UInt(VAddrBits.W)) //for debug 289 val valid = Output(Bool()) 290 291 val forwardMaskFast = Input(Vec((VLEN/8), Bool())) // resp to load_s1 292 val forwardMask = Input(Vec((VLEN/8), Bool())) // resp to load_s2 293 val forwardData = Input(Vec((VLEN/8), UInt(8.W))) // resp to load_s2 294 295 // val lqIdx = Output(UInt(LoadQueueIdxWidth.W)) 296 val sqIdx = Output(new SqPtr) 297 298 // dataInvalid suggests store to load forward found forward should happen, 299 // but data is not available for now. If dataInvalid, load inst should 300 // be replayed from RS. Feedback type should be RSFeedbackType.dataInvalid 301 val dataInvalid = Input(Bool()) // Addr match, but data is not valid for now 302 303 // matchInvalid suggests in store to load forward logic, paddr cam result does 304 // to equal to vaddr cam result. If matchInvalid, a microarchitectural exception 305 // should be raised to flush SQ and committed sbuffer. 306 val matchInvalid = Input(Bool()) // resp to load_s2 307 308 // addrInvalid suggests store to load forward found forward should happen, 309 // but address (SSID) is not available for now. If addrInvalid, load inst should 310 // be replayed from RS. Feedback type should be RSFeedbackType.addrInvalid 311 val addrInvalid = Input(Bool()) 312 } 313 314 // LoadForwardQueryIO used in load pipeline 315 // 316 // Difference between PipeLoadForwardQueryIO and LoadForwardQueryIO: 317 // PipeIO use predecoded sqIdxMask for better forward timing 318 class PipeLoadForwardQueryIO(implicit p: Parameters) extends LoadForwardQueryIO { 319 // val sqIdx = Output(new SqPtr) // for debug, should not be used in pipeline for timing reasons 320 // sqIdxMask is calcuated in earlier stage for better timing 321 val sqIdxMask = Output(UInt(StoreQueueSize.W)) 322 323 // dataInvalid: addr match, but data is not valid for now 324 val dataInvalidFast = Input(Bool()) // resp to load_s1 325 // val dataInvalid = Input(Bool()) // resp to load_s2 326 val dataInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 327 val addrInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 328 } 329 330 // Query load queue for ld-ld violation 331 // 332 // Req should be send in load_s1 333 // Resp will be generated 1 cycle later 334 // 335 // Note that query req may be !ready, as dcache is releasing a block 336 // If it happens, a replay from rs is needed. 337 class LoadNukeQueryReq(implicit p: Parameters) extends XSBundle { // provide lqIdx 338 val uop = new DynInst 339 // mask: load's data mask. 340 val mask = UInt((VLEN/8).W) 341 342 // paddr: load's paddr. 343 val paddr = UInt(PAddrBits.W) 344 // dataInvalid: load data is invalid. 345 val data_valid = Bool() 346 // nc: is NC access 347 val is_nc = Bool() 348 } 349 350 class LoadNukeQueryResp(implicit p: Parameters) extends XSBundle { 351 // rep_frm_fetch: ld-ld violation check success, replay from fetch. 352 val rep_frm_fetch = Bool() 353 } 354 355 class LoadNukeQueryIO(implicit p: Parameters) extends XSBundle { 356 val req = Decoupled(new LoadNukeQueryReq) 357 val resp = Flipped(Valid(new LoadNukeQueryResp)) 358 val revoke = Output(Bool()) 359 } 360 361 class StoreNukeQueryIO(implicit p: Parameters) extends XSBundle { 362 // robIdx: Requestor's (a store instruction) rob index for match logic. 363 val robIdx = new RobPtr 364 365 // paddr: requestor's (a store instruction) physical address for match logic. 366 val paddr = UInt(PAddrBits.W) 367 368 // mask: requestor's (a store instruction) data width mask for match logic. 369 val mask = UInt((VLEN/8).W) 370 371 // matchLine: if store is vector 128-bits, load unit need to compare 128-bits vaddr. 372 val matchLine = Bool() 373 } 374 375 class StoreMaBufToSqControlIO(implicit p: Parameters) extends XSBundle { 376 // from storeMisalignBuffer to storeQueue, control it's sbuffer write 377 val toStoreQueue = Output(new XSBundle { 378 // This entry is a cross page 379 val crossPageWithHit = Bool() 380 val crossPageCanDeq = Bool() 381 // High page Paddr 382 val paddr = UInt(PAddrBits.W) 383 384 val withSameUop = Bool() 385 }) 386 // from storeQueue to storeMisalignBuffer, provide detail info of this store 387 val toStoreMisalignBuffer = Input(new XSBundle { 388 val sqPtr = new SqPtr 389 val doDeq = Bool() 390 391 val uop = new DynInst() 392 }) 393 } 394 395 class StoreMaBufToVecStoreMergeBufferIO(implicit p: Parameters) extends VLSUBundle{ 396 val mbIndex = Output(UInt(vsmBindexBits.W)) 397 val flush = Output(Bool()) 398 } 399 400 // Store byte valid mask write bundle 401 // 402 // Store byte valid mask write to SQ takes 2 cycles 403 class StoreMaskBundle(implicit p: Parameters) extends XSBundle { 404 val sqIdx = new SqPtr 405 val mask = UInt((VLEN/8).W) 406 } 407 408 class LoadDataFromDcacheBundle(implicit p: Parameters) extends DCacheBundle { 409 // old dcache: optimize data sram read fanout 410 // val bankedDcacheData = Vec(DCacheBanks, UInt(64.W)) 411 // val bank_oh = UInt(DCacheBanks.W) 412 413 // new dcache 414 val respDcacheData = UInt(VLEN.W) 415 val forwardMask = Vec(VLEN/8, Bool()) 416 val forwardData = Vec(VLEN/8, UInt(8.W)) 417 val uop = new DynInst // for data selection, only fwen and fuOpType are used 418 val addrOffset = UInt(4.W) // for data selection 419 420 // forward tilelink D channel 421 val forward_D = Bool() 422 val forwardData_D = Vec(VLEN/8, UInt(8.W)) 423 424 // forward mshr data 425 val forward_mshr = Bool() 426 val forwardData_mshr = Vec(VLEN/8, UInt(8.W)) 427 428 val forward_result_valid = Bool() 429 430 def mergeTLData(): UInt = { 431 // merge TL D or MSHR data at load s2 432 val dcache_data = respDcacheData 433 val use_D = forward_D && forward_result_valid 434 val use_mshr = forward_mshr && forward_result_valid 435 Mux( 436 use_D || use_mshr, 437 Mux( 438 use_D, 439 forwardData_D.asUInt, 440 forwardData_mshr.asUInt 441 ), 442 dcache_data 443 ) 444 } 445 446 def mergeLsqFwdData(dcacheData: UInt): UInt = { 447 // merge dcache and lsq forward data at load s3 448 val rdataVec = VecInit((0 until VLEN / 8).map(j => 449 Mux(forwardMask(j), forwardData(j), dcacheData(8*(j+1)-1, 8*j)) 450 )) 451 rdataVec.asUInt 452 } 453 } 454 455 // Load writeback data from load queue (refill) 456 class LoadDataFromLQBundle(implicit p: Parameters) extends XSBundle { 457 val lqData = UInt(64.W) // load queue has merged data 458 val uop = new DynInst // for data selection, only fwen and fuOpType are used 459 val addrOffset = UInt(3.W) // for data selection 460 461 def mergedData(): UInt = { 462 lqData 463 } 464 } 465 466 // Bundle for load / store wait waking up 467 class MemWaitUpdateReq(implicit p: Parameters) extends XSBundle { 468 val robIdx = Vec(backendParams.StaExuCnt, ValidIO(new RobPtr)) 469 val sqIdx = Vec(backendParams.StdCnt, ValidIO(new SqPtr)) 470 } 471 472} 473