1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.frontend.icache 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import difftest._ 23import freechips.rocketchip.tilelink._ 24import utils._ 25import xiangshan.cache.mmu._ 26import xiangshan.frontend._ 27import xiangshan.backend.fu.{PMPReqBundle, PMPRespBundle} 28import huancun.PreferCacheKey 29import xiangshan.XSCoreParamsKey 30import utility._ 31 32abstract class IPrefetchBundle(implicit p: Parameters) extends ICacheBundle 33abstract class IPrefetchModule(implicit p: Parameters) extends ICacheModule 34 35class IPrefetchIO(implicit p: Parameters) extends IPrefetchBundle { 36 // control 37 val csr_pf_enable = Input(Bool()) 38 val csr_parity_enable = Input(Bool()) 39 val flush = Input(Bool()) 40 41 val ftqReq = Flipped(new FtqToPrefetchIO) 42 val itlb = Vec(PortNumber, new TlbRequestIO) 43 val pmp = Vec(PortNumber, new ICachePMPBundle) 44 val metaRead = new ICacheMetaReqBundle 45 val MSHRReq = DecoupledIO(new ICacheMissReq) 46 val MSHRResp = Flipped(ValidIO(new ICacheMissResp)) 47 val wayLookupWrite = DecoupledIO(new WayLookupInfo) 48} 49 50class IPrefetchPipe(implicit p: Parameters) extends IPrefetchModule 51{ 52 val io: IPrefetchIO = IO(new IPrefetchIO) 53 54 val fromFtq = io.ftqReq 55 val (toITLB, fromITLB) = (io.itlb.map(_.req), io.itlb.map(_.resp)) 56 val (toPMP, fromPMP) = (io.pmp.map(_.req), io.pmp.map(_.resp)) 57 val (toMeta, fromMeta) = (io.metaRead.toIMeta, io.metaRead.fromIMeta) 58 val (toMSHR, fromMSHR) = (io.MSHRReq, io.MSHRResp) 59 val toWayLookup = io.wayLookupWrite 60 61 val s0_fire, s1_fire, s2_fire = WireInit(false.B) 62 val s0_discard, s2_discard = WireInit(false.B) 63 val s0_ready, s1_ready, s2_ready = WireInit(false.B) 64 val s0_flush, s1_flush, s2_flush = WireInit(false.B) 65 val from_bpu_s0_flush, from_bpu_s1_flush = WireInit(false.B) 66 67 /** 68 ****************************************************************************** 69 * IPrefetch Stage 0 70 * - 1. receive ftq req 71 * - 2. send req to ITLB 72 * - 3. send req to Meta SRAM 73 ****************************************************************************** 74 */ 75 val s0_valid = fromFtq.req.valid 76 77 /** 78 ****************************************************************************** 79 * receive ftq req 80 ****************************************************************************** 81 */ 82 val s0_req_vaddr = VecInit(Seq(fromFtq.req.bits.startAddr, fromFtq.req.bits.nextlineStart)) 83 val s0_req_ftqIdx = fromFtq.req.bits.ftqIdx 84 val s0_doubleline = fromFtq.req.bits.crossCacheline 85 val s0_req_vSetIdx = s0_req_vaddr.map(get_idx) 86 87 from_bpu_s0_flush := fromFtq.flushFromBpu.shouldFlushByStage2(s0_req_ftqIdx) || 88 fromFtq.flushFromBpu.shouldFlushByStage3(s0_req_ftqIdx) 89 s0_flush := io.flush || from_bpu_s0_flush || s1_flush 90 91 val s0_can_go = s1_ready && toITLB(0).ready && toITLB(1).ready && toMeta.ready 92 fromFtq.req.ready := s0_can_go 93 94 s0_fire := s0_valid && s0_can_go && !s0_flush 95 96 /** 97 ****************************************************************************** 98 * IPrefetch Stage 1 99 * - 1. Receive resp from ITLB 100 * - 2. Receive resp from IMeta and check 101 * - 3. Monitor the requests from missUnit to write to SRAM. 102 * - 4. Wirte wayLookup 103 ****************************************************************************** 104 */ 105 val s1_valid = generatePipeControl(lastFire = s0_fire, thisFire = s1_fire, thisFlush = s1_flush, lastFlush = false.B) 106 107 val s1_req_vaddr = RegEnable(s0_req_vaddr, 0.U.asTypeOf(s0_req_vaddr), s0_fire) 108 val s1_doubleline = RegEnable(s0_doubleline, 0.U.asTypeOf(s0_doubleline), s0_fire) 109 val s1_req_ftqIdx = RegEnable(s0_req_ftqIdx, 0.U.asTypeOf(s0_req_ftqIdx), s0_fire) 110 val s1_req_vSetIdx = VecInit(s1_req_vaddr.map(get_idx)) 111 112 val m_idle :: m_itlbResend :: m_metaResend :: m_enqWay :: m_enterS2 :: Nil = Enum(5) 113 val state = RegInit(m_idle) 114 val next_state = WireDefault(state) 115 val s0_fire_r = RegNext(s0_fire) 116 dontTouch(state) 117 dontTouch(next_state) 118 state := next_state 119 120 /** 121 ****************************************************************************** 122 * resend itlb req if miss 123 ****************************************************************************** 124 */ 125 val s1_wait_itlb = RegInit(VecInit(Seq.fill(PortNumber)(false.B))) 126 (0 until PortNumber).foreach { i => 127 when(s1_flush) { 128 s1_wait_itlb(i) := false.B 129 }.elsewhen(RegNext(s0_fire) && fromITLB(i).bits.miss) { 130 s1_wait_itlb(i) := true.B 131 }.elsewhen(s1_wait_itlb(i) && !fromITLB(i).bits.miss) { 132 s1_wait_itlb(i) := false.B 133 } 134 } 135 val s1_need_itlb = VecInit(Seq((RegNext(s0_fire) || s1_wait_itlb(0)) && fromITLB(0).bits.miss, 136 (RegNext(s0_fire) || s1_wait_itlb(1)) && fromITLB(1).bits.miss && s1_doubleline)) 137 val tlb_valid_pulse = VecInit(Seq((RegNext(s0_fire) || s1_wait_itlb(0)) && !fromITLB(0).bits.miss, 138 (RegNext(s0_fire) || s1_wait_itlb(1)) && !fromITLB(1).bits.miss && s1_doubleline)) 139 val tlb_valid_latch = VecInit((0 until PortNumber).map(i => ValidHoldBypass(tlb_valid_pulse(i), s1_fire, flush=s1_flush))) 140 val itlb_finish = tlb_valid_latch(0) && (!s1_doubleline || tlb_valid_latch(1)) 141 142 for (i <- 0 until PortNumber) { 143 toITLB(i).valid := s1_need_itlb(i) || (s0_valid && (if(i == 0) true.B else s0_doubleline)) 144 toITLB(i).bits := DontCare 145 toITLB(i).bits.size := 3.U 146 toITLB(i).bits.vaddr := Mux(s1_need_itlb(i), s1_req_vaddr(i), s0_req_vaddr(i)) 147 toITLB(i).bits.debug.pc := Mux(s1_need_itlb(i), s1_req_vaddr(i), s0_req_vaddr(i)) 148 toITLB(i).bits.cmd := TlbCmd.exec 149 toITLB(i).bits.no_translate := false.B 150 } 151 fromITLB.foreach(_.ready := true.B) 152 io.itlb.foreach(_.req_kill := false.B) 153 154 /** 155 ****************************************************************************** 156 * Receive resp from ITLB 157 ****************************************************************************** 158 */ 159 val s1_req_paddr_wire = VecInit(fromITLB.map(_.bits.paddr(0))) 160 val s1_req_paddr_reg = VecInit((0 until PortNumber).map( i => 161 RegEnable(s1_req_paddr_wire(i), 0.U(PAddrBits.W), tlb_valid_pulse(i)) 162 )) 163 val s1_req_paddr = VecInit((0 until PortNumber).map( i => 164 Mux(tlb_valid_pulse(i), s1_req_paddr_wire(i), s1_req_paddr_reg(i)) 165 )) 166 val s1_req_gpaddr_tmp = VecInit((0 until PortNumber).map( i => 167 ResultHoldBypass(valid = tlb_valid_pulse(i), init = 0.U.asTypeOf(fromITLB(i).bits.gpaddr(0)), data = fromITLB(i).bits.gpaddr(0)) 168 )) 169 val s1_itlb_exception = VecInit((0 until PortNumber).map( i => 170 ResultHoldBypass(valid = tlb_valid_pulse(i), init = 0.U(ExceptionType.width.W), data = ExceptionType.fromTlbResp(fromITLB(i).bits)) 171 )) 172 val s1_itlb_exception_gpf = VecInit(s1_itlb_exception.map(_ === ExceptionType.gpf)) 173 174 /* Select gpaddr with the first gpf 175 * Note: the backend wants the base guest physical address of a fetch block 176 * for port(i), its base gpaddr is actually (gpaddr - i * blocksize) 177 * see GPAMem: https://github.com/OpenXiangShan/XiangShan/blob/344cf5d55568dd40cd658a9ee66047a505eeb504/src/main/scala/xiangshan/backend/GPAMem.scala#L33-L34 178 * see also: https://github.com/OpenXiangShan/XiangShan/blob/344cf5d55568dd40cd658a9ee66047a505eeb504/src/main/scala/xiangshan/frontend/IFU.scala#L374-L375 179 */ 180 val s1_req_gpaddr = PriorityMuxDefault( 181 s1_itlb_exception_gpf zip (0 until PortNumber).map(i => s1_req_gpaddr_tmp(i) - (i << blockOffBits).U), 182 0.U.asTypeOf(s1_req_gpaddr_tmp(0)) 183 ) 184 185 /** 186 ****************************************************************************** 187 * resend metaArray read req when itlb miss finish 188 ****************************************************************************** 189 */ 190 val s1_need_meta = ((state === m_itlbResend) && itlb_finish) || (state === m_metaResend) 191 toMeta.valid := s1_need_meta || s0_valid 192 toMeta.bits := DontCare 193 toMeta.bits.isDoubleLine := Mux(s1_need_meta, s1_doubleline, s0_doubleline) 194 195 for (i <- 0 until PortNumber) { 196 toMeta.bits.vSetIdx(i) := Mux(s1_need_meta, s1_req_vSetIdx(i), s0_req_vSetIdx(i)) 197 } 198 199 /** 200 ****************************************************************************** 201 * Receive resp from IMeta and check 202 ****************************************************************************** 203 */ 204 val s1_req_ptags = VecInit(s1_req_paddr.map(get_phy_tag)) 205 206 val s1_meta_ptags = fromMeta.tags 207 val s1_meta_valids = fromMeta.entryValid 208 // If error is found in either way, the tag_eq_vec is unreliable, so we do not use waymask, but directly .orR 209 val s1_meta_corrupt = VecInit(fromMeta.errors.map(_.asUInt.orR)) 210 211 def get_waymask(paddrs: Vec[UInt]): Vec[UInt] = { 212 val ptags = paddrs.map(get_phy_tag) 213 val tag_eq_vec = VecInit((0 until PortNumber).map( p => VecInit((0 until nWays).map( w => s1_meta_ptags(p)(w) === ptags(p))))) 214 val tag_match_vec = VecInit((0 until PortNumber).map( k => VecInit(tag_eq_vec(k).zipWithIndex.map{ case(way_tag_eq, w) => way_tag_eq && s1_meta_valids(k)(w)}))) 215 val waymasks = VecInit(tag_match_vec.map(_.asUInt)) 216 waymasks 217 } 218 219 val s1_SRAM_waymasks = VecInit((0 until PortNumber).map(i => 220 Mux(tlb_valid_pulse(i), get_waymask(s1_req_paddr_wire)(i), get_waymask(s1_req_paddr_reg)(i)))) 221 222 /** 223 ****************************************************************************** 224 * update waymask according to MSHR update data 225 ****************************************************************************** 226 */ 227 def update_waymask(mask: UInt, vSetIdx: UInt, ptag: UInt): UInt = { 228 require(mask.getWidth == nWays) 229 val new_mask = WireInit(mask) 230 val valid = fromMSHR.valid && !fromMSHR.bits.corrupt 231 val vset_same = fromMSHR.bits.vSetIdx === vSetIdx 232 val ptag_same = getPhyTagFromBlk(fromMSHR.bits.blkPaddr) === ptag 233 val way_same = fromMSHR.bits.waymask === mask 234 when(valid && vset_same) { 235 when(ptag_same) { 236 new_mask := fromMSHR.bits.waymask 237 }.elsewhen(way_same) { 238 new_mask := 0.U 239 } 240 } 241 new_mask 242 } 243 244 val s1_SRAM_valid = s0_fire_r || RegNext(s1_need_meta && toMeta.ready) 245 val s1_MSHR_valid = fromMSHR.valid && !fromMSHR.bits.corrupt 246 val s1_waymasks = WireInit(VecInit(Seq.fill(PortNumber)(0.U(nWays.W)))) 247 val s1_waymasks_r = RegEnable(s1_waymasks, 0.U.asTypeOf(s1_waymasks), s1_SRAM_valid || s1_MSHR_valid) 248 (0 until PortNumber).foreach{i => 249 val old_waymask = Mux(s1_SRAM_valid, s1_SRAM_waymasks(i), s1_waymasks_r(i)) 250 s1_waymasks(i) := update_waymask(old_waymask, s1_req_vSetIdx(i), s1_req_ptags(i)) 251 } 252 253 /** 254 ****************************************************************************** 255 * send enqueu req to WayLookup 256 ******** ********************************************************************** 257 */ 258 // Disallow enqueuing wayLookup when SRAM write occurs. 259 toWayLookup.valid := ((state === m_enqWay) || ((state === m_idle) && itlb_finish)) && !s1_flush && !fromMSHR.valid 260 toWayLookup.bits.vSetIdx := s1_req_vSetIdx 261 toWayLookup.bits.waymask := s1_waymasks 262 toWayLookup.bits.ptag := s1_req_ptags 263 toWayLookup.bits.gpaddr := s1_req_gpaddr 264 (0 until PortNumber).foreach { i => 265 val excpValid = (if (i == 0) true.B else s1_doubleline) // exception in first line is always valid, in second line is valid iff is doubleline request 266 // Send s1_itlb_exception to WayLookup (instead of s1_exception_out) for better timing. Will check pmp again in mainPipe 267 toWayLookup.bits.itlb_exception(i) := Mux(excpValid, s1_itlb_exception(i), ExceptionType.none) 268 toWayLookup.bits.meta_corrupt(i) := excpValid && s1_meta_corrupt(i) 269 } 270 271 val s1_waymasks_vec = s1_waymasks.map(_.asTypeOf(Vec(nWays, Bool()))) 272 when(toWayLookup.fire) { 273 assert(PopCount(s1_waymasks_vec(0)) <= 1.U && (PopCount(s1_waymasks_vec(1)) <= 1.U || !s1_doubleline), 274 "Multiple hit in main pipe, port0:is=%d,ptag=0x%x,vidx=0x%x,vaddr=0x%x port1:is=%d,ptag=0x%x,vidx=0x%x,vaddr=0x%x ", 275 PopCount(s1_waymasks_vec(0)) > 1.U, s1_req_ptags(0), get_idx(s1_req_vaddr(0)), s1_req_vaddr(0), 276 PopCount(s1_waymasks_vec(1)) > 1.U && s1_doubleline, s1_req_ptags(1), get_idx(s1_req_vaddr(1)), s1_req_vaddr(1)) 277 } 278 279 /** 280 ****************************************************************************** 281 * PMP check 282 ****************************************************************************** 283 */ 284 toPMP.zipWithIndex.foreach { case (p, i) => 285 // if itlb has exception, paddr can be invalid, therefore pmp check can be skipped 286 p.valid := s1_valid // && s1_itlb_exception === ExceptionType.none 287 p.bits.addr := s1_req_paddr(i) 288 p.bits.size := 3.U // TODO 289 p.bits.cmd := TlbCmd.exec 290 } 291 val s1_pmp_exception = VecInit(fromPMP.map(ExceptionType.fromPMPResp)) 292 val s1_mmio = VecInit(fromPMP.map(_.mmio)) 293 294 // also raise af when meta array corrupt is detected, to cancel prefetch 295 val s1_meta_exception = VecInit(s1_meta_corrupt.map(ExceptionType.fromECC(io.csr_parity_enable, _))) 296 297 // merge s1 itlb/pmp/meta exceptions, itlb has the highest priority, pmp next, meta lowest 298 val s1_exception_out = ExceptionType.merge( 299 s1_itlb_exception, 300 s1_pmp_exception, 301 s1_meta_exception 302 ) 303 304 /** 305 ****************************************************************************** 306 * state machine 307 ******** ********************************************************************** 308 */ 309 310 switch(state) { 311 is(m_idle) { 312 when(s1_valid && !itlb_finish) { 313 next_state := m_itlbResend 314 }.elsewhen(s1_valid && itlb_finish && !toWayLookup.fire) { 315 next_state := m_enqWay 316 }.elsewhen(s1_valid && itlb_finish && toWayLookup.fire && !s2_ready) { 317 next_state := m_enterS2 318 } 319 } 320 is(m_itlbResend) { 321 when(itlb_finish && !toMeta.ready) { 322 next_state := m_metaResend 323 }.elsewhen(itlb_finish && toMeta.ready) { 324 next_state := m_enqWay 325 } 326 } 327 is(m_metaResend) { 328 when(toMeta.ready) { 329 next_state := m_enqWay 330 } 331 } 332 is(m_enqWay) { 333 when(toWayLookup.fire && !s2_ready) { 334 next_state := m_enterS2 335 }.elsewhen(toWayLookup.fire && s2_ready) { 336 next_state := m_idle 337 } 338 } 339 is(m_enterS2) { 340 when(s2_ready) { 341 next_state := m_idle 342 } 343 } 344 } 345 346 when(s1_flush) { 347 next_state := m_idle 348 } 349 350 /** Stage 1 control */ 351 from_bpu_s1_flush := s1_valid && fromFtq.flushFromBpu.shouldFlushByStage3(s1_req_ftqIdx) 352 s1_flush := io.flush || from_bpu_s1_flush 353 354 s1_ready := next_state === m_idle 355 s1_fire := (next_state === m_idle) && s1_valid && !s1_flush // used to clear s1_valid & itlb_valid_latch 356 val s1_real_fire = s1_fire && io.csr_pf_enable // real "s1 fire" that s1 enters s2 357 358 /** 359 ****************************************************************************** 360 * IPrefetch Stage 2 361 * - 1. Monitor the requests from missUnit to write to SRAM. 362 * - 2. send req to missUnit 363 ****************************************************************************** 364 */ 365 val s2_valid = generatePipeControl(lastFire = s1_real_fire, thisFire = s2_fire, thisFlush = s2_flush, lastFlush = false.B) 366 367 val s2_req_vaddr = RegEnable(s1_req_vaddr, 0.U.asTypeOf(s1_req_vaddr), s1_real_fire) 368 val s2_doubleline = RegEnable(s1_doubleline, 0.U.asTypeOf(s1_doubleline), s1_real_fire) 369 val s2_req_paddr = RegEnable(s1_req_paddr, 0.U.asTypeOf(s1_req_paddr), s1_real_fire) 370 val s2_exception = RegEnable(s1_exception_out, 0.U.asTypeOf(s1_exception_out), s1_real_fire) // includes itlb/pmp/meta exception 371 val s2_mmio = RegEnable(s1_mmio, 0.U.asTypeOf(s1_mmio), s1_real_fire) 372 val s2_waymasks = RegEnable(s1_waymasks, 0.U.asTypeOf(s1_waymasks), s1_real_fire) 373 374 val s2_req_vSetIdx = s2_req_vaddr.map(get_idx) 375 val s2_req_ptags = s2_req_paddr.map(get_phy_tag) 376 377 /** 378 ****************************************************************************** 379 * Monitor the requests from missUnit to write to SRAM 380 ****************************************************************************** 381 */ 382 383 /* NOTE: If fromMSHR.bits.corrupt, we should set s2_MSHR_hits to false.B, and send prefetch requests again. 384 * This is the opposite of how mainPipe handles fromMSHR.bits.corrupt, 385 * in which we should set s2_MSHR_hits to true.B, and send error to ifu. 386 */ 387 val s2_MSHR_match = VecInit((0 until PortNumber).map(i => 388 (s2_req_vSetIdx(i) === fromMSHR.bits.vSetIdx) && 389 (s2_req_ptags(i) === getPhyTagFromBlk(fromMSHR.bits.blkPaddr)) && 390 s2_valid && fromMSHR.valid && !fromMSHR.bits.corrupt 391 )) 392 val s2_MSHR_hits = (0 until PortNumber).map(i => ValidHoldBypass(s2_MSHR_match(i), s2_fire || s2_flush)) 393 394 val s2_SRAM_hits = s2_waymasks.map(_.orR) 395 val s2_hits = VecInit((0 until PortNumber).map(i => s2_MSHR_hits(i) || s2_SRAM_hits(i))) 396 397 /* s2_exception includes itlb pf/gpf/af, pmp af and meta corruption (af), neither of which should be prefetched 398 * mmio should not be prefetched 399 * also, if previous has exception, latter port should also not be prefetched 400 */ 401 val s2_miss = VecInit((0 until PortNumber).map { i => 402 !s2_hits(i) && (if (i==0) true.B else s2_doubleline) && 403 s2_exception.take(i+1).map(_ === ExceptionType.none).reduce(_&&_) && 404 s2_mmio.take(i+1).map(!_).reduce(_&&_) 405 }) 406 407 /** 408 ****************************************************************************** 409 * send req to missUnit 410 ****************************************************************************** 411 */ 412 val toMSHRArbiter = Module(new Arbiter(new ICacheMissReq, PortNumber)) 413 414 // To avoid sending duplicate requests. 415 val has_send = RegInit(VecInit(Seq.fill(PortNumber)(false.B))) 416 (0 until PortNumber).foreach{ i => 417 when(s1_real_fire) { 418 has_send(i) := false.B 419 }.elsewhen(toMSHRArbiter.io.in(i).fire) { 420 has_send(i) := true.B 421 } 422 } 423 424 (0 until PortNumber).map{ i => 425 toMSHRArbiter.io.in(i).valid := s2_valid && s2_miss(i) && !has_send(i) 426 toMSHRArbiter.io.in(i).bits.blkPaddr := getBlkAddr(s2_req_paddr(i)) 427 toMSHRArbiter.io.in(i).bits.vSetIdx := s2_req_vSetIdx(i) 428 } 429 430 toMSHR <> toMSHRArbiter.io.out 431 432 s2_flush := io.flush 433 434 val s2_finish = (0 until PortNumber).map(i => has_send(i) || !s2_miss(i) || toMSHRArbiter.io.in(i).fire).reduce(_&&_) 435 s2_ready := s2_finish || !s2_valid 436 s2_fire := s2_valid && s2_finish && !s2_flush 437 438 /** PerfAccumulate */ 439 // the number of prefetch request received from ftq 440 XSPerfAccumulate("prefetch_req_receive", fromFtq.req.fire) 441 // the number of prefetch request sent to missUnit 442 XSPerfAccumulate("prefetch_req_send", toMSHR.fire) 443 XSPerfAccumulate("to_missUnit_stall", toMSHR.valid && !toMSHR.ready) 444 /** 445 * Count the number of requests that are filtered for various reasons. 446 * The number of prefetch discard in Performance Accumulator may be 447 * a littel larger the number of really discarded. Because there can 448 * be multiple reasons for a canceled request at the same time. 449 */ 450 // discard prefetch request by flush 451 // XSPerfAccumulate("fdip_prefetch_discard_by_tlb_except", p1_discard && p1_tlb_except) 452 // // discard prefetch request by hit icache SRAM 453 // XSPerfAccumulate("fdip_prefetch_discard_by_hit_cache", p2_discard && p1_meta_hit) 454 // // discard prefetch request by hit wirte SRAM 455 // XSPerfAccumulate("fdip_prefetch_discard_by_p1_monoitor", p1_discard && p1_monitor_hit) 456 // // discard prefetch request by pmp except or mmio 457 // XSPerfAccumulate("fdip_prefetch_discard_by_pmp", p2_discard && p2_pmp_except) 458 // // discard prefetch request by hit mainPipe info 459 // // XSPerfAccumulate("fdip_prefetch_discard_by_mainPipe", p2_discard && p2_mainPipe_hit) 460}