xref: /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala (revision 67ba96b4871c459c09df20e3052738174021a830) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.frontend.icache
18
19import chipsalliance.rocketchip.config.Parameters
20import chisel3._
21import chisel3.util._
22import freechips.rocketchip.tilelink.{ClientMetadata, TLPermissions}
23import xiangshan._
24import utils._
25import utility._
26
27class ICacheReadBundle(implicit p: Parameters) extends ICacheBundle
28{
29  val isDoubleLine  = Bool()
30  val vSetIdx       = Vec(2,UInt(log2Ceil(nSets).W))
31
32  def port_0_read_0 =  !vSetIdx(0)(0)
33  def port_0_read_1 =   vSetIdx(0)(0)
34  def port_1_read_0 =  !vSetIdx(1)(0) && isDoubleLine
35  def port_1_read_1 =   vSetIdx(1)(0) && isDoubleLine
36
37  def read_bank_0 = port_0_read_0 || port_1_read_0
38  def read_bank_1 =  port_0_read_1 || port_1_read_1
39}
40
41
42class ICacheMetaRespBundle(implicit p: Parameters) extends ICacheBundle
43{
44  val metaData   = Vec(2, Vec(nWays, new ICacheMetadata))
45  val errors     = Vec(2, Vec(nWays ,Bool() ))
46
47  def tags = VecInit(metaData.map(port => VecInit(port.map( way=> way.tag ))))
48  def cohs = VecInit(metaData.map(port => VecInit(port.map( way=> way.coh ))))
49}
50
51class ICacheMetaWriteBundle(implicit p: Parameters) extends ICacheBundle
52{
53  val virIdx  = UInt(idxBits.W)
54  val phyTag  = UInt(tagBits.W)
55  val coh     = new ClientMetadata
56  val waymask = UInt(nWays.W)
57  val bankIdx = Bool()
58
59  def generate(tag:UInt, coh: ClientMetadata, idx:UInt, waymask:UInt, bankIdx: Bool){
60    this.virIdx  := idx
61    this.phyTag  := tag
62    this.coh     := coh
63    this.waymask := waymask
64    this.bankIdx   := bankIdx
65  }
66
67}
68
69class ICacheDataWriteBundle(implicit p: Parameters) extends ICacheBundle
70{
71  val virIdx  = UInt(idxBits.W)
72  val data    = UInt(blockBits.W)
73  val waymask = UInt(nWays.W)
74  val bankIdx = Bool()
75  val paddr   = UInt(PAddrBits.W)
76
77  def generate(data:UInt, idx:UInt, waymask:UInt, bankIdx: Bool, paddr: UInt){
78    this.virIdx  := idx
79    this.data    := data
80    this.waymask := waymask
81    this.bankIdx := bankIdx
82    this.paddr   := paddr
83  }
84
85}
86
87class ICacheDataRespBundle(implicit p: Parameters) extends ICacheBundle
88{
89  val datas = Vec(2, Vec(nWays,  UInt(blockBits.W)))
90  val codes = Vec(2, Vec(nWays , UInt(dataCodeEntryBits.W)))
91}
92
93class ICacheMetaReadBundle(implicit p: Parameters) extends ICacheBundle
94{
95    val req     = Flipped(DecoupledIO(new ICacheReadBundle))
96    val resp = Output(new ICacheMetaRespBundle)
97}
98
99class ICacheCommonReadBundle(isMeta: Boolean)(implicit p: Parameters) extends ICacheBundle
100{
101    val req     = Flipped(DecoupledIO(new ICacheReadBundle))
102    val resp    = if(isMeta) Output(new ICacheMetaRespBundle) else Output(new ICacheDataRespBundle)
103}
104
105class ICacheProbeReq(implicit p: Parameters) extends ICacheBundle {
106  val miss = Bool()
107  val probe_param = UInt(TLPermissions.bdWidth.W)
108  val addr = UInt(PAddrBits.W)
109  val vaddr = UInt(VAddrBits.W)
110}
111
112class ICacheVictimInfor(implicit p: Parameters) extends ICacheBundle {
113  val valid = Bool()
114  val vidx  = UInt(idxBits.W)
115}