1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend.icache 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util.{DecoupledIO, _} 22import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp, TransferSizes} 23import freechips.rocketchip.tilelink._ 24import freechips.rocketchip.util.BundleFieldBase 25import huancun.{AliasField, DirtyField, PreferCacheField, PrefetchField} 26import xiangshan._ 27import xiangshan.frontend._ 28import xiangshan.cache._ 29import utils._ 30import utility._ 31import xiangshan.backend.fu.PMPReqBundle 32import xiangshan.cache.mmu.{TlbRequestIO, TlbReq} 33 34case class ICacheParameters( 35 nSets: Int = 256, 36 nWays: Int = 8, 37 rowBits: Int = 64, 38 nTLBEntries: Int = 32, 39 tagECC: Option[String] = None, 40 dataECC: Option[String] = None, 41 replacer: Option[String] = Some("random"), 42 nMissEntries: Int = 2, 43 nReleaseEntries: Int = 1, 44 nProbeEntries: Int = 2, 45 nPrefetchEntries: Int = 4, 46 hasPrefetch: Boolean = false, 47 nMMIOs: Int = 1, 48 blockBytes: Int = 64 49)extends L1CacheParameters { 50 51 val setBytes = nSets * blockBytes 52 val aliasBitsOpt = if(setBytes > pageSize) Some(log2Ceil(setBytes / pageSize)) else None 53 val reqFields: Seq[BundleFieldBase] = Seq( 54 PrefetchField(), 55 PreferCacheField() 56 ) ++ aliasBitsOpt.map(AliasField) 57 val echoFields: Seq[BundleFieldBase] = Seq(DirtyField()) 58 def tagCode: Code = Code.fromString(tagECC) 59 def dataCode: Code = Code.fromString(dataECC) 60 def replacement = ReplacementPolicy.fromString(replacer,nWays,nSets) 61} 62 63trait HasICacheParameters extends HasL1CacheParameters with HasInstrMMIOConst with HasIFUConst{ 64 val cacheParams = icacheParameters 65 val dataCodeUnit = 16 66 val dataCodeUnitNum = blockBits/dataCodeUnit 67 68 def highestIdxBit = log2Ceil(nSets) - 1 69 def encDataUnitBits = cacheParams.dataCode.width(dataCodeUnit) 70 def dataCodeBits = encDataUnitBits - dataCodeUnit 71 def dataCodeEntryBits = dataCodeBits * dataCodeUnitNum 72 73 val ICacheSets = cacheParams.nSets 74 val ICacheWays = cacheParams.nWays 75 76 val ICacheSameVPAddrLength = 12 77 val ReplaceIdWid = 5 78 79 val ICacheWordOffset = 0 80 val ICacheSetOffset = ICacheWordOffset + log2Up(blockBytes) 81 val ICacheAboveIndexOffset = ICacheSetOffset + log2Up(ICacheSets) 82 val ICacheTagOffset = ICacheAboveIndexOffset min ICacheSameVPAddrLength 83 84 def ReplacePipeKey = 0 85 def MainPipeKey = 1 86 def PortNumber = 2 87 def ProbeKey = 3 88 89 def partWayNum = 4 90 def pWay = nWays/partWayNum 91 92 def nPrefetchEntries = cacheParams.nPrefetchEntries 93 94 def getBits(num: Int) = log2Ceil(num).W 95 96 97 def generatePipeControl(lastFire: Bool, thisFire: Bool, thisFlush: Bool, lastFlush: Bool): Bool = { 98 val valid = RegInit(false.B) 99 when(thisFlush) {valid := false.B} 100 .elsewhen(lastFire && !lastFlush) {valid := true.B} 101 .elsewhen(thisFire) {valid := false.B} 102 valid 103 } 104 105 def ResultHoldBypass[T<:Data](data: T, valid: Bool): T = { 106 Mux(valid, data, RegEnable(data, valid)) 107 } 108 109 require(isPow2(nSets), s"nSets($nSets) must be pow2") 110 require(isPow2(nWays), s"nWays($nWays) must be pow2") 111} 112 113abstract class ICacheBundle(implicit p: Parameters) extends XSBundle 114 with HasICacheParameters 115 116abstract class ICacheModule(implicit p: Parameters) extends XSModule 117 with HasICacheParameters 118 119abstract class ICacheArray(implicit p: Parameters) extends XSModule 120 with HasICacheParameters 121 122class ICacheMetadata(implicit p: Parameters) extends ICacheBundle { 123 val coh = new ClientMetadata 124 val tag = UInt(tagBits.W) 125} 126 127object ICacheMetadata { 128 def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = { 129 val meta = Wire(new L1Metadata) 130 meta.tag := tag 131 meta.coh := coh 132 meta 133 } 134} 135 136 137class ICacheMetaArray()(implicit p: Parameters) extends ICacheArray 138{ 139 def onReset = ICacheMetadata(0.U, ClientMetadata.onReset) 140 val metaBits = onReset.getWidth 141 val metaEntryBits = cacheParams.tagCode.width(metaBits) 142 143 val io=IO{new Bundle{ 144 val write = Flipped(DecoupledIO(new ICacheMetaWriteBundle)) 145 val read = Flipped(DecoupledIO(new ICacheReadBundle)) 146 val readResp = Output(new ICacheMetaRespBundle) 147 val cacheOp = Flipped(new L1CacheInnerOpIO) // customized cache op port 148 }} 149 150 io.read.ready := !io.write.valid 151 152 val port_0_read_0 = io.read.valid && !io.read.bits.vSetIdx(0)(0) 153 val port_0_read_1 = io.read.valid && io.read.bits.vSetIdx(0)(0) 154 val port_1_read_1 = io.read.valid && io.read.bits.vSetIdx(1)(0) && io.read.bits.isDoubleLine 155 val port_1_read_0 = io.read.valid && !io.read.bits.vSetIdx(1)(0) && io.read.bits.isDoubleLine 156 157 val port_0_read_0_reg = RegEnable(next = port_0_read_0, enable = io.read.fire()) 158 val port_0_read_1_reg = RegEnable(next = port_0_read_1, enable = io.read.fire()) 159 val port_1_read_1_reg = RegEnable(next = port_1_read_1, enable = io.read.fire()) 160 val port_1_read_0_reg = RegEnable(next = port_1_read_0, enable = io.read.fire()) 161 162 val bank_0_idx = Mux(port_0_read_0, io.read.bits.vSetIdx(0), io.read.bits.vSetIdx(1)) 163 val bank_1_idx = Mux(port_0_read_1, io.read.bits.vSetIdx(0), io.read.bits.vSetIdx(1)) 164 val bank_idx = Seq(bank_0_idx, bank_1_idx) 165 166 val write_bank_0 = io.write.valid && !io.write.bits.bankIdx 167 val write_bank_1 = io.write.valid && io.write.bits.bankIdx 168 169 val write_meta_bits = Wire(UInt(metaEntryBits.W)) 170 171 val tagArrays = (0 until 2) map { bank => 172 val tagArray = Module(new SRAMTemplate( 173 UInt(metaEntryBits.W), 174 set=nSets/2, 175 way=nWays, 176 shouldReset = true, 177 holdRead = true, 178 singlePort = true 179 )) 180 181 //meta connection 182 if(bank == 0) { 183 tagArray.io.r.req.valid := port_0_read_0 || port_1_read_0 184 tagArray.io.r.req.bits.apply(setIdx=bank_0_idx(highestIdxBit,1)) 185 tagArray.io.w.req.valid := write_bank_0 186 tagArray.io.w.req.bits.apply(data=write_meta_bits, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 187 } 188 else { 189 tagArray.io.r.req.valid := port_0_read_1 || port_1_read_1 190 tagArray.io.r.req.bits.apply(setIdx=bank_1_idx(highestIdxBit,1)) 191 tagArray.io.w.req.valid := write_bank_1 192 tagArray.io.w.req.bits.apply(data=write_meta_bits, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 193 } 194 195 tagArray 196 } 197 198 io.read.ready := !io.write.valid && tagArrays.map(_.io.r.req.ready).reduce(_&&_) 199 200 //Parity Decode 201 val read_metas = Wire(Vec(2,Vec(nWays,new ICacheMetadata()))) 202 for((tagArray,i) <- tagArrays.zipWithIndex){ 203 val read_meta_bits = tagArray.io.r.resp.asTypeOf(Vec(nWays,UInt(metaEntryBits.W))) 204 val read_meta_decoded = read_meta_bits.map{ way_bits => cacheParams.tagCode.decode(way_bits)} 205 val read_meta_wrong = read_meta_decoded.map{ way_bits_decoded => way_bits_decoded.error} 206 val read_meta_corrected = VecInit(read_meta_decoded.map{ way_bits_decoded => way_bits_decoded.corrected}) 207 read_metas(i) := read_meta_corrected.asTypeOf(Vec(nWays,new ICacheMetadata())) 208 (0 until nWays).map{ w => io.readResp.errors(i)(w) := RegNext(read_meta_wrong(w)) && RegNext(RegNext(io.read.fire))} 209 } 210 211 //Parity Encode 212 val write = io.write.bits 213 write_meta_bits := cacheParams.tagCode.encode(ICacheMetadata(tag = write.phyTag, coh = write.coh).asUInt) 214 215 val wayNum = OHToUInt(io.write.bits.waymask) 216 val validPtr = Cat(io.write.bits.virIdx, wayNum) 217 218 io.readResp.metaData <> DontCare 219 when(port_0_read_0_reg){ 220 io.readResp.metaData(0) := read_metas(0) 221 }.elsewhen(port_0_read_1_reg){ 222 io.readResp.metaData(0) := read_metas(1) 223 } 224 225 when(port_1_read_0_reg){ 226 io.readResp.metaData(1) := read_metas(0) 227 }.elsewhen(port_1_read_1_reg){ 228 io.readResp.metaData(1) := read_metas(1) 229 } 230 231 232 io.write.ready := true.B 233 // deal with customized cache op 234 require(nWays <= 32) 235 io.cacheOp.resp.bits := DontCare 236 val cacheOpShouldResp = WireInit(false.B) 237 when(io.cacheOp.req.valid){ 238 when( 239 CacheInstrucion.isReadTag(io.cacheOp.req.bits.opCode) || 240 CacheInstrucion.isReadTagECC(io.cacheOp.req.bits.opCode) 241 ){ 242 for (i <- 0 until 2) { 243 tagArrays(i).io.r.req.valid := true.B 244 tagArrays(i).io.r.req.bits.apply(setIdx = io.cacheOp.req.bits.index) 245 } 246 cacheOpShouldResp := true.B 247 } 248 when(CacheInstrucion.isWriteTag(io.cacheOp.req.bits.opCode)){ 249 for (i <- 0 until 2) { 250 tagArrays(i).io.w.req.valid := true.B 251 tagArrays(i).io.w.req.bits.apply( 252 data = io.cacheOp.req.bits.write_tag_low, 253 setIdx = io.cacheOp.req.bits.index, 254 waymask = UIntToOH(io.cacheOp.req.bits.wayNum(4, 0)) 255 ) 256 } 257 cacheOpShouldResp := true.B 258 } 259 // TODO 260 // when(CacheInstrucion.isWriteTagECC(io.cacheOp.req.bits.opCode)){ 261 // for (i <- 0 until readPorts) { 262 // array(i).io.ecc_write.valid := true.B 263 // array(i).io.ecc_write.bits.idx := io.cacheOp.req.bits.index 264 // array(i).io.ecc_write.bits.way_en := UIntToOH(io.cacheOp.req.bits.wayNum(4, 0)) 265 // array(i).io.ecc_write.bits.ecc := io.cacheOp.req.bits.write_tag_ecc 266 // } 267 // cacheOpShouldResp := true.B 268 // } 269 } 270 io.cacheOp.resp.valid := RegNext(io.cacheOp.req.valid && cacheOpShouldResp) 271 io.cacheOp.resp.bits.read_tag_low := Mux(io.cacheOp.resp.valid, 272 tagArrays(0).io.r.resp.asTypeOf(Vec(nWays, UInt(tagBits.W)))(io.cacheOp.req.bits.wayNum), 273 0.U 274 ) 275 io.cacheOp.resp.bits.read_tag_ecc := DontCare // TODO 276 // TODO: deal with duplicated array 277} 278 279 280 281class ICacheDataArray(implicit p: Parameters) extends ICacheArray 282{ 283 284 def getECCFromEncUnit(encUnit: UInt) = { 285 require(encUnit.getWidth == encDataUnitBits) 286 if (encDataUnitBits == dataCodeUnit) { 287 0.U.asTypeOf(UInt(1.W)) 288 } else { 289 encUnit(encDataUnitBits - 1, dataCodeUnit) 290 } 291 } 292 293 def getECCFromBlock(cacheblock: UInt) = { 294 // require(cacheblock.getWidth == blockBits) 295 VecInit((0 until dataCodeUnitNum).map { w => 296 val unit = cacheblock(dataCodeUnit * (w + 1) - 1, dataCodeUnit * w) 297 getECCFromEncUnit(cacheParams.dataCode.encode(unit)) 298 }) 299 } 300 301 val io=IO{new Bundle{ 302 val write = Flipped(DecoupledIO(new ICacheDataWriteBundle)) 303 val read = Flipped(DecoupledIO(Vec(partWayNum, new ICacheReadBundle))) 304 val readResp = Output(new ICacheDataRespBundle) 305 val cacheOp = Flipped(new L1CacheInnerOpIO) // customized cache op port 306 }} 307 308 val write_data_bits = Wire(UInt(blockBits.W)) 309 310 val port_0_read_0_reg = RegEnable(next = io.read.valid && io.read.bits.head.port_0_read_0, enable = io.read.fire()) 311 val port_0_read_1_reg = RegEnable(next = io.read.valid && io.read.bits.head.port_0_read_1, enable = io.read.fire()) 312 val port_1_read_1_reg = RegEnable(next = io.read.valid && io.read.bits.head.port_1_read_1, enable = io.read.fire()) 313 val port_1_read_0_reg = RegEnable(next = io.read.valid && io.read.bits.head.port_1_read_0, enable = io.read.fire()) 314 315 val bank_0_idx_vec = io.read.bits.map(copy => Mux(io.read.valid && copy.port_0_read_0, copy.vSetIdx(0), copy.vSetIdx(1))) 316 val bank_1_idx_vec = io.read.bits.map(copy => Mux(io.read.valid && copy.port_0_read_1, copy.vSetIdx(0), copy.vSetIdx(1))) 317 318 val dataArrays = (0 until partWayNum).map{ i => 319 val dataArray = Module(new ICachePartWayArray( 320 UInt(blockBits.W), 321 pWay, 322 )) 323 324 dataArray.io.read.req(0).valid := io.read.bits(i).read_bank_0 && io.read.valid 325 dataArray.io.read.req(0).bits.ridx := bank_0_idx_vec(i)(highestIdxBit,1) 326 dataArray.io.read.req(1).valid := io.read.bits(i).read_bank_1 && io.read.valid 327 dataArray.io.read.req(1).bits.ridx := bank_1_idx_vec(i)(highestIdxBit,1) 328 329 330 dataArray.io.write.valid := io.write.valid 331 dataArray.io.write.bits.wdata := write_data_bits 332 dataArray.io.write.bits.widx := io.write.bits.virIdx(highestIdxBit,1) 333 dataArray.io.write.bits.wbankidx := io.write.bits.bankIdx 334 dataArray.io.write.bits.wmask := io.write.bits.waymask.asTypeOf(Vec(partWayNum, Vec(pWay, Bool())))(i) 335 336 dataArray 337 } 338 339 val read_datas = Wire(Vec(2,Vec(nWays,UInt(blockBits.W) ))) 340 341 (0 until PortNumber).map { port => 342 (0 until nWays).map { w => 343 read_datas(port)(w) := dataArrays(w / pWay).io.read.resp.rdata(port).asTypeOf(Vec(pWay, UInt(blockBits.W)))(w % pWay) 344 } 345 } 346 347 io.readResp.datas(0) := Mux( port_0_read_1_reg, read_datas(1) , read_datas(0)) 348 io.readResp.datas(1) := Mux( port_1_read_0_reg, read_datas(0) , read_datas(1)) 349 350 351 val write_data_code = Wire(UInt(dataCodeEntryBits.W)) 352 val write_bank_0 = WireInit(io.write.valid && !io.write.bits.bankIdx) 353 val write_bank_1 = WireInit(io.write.valid && io.write.bits.bankIdx) 354 355 val bank_0_idx = bank_0_idx_vec.last 356 val bank_1_idx = bank_1_idx_vec.last 357 358 val codeArrays = (0 until 2) map { i => 359 val codeArray = Module(new SRAMTemplate( 360 UInt(dataCodeEntryBits.W), 361 set=nSets/2, 362 way=nWays, 363 shouldReset = true, 364 holdRead = true, 365 singlePort = true 366 )) 367 368 if(i == 0) { 369 codeArray.io.r.req.valid := io.read.valid && io.read.bits.last.read_bank_0 370 codeArray.io.r.req.bits.apply(setIdx=bank_0_idx(highestIdxBit,1)) 371 codeArray.io.w.req.valid := write_bank_0 372 codeArray.io.w.req.bits.apply(data=write_data_code, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 373 } 374 else { 375 codeArray.io.r.req.valid := io.read.valid && io.read.bits.last.read_bank_1 376 codeArray.io.r.req.bits.apply(setIdx=bank_1_idx(highestIdxBit,1)) 377 codeArray.io.w.req.valid := write_bank_1 378 codeArray.io.w.req.bits.apply(data=write_data_code, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 379 } 380 381 codeArray 382 } 383 384 io.read.ready := !io.write.valid && 385 dataArrays.map(_.io.read.req.map(_.ready).reduce(_&&_)).reduce(_&&_) && 386 codeArrays.map(_.io.r.req.ready).reduce(_ && _) 387 388 //Parity Decode 389 val read_codes = Wire(Vec(2,Vec(nWays,UInt(dataCodeEntryBits.W) ))) 390 for(((dataArray,codeArray),i) <- dataArrays.zip(codeArrays).zipWithIndex){ 391 read_codes(i) := codeArray.io.r.resp.asTypeOf(Vec(nWays,UInt(dataCodeEntryBits.W))) 392 } 393 394 //Parity Encode 395 val write = io.write.bits 396 val write_data = WireInit(write.data) 397 write_data_code := getECCFromBlock(write_data).asUInt 398 write_data_bits := write_data 399 400 io.readResp.codes(0) := Mux( port_0_read_1_reg, read_codes(1) , read_codes(0)) 401 io.readResp.codes(1) := Mux( port_1_read_0_reg, read_codes(0) , read_codes(1)) 402 403 io.write.ready := true.B 404 405 // deal with customized cache op 406 require(nWays <= 32) 407 io.cacheOp.resp.bits := DontCare 408 io.cacheOp.resp.valid := false.B 409 val cacheOpShouldResp = WireInit(false.B) 410 val dataresp = Wire(Vec(nWays,UInt(blockBits.W) )) 411 dataresp := DontCare 412 when(io.cacheOp.req.valid){ 413 when( 414 CacheInstrucion.isReadData(io.cacheOp.req.bits.opCode) 415 ){ 416 for (i <- 0 until partWayNum) { 417 dataArrays(i).io.read.req.zipWithIndex.map{ case(port,i) => 418 if(i ==0) port.valid := !io.cacheOp.req.bits.bank_num(0) 419 else port.valid := io.cacheOp.req.bits.bank_num(0) 420 port.bits.ridx := io.cacheOp.req.bits.index(highestIdxBit,1) 421 } 422 } 423 cacheOpShouldResp := dataArrays.head.io.read.req.map(_.fire()).reduce(_||_) 424 dataresp :=Mux(io.cacheOp.req.bits.bank_num(0).asBool, read_datas(1), read_datas(0)) 425 } 426 when(CacheInstrucion.isWriteData(io.cacheOp.req.bits.opCode)){ 427 for (i <- 0 until partWayNum) { 428 dataArrays(i).io.write.valid := true.B 429 dataArrays(i).io.write.bits.wdata := io.cacheOp.req.bits.write_data_vec.asTypeOf(write_data.cloneType) 430 dataArrays(i).io.write.bits.wbankidx := io.cacheOp.req.bits.bank_num(0) 431 dataArrays(i).io.write.bits.widx := io.cacheOp.req.bits.index(highestIdxBit,1) 432 dataArrays(i).io.write.bits.wmask := UIntToOH(io.cacheOp.req.bits.wayNum(4, 0)).asTypeOf(Vec(partWayNum, Vec(pWay, Bool())))(i) 433 } 434 cacheOpShouldResp := true.B 435 } 436 } 437 438 io.cacheOp.resp.valid := RegNext(cacheOpShouldResp) 439 val numICacheLineWords = blockBits / 64 440 require(blockBits >= 64 && isPow2(blockBits)) 441 for (wordIndex <- 0 until numICacheLineWords) { 442 io.cacheOp.resp.bits.read_data_vec(wordIndex) := dataresp(io.cacheOp.req.bits.wayNum(4, 0))(64*(wordIndex+1)-1, 64*wordIndex) 443 } 444 445} 446 447 448class ICacheIO(implicit p: Parameters) extends ICacheBundle 449{ 450 val hartId = Input(UInt(8.W)) 451 val prefetch = Flipped(new FtqPrefechBundle) 452 val stop = Input(Bool()) 453 val fetch = new ICacheMainPipeBundle 454 val toIFU = Output(Bool()) 455 val pmp = Vec(PortNumber + 1, new ICachePMPBundle) 456 val itlb = Vec(PortNumber + 1, new TlbRequestIO) 457 val perfInfo = Output(new ICachePerfInfo) 458 val error = new L1CacheErrorInfo 459 /* Cache Instruction */ 460 val csr = new L1CacheToCsrIO 461 /* CSR control signal */ 462 val csr_pf_enable = Input(Bool()) 463 val csr_parity_enable = Input(Bool()) 464} 465 466class ICache()(implicit p: Parameters) extends LazyModule with HasICacheParameters { 467 468 val clientParameters = TLMasterPortParameters.v1( 469 Seq(TLMasterParameters.v1( 470 name = "icache", 471 sourceId = IdRange(0, cacheParams.nMissEntries + cacheParams.nReleaseEntries), 472 supportsProbe = TransferSizes(blockBytes), 473 supportsHint = TransferSizes(blockBytes) 474 )), 475 requestFields = cacheParams.reqFields, 476 echoFields = cacheParams.echoFields 477 ) 478 479 val clientNode = TLClientNode(Seq(clientParameters)) 480 481 lazy val module = new ICacheImp(this) 482} 483 484class ICacheImp(outer: ICache) extends LazyModuleImp(outer) with HasICacheParameters with HasPerfEvents { 485 val io = IO(new ICacheIO) 486 487 println("ICache:") 488 println(" ICacheSets: " + cacheParams.nSets) 489 println(" ICacheWays: " + cacheParams.nWays) 490 println(" ICacheBanks: " + PortNumber) 491 println(" hasPrefetch: " + cacheParams.hasPrefetch) 492 if(cacheParams.hasPrefetch){ 493 println(" nPrefetchEntries: " + cacheParams.nPrefetchEntries) 494 } 495 496 val (bus, edge) = outer.clientNode.out.head 497 498 val metaArray = Module(new ICacheMetaArray) 499 val dataArray = Module(new ICacheDataArray) 500 val mainPipe = Module(new ICacheMainPipe) 501 val missUnit = Module(new ICacheMissUnit(edge)) 502 val releaseUnit = Module(new ReleaseUnit(edge)) 503 val replacePipe = Module(new ICacheReplacePipe) 504 val probeQueue = Module(new ICacheProbeQueue(edge)) 505 val prefetchPipe = Module(new IPrefetchPipe) 506 507 val meta_read_arb = Module(new Arbiter(new ICacheReadBundle, 3)) 508 val data_read_arb = Module(new Arbiter(Vec(partWayNum, new ICacheReadBundle), 2)) 509 val meta_write_arb = Module(new Arbiter(new ICacheMetaWriteBundle(), 2 )) 510 val replace_req_arb = Module(new Arbiter(new ReplacePipeReq, 2)) 511 // val tlb_req_arb = Module(new Arbiter(new TlbReq, 2)) 512 513 meta_read_arb.io.in(ReplacePipeKey) <> replacePipe.io.meta_read 514 meta_read_arb.io.in(MainPipeKey) <> mainPipe.io.metaArray.toIMeta 515 meta_read_arb.io.in(2) <> prefetchPipe.io.toIMeta 516 metaArray.io.read <> meta_read_arb.io.out 517 518 replacePipe.io.meta_response <> metaArray.io.readResp 519 mainPipe.io.metaArray.fromIMeta <> metaArray.io.readResp 520 prefetchPipe.io.fromIMeta <> metaArray.io.readResp 521 522 data_read_arb.io.in(ReplacePipeKey) <> replacePipe.io.data_read 523 data_read_arb.io.in(MainPipeKey) <> mainPipe.io.dataArray.toIData 524 dataArray.io.read <> data_read_arb.io.out 525 replacePipe.io.data_response <> dataArray.io.readResp 526 mainPipe.io.dataArray.fromIData <> dataArray.io.readResp 527 528 mainPipe.io.respStall := io.stop 529 io.perfInfo := mainPipe.io.perfInfo 530 531 meta_write_arb.io.in(ReplacePipeKey) <> replacePipe.io.meta_write 532 meta_write_arb.io.in(MainPipeKey) <> missUnit.io.meta_write 533 534 //metaArray.io.write <> meta_write_arb.io.out 535 //dataArray.io.write <> missUnit.io.data_write 536 537 metaArray.io.write.valid := RegNext(meta_write_arb.io.out.valid,init =false.B) 538 metaArray.io.write.bits := RegNext(meta_write_arb.io.out.bits) 539 meta_write_arb.io.out.ready := true.B 540 541 dataArray.io.write.valid := RegNext(missUnit.io.data_write.valid,init =false.B) 542 dataArray.io.write.bits := RegNext(missUnit.io.data_write.bits) 543 missUnit.io.data_write.ready := true.B 544 545 mainPipe.io.csr_parity_enable := io.csr_parity_enable 546 replacePipe.io.csr_parity_enable := io.csr_parity_enable 547 548 if(cacheParams.hasPrefetch){ 549 prefetchPipe.io.fromFtq <> io.prefetch 550 when(!io.csr_pf_enable){ 551 prefetchPipe.io.fromFtq.req.valid := false.B 552 io.prefetch.req.ready := true.B 553 } 554 } else { 555 prefetchPipe.io.fromFtq <> DontCare 556 } 557 558 io.pmp(0) <> mainPipe.io.pmp(0) 559 io.pmp(1) <> mainPipe.io.pmp(1) 560 io.pmp(2) <> prefetchPipe.io.pmp 561 562 prefetchPipe.io.prefetchEnable := mainPipe.io.prefetchEnable 563 prefetchPipe.io.prefetchDisable := mainPipe.io.prefetchDisable 564 565 //notify IFU that Icache pipeline is available 566 io.toIFU := mainPipe.io.fetch.req.ready 567 568 // tlb_req_arb.io.in(0) <> mainPipe.io.itlb(0).req 569 // tlb_req_arb.io.in(1) <> prefetchPipe.io.iTLBInter.req 570 // io.itlb(0).req <> tlb_req_arb.io.out 571 572 // mainPipe.io.itlb(0).resp <> io.itlb(0).resp 573 // prefetchPipe.io.iTLBInter.resp <> io.itlb(0).resp 574 575 // when(mainPipe.io.itlb(0).req.fire() && prefetchPipe.io.iTLBInter.req.fire()) 576 // { 577 // assert(false.B, "Both mainPipe ITLB and prefetchPipe ITLB fire!") 578 // } 579 580 io.itlb(0) <> mainPipe.io.itlb(0) 581 io.itlb(1) <> mainPipe.io.itlb(1) 582 // io.itlb(2) <> mainPipe.io.itlb(2) 583 // io.itlb(3) <> mainPipe.io.itlb(3) 584 io.itlb(2) <> prefetchPipe.io.iTLBInter 585 586 587 io.fetch.resp <> mainPipe.io.fetch.resp 588 589 for(i <- 0 until PortNumber){ 590 missUnit.io.req(i) <> mainPipe.io.mshr(i).toMSHR 591 mainPipe.io.mshr(i).fromMSHR <> missUnit.io.resp(i) 592 } 593 594 missUnit.io.prefetch_req <> prefetchPipe.io.toMissUnit.enqReq 595 missUnit.io.hartId := io.hartId 596 prefetchPipe.io.fromMSHR <> missUnit.io.prefetch_check 597 598 bus.b.ready := false.B 599 bus.c.valid := false.B 600 bus.c.bits := DontCare 601 bus.e.valid := false.B 602 bus.e.bits := DontCare 603 604 bus.a <> missUnit.io.mem_acquire 605 bus.e <> missUnit.io.mem_finish 606 607 releaseUnit.io.req <> replacePipe.io.release_req 608 replacePipe.io.release_finish := releaseUnit.io.finish 609 bus.c <> releaseUnit.io.mem_release 610 611 // connect bus d 612 missUnit.io.mem_grant.valid := false.B 613 missUnit.io.mem_grant.bits := DontCare 614 615 releaseUnit.io.mem_grant.valid := false.B 616 releaseUnit.io.mem_grant.bits := DontCare 617 618 //Probe through bus b 619 probeQueue.io.mem_probe <> bus.b 620 621 //Parity error port 622 val errors = mainPipe.io.errors ++ Seq(replacePipe.io.error) 623 io.error <> RegNext(Mux1H(errors.map(e => e.valid -> e))) 624 625 626 /** Block set-conflict request */ 627 val probeReqValid = probeQueue.io.pipe_req.valid 628 val probeReqVidx = probeQueue.io.pipe_req.bits.vidx 629 630 val hasVictim = VecInit(missUnit.io.victimInfor.map(_.valid)) 631 val victimSetSeq = VecInit(missUnit.io.victimInfor.map(_.vidx)) 632 633 val probeShouldBlock = VecInit(hasVictim.zip(victimSetSeq).map{case(valid, idx) => valid && probeReqValid && idx === probeReqVidx }).reduce(_||_) 634 635 val releaseReqValid = missUnit.io.release_req.valid 636 val releaseReqVidx = missUnit.io.release_req.bits.vidx 637 638 val hasConflict = VecInit(Seq( 639 replacePipe.io.status.r0_set.valid, 640 replacePipe.io.status.r1_set.valid, 641 replacePipe.io.status.r2_set.valid, 642 replacePipe.io.status.r3_set.valid 643 )) 644 645 val conflictIdx = VecInit(Seq( 646 replacePipe.io.status.r0_set.bits, 647 replacePipe.io.status.r1_set.bits, 648 replacePipe.io.status.r2_set.bits, 649 replacePipe.io.status.r3_set.bits 650 )) 651 652 val releaseShouldBlock = VecInit(hasConflict.zip(conflictIdx).map{case(valid, idx) => valid && releaseReqValid && idx === releaseReqVidx }).reduce(_||_) 653 654 replace_req_arb.io.in(ReplacePipeKey) <> probeQueue.io.pipe_req 655 replace_req_arb.io.in(ReplacePipeKey).valid := probeQueue.io.pipe_req.valid && !probeShouldBlock 656 replace_req_arb.io.in(MainPipeKey) <> missUnit.io.release_req 657 replace_req_arb.io.in(MainPipeKey).valid := missUnit.io.release_req.valid && !releaseShouldBlock 658 replacePipe.io.pipe_req <> replace_req_arb.io.out 659 660 when(releaseShouldBlock){ 661 missUnit.io.release_req.ready := false.B 662 } 663 664 when(probeShouldBlock){ 665 probeQueue.io.pipe_req.ready := false.B 666 } 667 668 669 missUnit.io.release_resp <> replacePipe.io.pipe_resp 670 671 672 mainPipe.io.fetch.req <> io.fetch.req //&& !fetchShouldBlock(i) 673 // in L1ICache, we only expect GrantData and ReleaseAck 674 bus.d.ready := false.B 675 when ( bus.d.bits.opcode === TLMessages.GrantData) { 676 missUnit.io.mem_grant <> bus.d 677 } .elsewhen (bus.d.bits.opcode === TLMessages.ReleaseAck) { 678 releaseUnit.io.mem_grant <> bus.d 679 } .otherwise { 680 assert (!bus.d.fire()) 681 } 682 683 val perfEvents = Seq( 684 ("icache_miss_cnt ", false.B), 685 ("icache_miss_penty", BoolStopWatch(start = false.B, stop = false.B || false.B, startHighPriority = true)), 686 ) 687 generatePerfEvent() 688 689 // Customized csr cache op support 690 val cacheOpDecoder = Module(new CSRCacheOpDecoder("icache", CacheInstrucion.COP_ID_ICACHE)) 691 cacheOpDecoder.io.csr <> io.csr 692 dataArray.io.cacheOp.req := cacheOpDecoder.io.cache.req 693 metaArray.io.cacheOp.req := cacheOpDecoder.io.cache.req 694 cacheOpDecoder.io.cache.resp.valid := 695 dataArray.io.cacheOp.resp.valid || 696 metaArray.io.cacheOp.resp.valid 697 cacheOpDecoder.io.cache.resp.bits := Mux1H(List( 698 dataArray.io.cacheOp.resp.valid -> dataArray.io.cacheOp.resp.bits, 699 metaArray.io.cacheOp.resp.valid -> metaArray.io.cacheOp.resp.bits, 700 )) 701 cacheOpDecoder.io.error := io.error 702 assert(!((dataArray.io.cacheOp.resp.valid +& metaArray.io.cacheOp.resp.valid) > 1.U)) 703 704} 705 706class ICachePartWayReadBundle[T <: Data](gen: T, pWay: Int)(implicit p: Parameters) 707 extends ICacheBundle 708{ 709 val req = Flipped(Vec(PortNumber, Decoupled(new Bundle{ 710 val ridx = UInt((log2Ceil(nSets) - 1).W) 711 }))) 712 val resp = Output(new Bundle{ 713 val rdata = Vec(PortNumber,Vec(pWay, gen)) 714 }) 715} 716 717class ICacheWriteBundle[T <: Data](gen: T, pWay: Int)(implicit p: Parameters) 718 extends ICacheBundle 719{ 720 val wdata = gen 721 val widx = UInt((log2Ceil(nSets) - 1).W) 722 val wbankidx = Bool() 723 val wmask = Vec(pWay, Bool()) 724} 725 726class ICachePartWayArray[T <: Data](gen: T, pWay: Int)(implicit p: Parameters) extends ICacheArray 727{ 728 729 //including part way data 730 val io = IO{new Bundle { 731 val read = new ICachePartWayReadBundle(gen,pWay) 732 val write = Flipped(ValidIO(new ICacheWriteBundle(gen, pWay))) 733 }} 734 735 io.read.req.map(_.ready := !io.write.valid) 736 737 val srams = (0 until PortNumber) map { bank => 738 val sramBank = Module(new SRAMTemplate( 739 gen, 740 set=nSets/2, 741 way=pWay, 742 shouldReset = true, 743 holdRead = true, 744 singlePort = true 745 )) 746 747 sramBank.io.r.req.valid := io.read.req(bank).valid 748 sramBank.io.r.req.bits.apply(setIdx= io.read.req(bank).bits.ridx) 749 750 if(bank == 0) sramBank.io.w.req.valid := io.write.valid && !io.write.bits.wbankidx 751 else sramBank.io.w.req.valid := io.write.valid && io.write.bits.wbankidx 752 sramBank.io.w.req.bits.apply(data=io.write.bits.wdata, setIdx=io.write.bits.widx, waymask=io.write.bits.wmask.asUInt()) 753 754 sramBank 755 } 756 757 io.read.req.map(_.ready := !io.write.valid && srams.map(_.io.r.req.ready).reduce(_&&_)) 758 759 io.read.resp.rdata := VecInit(srams.map(bank => bank.io.r.resp.asTypeOf(Vec(pWay,gen)))) 760 761} 762