xref: /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala (revision 2199a01c65d5a7bf503c4b40771336a50a6f1122) 
1package xiangshan.frontend
2
3import chisel3._
4import chisel3.util._
5import utils._
6import freechips.rocketchip.rocket.{RVCDecoder, ExpandedInstruction}
7import xiangshan._
8import xiangshan.backend.decode.isa.predecode.PreDecodeInst
9import xiangshan.cache._
10
11trait HasPdconst{ this: XSModule =>
12  def isRVC(inst: UInt) = (inst(1,0) =/= 3.U)
13  def isLink(reg:UInt) = reg === 1.U || reg === 5.U
14  def brInfo(instr: UInt) = {
15    val brType::Nil = ListLookup(instr, List(BrType.notBr), PreDecodeInst.brTable)
16    val rd = Mux(isRVC(instr), instr(12), instr(11,7))
17    val rs = Mux(isRVC(instr), Mux(brType === BrType.jal, 0.U, instr(11, 7)), instr(19, 15))
18    val isCall = (brType === BrType.jal && !isRVC(instr) || brType === BrType.jalr) && isLink(rd) // Only for RV64
19    val isRet = brType === BrType.jalr && isLink(rs) && !isCall
20    List(brType, isCall, isRet)
21  }
22}
23
24object BrType {
25  def notBr   = "b00".U
26  def branch  = "b01".U
27  def jal     = "b10".U
28  def jalr    = "b11".U
29  def apply() = UInt(2.W)
30}
31
32object ExcType {  //TODO:add exctype
33  def notExc = "b000".U
34  def apply() = UInt(3.W)
35}
36
37class PreDecodeInfo extends XSBundle {  // 8 bit
38  val isRVC   = Bool()
39  val brType  = UInt(2.W)
40  val isCall  = Bool()
41  val isRet   = Bool()
42  val excType = UInt(3.W)
43  def isBr = brType === BrType.branch
44  def isJal = brType === BrType.jal
45  def isJalr = brType === BrType.jalr
46  def notCFI = brType === BrType.notBr
47}
48
49class PreDecodeResp extends XSBundle with HasIFUConst {
50  val instrs = Vec(PredictWidth, UInt(32.W))
51  val pc = Vec(PredictWidth, UInt(VAddrBits.W))
52  val mask = UInt(PredictWidth.W)
53  // one for the first bank
54  val lastHalf = Bool()
55  val pd = Vec(PredictWidth, (new PreDecodeInfo))
56}
57
58class PreDecode extends XSModule with HasPdconst with HasIFUConst {
59  val io = IO(new Bundle() {
60    val in = Input(new ICacheResp)
61    val prev = Flipped(ValidIO(UInt(16.W)))
62    val prev_pc = Input(UInt(VAddrBits.W))
63    val out = Output(new PreDecodeResp)
64  })
65
66  val data = io.in.data
67  val mask = io.in.mask
68
69  val packetAlignedPC = packetAligned(io.in.pc)
70  val packetOffset = offsetInPacket(io.in.pc)
71
72  val firstValidIdx = packetOffset // io.prev.valid should only occur with firstValidIdx = 0
73  XSError(firstValidIdx =/= 0.U && io.prev.valid && HasCExtension.B, p"pc:${io.in.pc}, mask:${io.in.mask}, prevhalfInst valid occurs on unaligned fetch packet\n")
74
75  val instsMask = Wire(Vec(PredictWidth, Bool()))
76  val instsEndMask = Wire(Vec(PredictWidth, Bool()))
77
78  val rawInsts = if (HasCExtension) {
79                   VecInit((0 until PredictWidth).map(i => if (i == PredictWidth-1) Cat(0.U(16.W), data(i*16+15, i*16))
80                                                         else data(i*16+31, i*16)))
81                 } else {
82                   VecInit((0 until PredictWidth).map(i => data(i*32+31, i*32)))
83                 }
84
85  for (i <- 0 until PredictWidth) {
86    val inst = WireInit(rawInsts(i))
87    val validStart = Wire(Bool()) // is the beginning of a valid inst
88    val validEnd = Wire(Bool())  // is the end of a valid inst
89
90    val isFirstInPacket = i.U === firstValidIdx
91    val isLastInPacket = (i == PredictWidth-1).B
92    val currentRVC = isRVC(inst) && HasCExtension.B
93
94    val lastIsValidEnd = (if (i == 0) { !io.prev.valid } else { instsEndMask(i-1) || isFirstInPacket }) || !HasCExtension.B
95
96    inst := (if (HasCExtension)
97               Mux(io.prev.valid && i.U === 0.U,
98                 Cat(rawInsts(i)(15,0), io.prev.bits),
99                 rawInsts(i))
100             else
101               rawInsts(i))
102
103    // when disable rvc, every 4 bytes should be an inst
104    validStart := lastIsValidEnd && !(isLastInPacket && !currentRVC) || !HasCExtension.B
105    validEnd := validStart && currentRVC || !validStart && !(isLastInPacket && !currentRVC) || !HasCExtension.B
106
107    val currentLastHalf = lastIsValidEnd && (isLastInPacket && !currentRVC) && HasCExtension.B
108
109    instsMask(i) := (if (i == 0) Mux(io.prev.valid, validEnd, validStart) else validStart)
110    instsEndMask(i) := validEnd
111
112    val brType::isCall::isRet::Nil = brInfo(inst)
113    io.out.pd(i).isRVC := currentRVC
114    io.out.pd(i).brType := brType
115    io.out.pd(i).isCall := isCall
116    io.out.pd(i).isRet := isRet
117    io.out.pd(i).excType := ExcType.notExc
118    io.out.instrs(i) := inst
119    io.out.pc(i) := Mux(io.prev.valid && HasCExtension.B && (i==0).B, io.prev_pc, Cat(packetIdx(io.in.pc), (i << instOffsetBits).U(log2Ceil(packetBytes).W)))
120
121    if (i == PredictWidth-1) { io.out.lastHalf := currentLastHalf }
122  }
123  io.out.mask := instsMask.asUInt & mask
124
125  for (i <- 0 until PredictWidth) {
126    XSDebug(true.B,
127      p"instr ${Hexadecimal(io.out.instrs(i))}, " +
128      p"mask ${Binary(instsMask(i))}, " +
129      p"endMask ${Binary(instsEndMask(i))}, " +
130      p"pc ${Hexadecimal(io.out.pc(i))}, " +
131      p"isRVC ${Binary(io.out.pd(i).isRVC)}, " +
132      p"brType ${Binary(io.out.pd(i).brType)}, " +
133      p"isRet ${Binary(io.out.pd(i).isRet)}, " +
134      p"isCall ${Binary(io.out.pd(i).isCall)}\n"
135    )
136  }
137}
138
139class RVCExpander extends XSModule {
140  val io = IO(new Bundle {
141    val in = Input(UInt(32.W))
142    val out = Output(new ExpandedInstruction)
143  })
144
145  if (HasCExtension) {
146    io.out := new RVCDecoder(io.in, XLEN).decode
147  } else {
148    io.out := new RVCDecoder(io.in, XLEN).passthrough
149  }
150}
151