1package xiangshan.frontend 2import utils.XSInfo 3import chisel3._ 4import chisel3.util._ 5import utils.PipelineConnect 6import xiangshan._ 7import xiangshan.cache._ 8 9 10class Frontend extends XSModule { 11 val io = IO(new Bundle() { 12 val icacheReq = DecoupledIO(new ICacheReq) 13 val icacheResp = Flipped(DecoupledIO(new ICacheResp)) 14 val icacheFlush = Output(UInt(2.W)) 15 val icacheToTlb = Flipped(new BlockTlbRequestIO) 16 val ptw = new TlbPtwIO 17 val backend = new FrontendToBackendIO 18 }) 19 20 val ifu = Module(new IFU) 21 val ibuffer = Module(new Ibuffer) 22 23 val needFlush = io.backend.redirect.valid 24 25 //backend 26 ifu.io.redirect <> io.backend.redirect 27 ifu.io.inOrderBrInfo <> io.backend.inOrderBrInfo 28 ifu.io.outOfOrderBrInfo <> io.backend.outOfOrderBrInfo 29 //icache 30 io.icacheReq <> ifu.io.icacheReq 31 io.icacheFlush <> ifu.io.icacheFlush 32 ifu.io.icacheResp <> io.icacheResp 33 //itlb to ptw 34 io.ptw <> TLB( 35 in = Seq(io.icacheToTlb), 36 sfence = io.backend.sfence, 37 csr = io.backend.tlbCsrIO, 38 width = 1, 39 isDtlb = false, 40 shouldBlock = true 41 ) 42 //ibuffer 43 ibuffer.io.in <> ifu.io.fetchPacket 44 ibuffer.io.flush := needFlush 45 46 io.backend.cfVec <> ibuffer.io.out 47 48 // for(out <- ibuffer.io.out){ 49 // XSInfo(out.fire(), 50 // p"inst:${Hexadecimal(out.bits.instr)} pc:${Hexadecimal(out.bits.pc)}\n" 51 // ) 52 // } 53 54 55}