1package xiangshan.frontend 2import utils.XSInfo 3import chisel3._ 4import chisel3.util._ 5import chipsalliance.rocketchip.config.Parameters 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utils.PipelineConnect 8import xiangshan._ 9import xiangshan.cache._ 10import xiangshan.cache.prefetch.L1plusPrefetcher 11import xiangshan.backend.fu.HasExceptionNO 12 13class Frontend()(implicit p: Parameters) extends LazyModule with HasXSParameter{ 14 15 val instrUncache = LazyModule(new InstrUncache()) 16 17 lazy val module = new FrontendImp(this) 18} 19 20 21class FrontendImp (outer: Frontend) extends LazyModuleImp(outer) 22 with HasL1plusCacheParameters 23 with HasXSParameter 24 with HasExceptionNO 25 with HasXSLog 26{ 27 val io = IO(new Bundle() { 28 val icacheMemAcq = DecoupledIO(new L1plusCacheReq) 29 val icacheMemGrant = Flipped(DecoupledIO(new L1plusCacheResp)) 30 val l1plusFlush = Output(Bool()) 31 val fencei = Input(Bool()) 32 val ptw = new TlbPtwIO 33 val backend = new FrontendToBackendIO 34 val sfence = Input(new SfenceBundle) 35 val tlbCsr = Input(new TlbCsrBundle) 36 }) 37 38 val ifu = Module(new IFU) 39 val ibuffer = Module(new Ibuffer) 40 val l1plusPrefetcher = Module(new L1plusPrefetcher) 41 val instrUncache = outer.instrUncache.module 42 43 val needFlush = io.backend.redirect.valid 44 45 // from backend 46 ifu.io.redirect <> io.backend.redirect 47 ifu.io.cfiUpdateInfo <> io.backend.cfiUpdateInfo 48 // to icache 49 val grantClientId = clientId(io.icacheMemGrant.bits.id) 50 val grantEntryId = entryId(io.icacheMemGrant.bits.id) 51 ifu.io.icacheMemGrant.valid := io.icacheMemGrant.valid && grantClientId === icacheMissQueueId.U 52 ifu.io.icacheMemGrant.bits := io.icacheMemGrant.bits 53 ifu.io.icacheMemGrant.bits.id := Cat(0.U(clientIdWidth.W), grantEntryId) 54 l1plusPrefetcher.io.mem_grant.valid := io.icacheMemGrant.valid && grantClientId === l1plusPrefetcherId.U 55 l1plusPrefetcher.io.mem_grant.bits := io.icacheMemGrant.bits 56 l1plusPrefetcher.io.mem_grant.bits.id := Cat(0.U(clientIdWidth.W), grantEntryId) 57 io.icacheMemGrant.ready := Mux(grantClientId === icacheMissQueueId.U, 58 ifu.io.icacheMemGrant.ready, 59 l1plusPrefetcher.io.mem_grant.ready) 60 ifu.io.fencei := io.fencei 61 62 63 instrUncache.io.req <> ifu.io.mmio_acquire 64 instrUncache.io.resp <> ifu.io.mmio_grant 65 instrUncache.io.flush <> ifu.io.mmio_flush 66 // to tlb 67 ifu.io.sfence := io.sfence 68 ifu.io.tlbCsr := io.tlbCsr 69 // from icache and l1plus prefetcher 70 io.l1plusFlush := ifu.io.l1plusFlush 71 l1plusPrefetcher.io.in.valid := ifu.io.prefetchTrainReq.valid 72 l1plusPrefetcher.io.in.bits := ifu.io.prefetchTrainReq.bits 73 val memAcquireArb = Module(new Arbiter(new L1plusCacheReq, nClients)) 74 memAcquireArb.io.in(icacheMissQueueId) <> ifu.io.icacheMemAcq 75 memAcquireArb.io.in(icacheMissQueueId).bits.id := Cat(icacheMissQueueId.U(clientIdWidth.W), 76 entryId(ifu.io.icacheMemAcq.bits.id)) 77 memAcquireArb.io.in(l1plusPrefetcherId) <> l1plusPrefetcher.io.mem_acquire 78 memAcquireArb.io.in(l1plusPrefetcherId).bits.id := Cat(l1plusPrefetcherId.U(clientIdWidth.W), 79 entryId(l1plusPrefetcher.io.mem_acquire.bits.id)) 80 io.icacheMemAcq <> memAcquireArb.io.out 81 // itlb to ptw 82 io.ptw <> ifu.io.ptw 83 // ifu to ibuffer 84 ibuffer.io.in <> ifu.io.fetchPacket 85 // backend to ibuffer 86 ibuffer.io.flush := needFlush 87 // ibuffer to backend 88 io.backend.cfVec <> ibuffer.io.out 89 90 // for(out <- ibuffer.io.out){ 91 // XSInfo(out.fire(), 92 // p"inst:${Hexadecimal(out.bits.instr)} pc:${Hexadecimal(out.bits.pc)}\n" 93 // ) 94 // } 95 96 97}