1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16package xiangshan.frontend 17 18import chipsalliance.rocketchip.config.Parameters 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import chisel3.experimental.chiselName 24 25trait BimParams extends HasXSParameter { 26 val BimBanks = PredictWidth 27 val BimSize = 4096 28 val nRows = BimSize / BimBanks 29 val bypassEntries = 4 30} 31 32@chiselName 33class BIM(implicit p: Parameters) extends BasePredictor with BimParams { 34 class BIMResp extends Resp { 35 val ctrs = Vec(PredictWidth, UInt(2.W)) 36 } 37 class BIMMeta extends Meta { 38 val ctrs = Vec(PredictWidth, UInt(2.W)) 39 } 40 class BIMFromOthers extends FromOthers {} 41 42 class BIMIO(implicit p: Parameters) extends DefaultBasePredictorIO { 43 val resp = Output(new BIMResp) 44 val meta = Output(new BIMMeta) 45 } 46 47 override val io = IO(new BIMIO) 48 override val debug = true 49 50 val bimAddr = new TableAddr(log2Up(BimSize), BimBanks) 51 52 val bim = Module(new SRAMTemplate(UInt(2.W), set = nRows, way=BimBanks, shouldReset = false, holdRead = true)) 53 54 val doing_reset = RegInit(true.B) 55 val resetRow = RegInit(0.U(log2Ceil(nRows).W)) 56 resetRow := resetRow + doing_reset 57 when (resetRow === (nRows-1).U) { doing_reset := false.B } 58 59 val if1_packetAlignedPC = packetAligned(io.pc.bits) 60 val if2_pc = RegEnable(if1_packetAlignedPC, io.pc.valid) 61 62 val if1_mask = io.inMask 63 val if1_row = bimAddr.getBankIdx(if1_packetAlignedPC) 64 65 bim.io.r.req.valid := io.pc.valid 66 bim.io.r.req.bits.setIdx := if1_row 67 68 val if2_bimRead = bim.io.r.resp.data 69 val ctrlMask = Fill(if2_bimRead.getWidth, ctrl.bim_enable.asUInt).asTypeOf(if2_bimRead) 70 io.resp.ctrs := VecInit(if2_bimRead zip ctrlMask map {case (a, b) => a & b}) 71 io.meta.ctrs := if2_bimRead 72 73 val updateValid = RegNext(io.update.valid) 74 val u = RegNext(io.update.bits) 75 76 val updateRow = bimAddr.getBankIdx(u.ftqPC) 77 78 79 val wrbypass_ctrs = RegInit(0.U.asTypeOf(Vec(bypassEntries, Vec(BimBanks, UInt(2.W))))) 80 val wrbypass_ctr_valids = RegInit(0.U.asTypeOf(Vec(bypassEntries, Vec(BimBanks, Bool())))) 81 val wrbypass_rows = RegInit(0.U.asTypeOf(Vec(bypassEntries, UInt(log2Up(nRows).W)))) 82 val wrbypass_enq_idx = RegInit(0.U(log2Up(bypassEntries).W)) 83 84 val wrbypass_hits = VecInit((0 until bypassEntries).map( i => 85 !doing_reset && wrbypass_rows(i) === updateRow)) 86 val wrbypass_hit = wrbypass_hits.reduce(_||_) 87 val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits) 88 89 val oldCtrs = VecInit((0 until BimBanks).map(b => 90 Mux(wrbypass_hit && wrbypass_ctr_valids(wrbypass_hit_idx)(b), 91 wrbypass_ctrs(wrbypass_hit_idx)(b), u.metas(b).bimCtr))) 92 93 val newTakens = VecInit((0 until BimBanks).map(b => u.cfiIndex.valid && u.cfiIndex.bits === b.U)) 94 val newCtrs = VecInit((0 until BimBanks).map(b => satUpdate(oldCtrs(b), 2, newTakens(b)))) 95 // val oldSaturated = newCtr === oldCtr 96 97 val needToUpdate = VecInit((0 until PredictWidth).map(i => updateValid && u.br_mask(i) && u.valids(i))) 98 99 when (reset.asBool) { wrbypass_ctr_valids.foreach(_.foreach(_ := false.B))} 100 101 for (b <- 0 until BimBanks) { 102 when (needToUpdate.reduce(_||_)) { 103 when (wrbypass_hit) { 104 when (needToUpdate(b)) { 105 wrbypass_ctrs(wrbypass_hit_idx)(b) := newCtrs(b) 106 wrbypass_ctr_valids(wrbypass_hit_idx)(b) := true.B 107 } 108 }.otherwise { 109 wrbypass_ctr_valids(wrbypass_enq_idx)(b) := false.B 110 when (needToUpdate(b)) { 111 wrbypass_ctr_valids(wrbypass_enq_idx)(b) := true.B 112 wrbypass_ctrs(wrbypass_enq_idx)(b) := newCtrs(b) 113 } 114 } 115 } 116 } 117 118 when (needToUpdate.reduce(_||_) && !wrbypass_hit) { 119 wrbypass_rows(wrbypass_enq_idx) := updateRow 120 wrbypass_enq_idx := (wrbypass_enq_idx + 1.U)(log2Up(bypassEntries)-1,0) 121 } 122 123 bim.io.w.apply( 124 valid = needToUpdate.asUInt.orR || doing_reset, 125 data = Mux(doing_reset, VecInit(Seq.fill(BimBanks)(2.U(2.W))), newCtrs), 126 setIdx = Mux(doing_reset, resetRow, updateRow), 127 waymask = Mux(doing_reset, Fill(BimBanks, "b1".U).asUInt, needToUpdate.asUInt) 128 ) 129 130 XSPerfAccumulate("bim_wrbypass_hit", needToUpdate.reduce(_||_) && wrbypass_hit) 131 XSPerfAccumulate("bim_wrbypass_enq", needToUpdate.reduce(_||_) && !wrbypass_hit) 132 133 if (BPUDebug && debug) { 134 val u = io.update.bits 135 XSDebug(doing_reset, "Reseting...\n") 136 XSDebug("[update] v=%d pc=%x valids=%b, tgt=%x\n", updateValid, u.ftqPC, u.valids.asUInt, u.target) 137 138 XSDebug("[update] brMask=%b, taken=%b isMisPred=%b\n", u.br_mask.asUInt, newTakens.asUInt, u.mispred.asUInt) 139 for (i <- 0 until BimBanks) { 140 XSDebug(RegNext(io.pc.valid && io.inMask(i)), p"BimResp[$i]: ctr = ${io.resp.ctrs(i)}\n") 141 XSDebug(needToUpdate(i), 142 p"update bim bank $i: pc:${Hexadecimal(u.ftqPC)}, taken:${u.takens(i)}, " + 143 p"oldCtr:${oldCtrs(i)}, newCtr:${newCtrs(i)}\n") 144 XSDebug(wrbypass_hit && wrbypass_ctr_valids(wrbypass_hit_idx)(i) && needToUpdate(i), 145 p"bank $i wrbypass hit wridx $wrbypass_hit_idx: row:$updateRow, " + 146 p"ctr:${oldCtrs(i)}, newCtr:${newCtrs(i)}\n") 147 XSDebug(true.B, p"bimCtr(${i.U})=${Binary(u.metas(i).bimCtr)} oldCtr=${Binary(oldCtrs(i))} newCtr=${Binary(newCtrs(i))}\n") 148 } 149 } 150 151} 152