xref: /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala (revision b086c6da80b5e7e939f9ce8dde0b13f881c26a65) 
1package xiangshan.frontend
2
3import chisel3._
4import chisel3.util._
5import xiangshan._
6import utils._
7import chisel3.experimental.chiselName
8
9trait BimParams extends HasXSParameter {
10  val BimBanks = PredictWidth
11  val BimSize = 4096
12  val nRows = BimSize / BimBanks
13  val bypassEntries = 4
14}
15
16@chiselName
17class BIM extends BasePredictor with BimParams {
18  class BIMResp extends Resp {
19    val ctrs = Vec(PredictWidth, UInt(2.W))
20  }
21  class BIMMeta extends Meta {
22    val ctrs = Vec(PredictWidth, UInt(2.W))
23  }
24  class BIMFromOthers extends FromOthers {}
25
26  class BIMIO extends DefaultBasePredictorIO {
27    val resp = Output(new BIMResp)
28    val meta = Output(new BIMMeta)
29  }
30
31  override val io = IO(new BIMIO)
32  override val debug = true
33
34  val bimAddr = new TableAddr(log2Up(BimSize), BimBanks)
35
36  val if1_bankAlignedPC = bankAligned(io.pc.bits)
37  val if2_pc = RegEnable(if1_bankAlignedPC, io.pc.valid)
38
39  val bim = List.fill(BimBanks) {
40    Module(new SRAMTemplate(UInt(2.W), set = nRows, shouldReset = false, holdRead = true))
41  }
42
43  val doing_reset = RegInit(true.B)
44  val resetRow = RegInit(0.U(log2Ceil(nRows).W))
45  resetRow := resetRow + doing_reset
46  when (resetRow === (nRows-1).U) { doing_reset := false.B }
47
48  // this bank means cache bank
49  val if1_startsAtOddBank = bankInGroup(if1_bankAlignedPC)(0)
50
51  val if1_realMask = Mux(if1_startsAtOddBank,
52                      Cat(io.inMask(bankWidth-1,0), io.inMask(PredictWidth-1, bankWidth)),
53                      io.inMask)
54
55
56  val if1_isInNextRow = VecInit((0 until BimBanks).map(i => Mux(if1_startsAtOddBank, (i < bankWidth).B, false.B)))
57
58  val if1_baseRow = bimAddr.getBankIdx(if1_bankAlignedPC)
59
60  val if1_realRow = VecInit((0 until BimBanks).map(b => Mux(if1_isInNextRow(b), (if1_baseRow+1.U)(log2Up(nRows)-1, 0), if1_baseRow)))
61
62  val if2_realRow = VecInit(if1_realRow.map(RegEnable(_, enable=io.pc.valid)))
63
64  for (b <- 0 until BimBanks) {
65    bim(b).io.r.req.valid       := if1_realMask(b) && io.pc.valid
66    bim(b).io.r.req.bits.setIdx := if1_realRow(b)
67  }
68
69  val if2_bimRead = VecInit(bim.map(_.io.r.resp.data(0)))
70
71  val if2_startsAtOddBank = bankInGroup(if2_pc)(0)
72
73  for (b <- 0 until BimBanks) {
74    val realBank = (if (b < bankWidth) Mux(if2_startsAtOddBank, (b+bankWidth).U, b.U)
75                    else Mux(if2_startsAtOddBank, (b-bankWidth).U, b.U))
76    val ctr = if2_bimRead(realBank)
77    io.resp.ctrs(b)  := ctr
78    io.meta.ctrs(b)  := ctr
79  }
80
81  val u = io.update.bits
82
83  val updateBank = bimAddr.getBank(u.pc)
84  val updateRow = bimAddr.getBankIdx(u.pc)
85
86
87  val wrbypass_ctrs       = Reg(Vec(bypassEntries, Vec(BimBanks, UInt(2.W))))
88  val wrbypass_ctr_valids = Reg(Vec(bypassEntries, Vec(BimBanks, Bool())))
89  val wrbypass_rows     = Reg(Vec(bypassEntries, UInt(log2Up(nRows).W)))
90  val wrbypass_enq_idx  = RegInit(0.U(log2Up(bypassEntries).W))
91
92  val wrbypass_hits = VecInit((0 until bypassEntries).map( i =>
93    !doing_reset && wrbypass_rows(i) === updateRow))
94  val wrbypass_hit = wrbypass_hits.reduce(_||_)
95  val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
96
97  val oldCtr = Mux(wrbypass_hit && wrbypass_ctr_valids(wrbypass_hit_idx)(updateBank), wrbypass_ctrs(wrbypass_hit_idx)(updateBank), u.bpuMeta.bimCtr)
98  val newTaken = u.taken
99  val newCtr = satUpdate(oldCtr, 2, newTaken)
100  // val oldSaturated = newCtr === oldCtr
101
102  val needToUpdate = io.update.valid && u.pd.isBr && !u.isReplay
103
104  when (reset.asBool) { wrbypass_ctr_valids.foreach(_.foreach(_ := false.B))}
105
106  when (needToUpdate) {
107    when (wrbypass_hit) {
108      wrbypass_ctrs(wrbypass_hit_idx)(updateBank) := newCtr
109      wrbypass_ctr_valids(wrbypass_hit_idx)(updateBank) := true.B
110    } .otherwise {
111      wrbypass_ctrs(wrbypass_enq_idx)(updateBank) := newCtr
112      (0 until BimBanks).foreach(b => wrbypass_ctr_valids(wrbypass_enq_idx)(b) := false.B) // reset valid bits
113      wrbypass_ctr_valids(wrbypass_enq_idx)(updateBank) := true.B
114      wrbypass_rows(wrbypass_enq_idx) := updateRow
115      wrbypass_enq_idx := (wrbypass_enq_idx + 1.U)(log2Up(bypassEntries)-1,0)
116    }
117  }
118
119  for (b <- 0 until BimBanks) {
120    bim(b).io.w.req.valid := needToUpdate && b.U === updateBank || doing_reset
121    bim(b).io.w.req.bits.setIdx := Mux(doing_reset, resetRow, updateRow)
122    bim(b).io.w.req.bits.data := Mux(doing_reset, 2.U(2.W), newCtr)
123  }
124
125  if (BPUDebug && debug) {
126    XSDebug(doing_reset, "Reseting...\n")
127    XSDebug("[update] v=%d pc=%x pnpc=%x tgt=%x", io.update.valid, u.pc, u.pnpc, u.target)
128    XSDebug("[update] taken=%d isMisPred=%d", u.taken, u.isMisPred)
129    XSDebug(false, true.B, p"brTag=${u.brTag} pd.isBr=${u.pd.isBr} brInfo.bimCtr=${Binary(u.bpuMeta.bimCtr)}\n")
130    XSDebug("needToUpdate=%d updateBank=%x updateRow=%x newCtr=%b oldCtr=%b\n", needToUpdate, updateBank, updateRow, newCtr, oldCtr)
131    XSDebug("[wrbypass] hit=%d hits=%b\n", wrbypass_hit, wrbypass_hits.asUInt)
132  }
133
134}