xref: /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala (revision 53c7ab8b2e79de0fa70909ea81a51720f666aaeb) 
1package xiangshan.frontend
2
3import chisel3._
4import chisel3.util._
5import xiangshan._
6import utils._
7import chisel3.experimental.chiselName
8
9trait BimParams extends HasXSParameter {
10  val BimBanks = PredictWidth
11  val BimSize = 4096
12  val nRows = BimSize / BimBanks
13  val bypassEntries = 4
14}
15
16@chiselName
17class BIM extends BasePredictor with BimParams {
18  class BIMResp extends Resp {
19    val ctrs = Vec(PredictWidth, UInt(2.W))
20  }
21  class BIMMeta extends Meta {
22    val ctrs = Vec(PredictWidth, UInt(2.W))
23  }
24  class BIMFromOthers extends FromOthers {}
25
26  class BIMIO extends DefaultBasePredictorIO {
27    val resp = Output(new BIMResp)
28    val meta = Output(new BIMMeta)
29  }
30
31  override val io = IO(new BIMIO)
32  override val debug = true
33
34  val bimAddr = new TableAddr(log2Up(BimSize), BimBanks)
35
36  val bim = List.fill(BimBanks) {
37    Module(new SRAMTemplate(UInt(2.W), set = nRows, shouldReset = false, holdRead = true))
38  }
39
40  val doing_reset = RegInit(true.B)
41  val resetRow = RegInit(0.U(log2Ceil(nRows).W))
42  resetRow := resetRow + doing_reset
43  when (resetRow === (nRows-1).U) { doing_reset := false.B }
44
45  val if1_packetAlignedPC = packetAligned(io.pc.bits)
46  val if2_pc = RegEnable(if1_packetAlignedPC, io.pc.valid)
47
48  val if1_mask = io.inMask
49  val if1_row  = bimAddr.getBankIdx(if1_packetAlignedPC)
50
51  for (b <- 0 until BimBanks) {
52    bim(b).io.r.req.valid       := if1_mask(b) && io.pc.valid
53    bim(b).io.r.req.bits.setIdx := if1_row
54  }
55
56  val if2_bimRead = VecInit(bim.map(_.io.r.resp.data(0)))
57
58  for (b <- 0 until BimBanks) {
59    io.resp.ctrs(b)  := if2_bimRead(b)
60    io.meta.ctrs(b)  := if2_bimRead(b)
61  }
62
63  val u = io.update.bits
64
65  val updateRow = bimAddr.getBankIdx(u.ftqPC)
66
67
68  val wrbypass_ctrs       = Reg(Vec(bypassEntries, Vec(BimBanks, UInt(2.W))))
69  val wrbypass_ctr_valids = Reg(Vec(bypassEntries, Vec(BimBanks, Bool())))
70  val wrbypass_rows     = Reg(Vec(bypassEntries, UInt(log2Up(nRows).W)))
71  val wrbypass_enq_idx  = RegInit(0.U(log2Up(bypassEntries).W))
72
73  val wrbypass_hits = VecInit((0 until bypassEntries).map( i =>
74    !doing_reset && wrbypass_rows(i) === updateRow))
75  val wrbypass_hit = wrbypass_hits.reduce(_||_)
76  val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
77
78  val oldCtrs = VecInit((0 until BimBanks).map(b =>
79                  Mux(wrbypass_hit && wrbypass_ctr_valids(wrbypass_hit_idx)(b),
80                    wrbypass_ctrs(wrbypass_hit_idx)(b), u.metas(b).bimCtr)))
81
82  val newTakens = VecInit((0 until BimBanks).map(b => u.cfiIndex.valid && u.cfiIndex.bits === b.U))
83  val newCtrs = VecInit((0 until BimBanks).map(b => satUpdate(oldCtrs(b), 2, newTakens(b))))
84  // val oldSaturated = newCtr === oldCtr
85
86  val needToUpdate = VecInit((0 until PredictWidth).map(i => io.update.valid && u.br_mask(i) && u.valids(i)))
87
88  when (reset.asBool) { wrbypass_ctr_valids.foreach(_.foreach(_ := false.B))}
89
90  for (b <- 0 until BimBanks) {
91    when (needToUpdate(b)) {
92      when (wrbypass_hit) {
93        wrbypass_ctrs(wrbypass_hit_idx)(b) := newCtrs(b)
94        wrbypass_ctr_valids(wrbypass_hit_idx)(b) := true.B
95      } .otherwise {
96        wrbypass_ctrs(wrbypass_enq_idx)(b) := newCtrs(b)
97        (0 until BimBanks).foreach(b => wrbypass_ctr_valids(wrbypass_enq_idx)(b) := false.B) // reset valid bits
98        wrbypass_ctr_valids(wrbypass_enq_idx)(b) := true.B
99        wrbypass_rows(wrbypass_enq_idx) := updateRow
100        wrbypass_enq_idx := (wrbypass_enq_idx + 1.U)(log2Up(bypassEntries)-1,0)
101      }
102    }
103  }
104
105  for (b <- 0 until BimBanks) {
106    bim(b).io.w.req.valid := needToUpdate(b) || doing_reset
107    bim(b).io.w.req.bits.setIdx := Mux(doing_reset, resetRow, updateRow)
108    bim(b).io.w.req.bits.data := Mux(doing_reset, 2.U(2.W), newCtrs(b))
109  }
110
111  if (BPUDebug && debug) {
112    XSDebug(doing_reset, "Reseting...\n")
113    XSDebug("[update] v=%d pc=%x valids=%b, tgt=%x\n", io.update.valid, u.ftqPC, u.valids.asUInt, u.target)
114
115    XSDebug("[update] brMask=%b, taken=%b isMisPred=%b\n", u.br_mask.asUInt, newTakens.asUInt, u.mispred.asUInt)
116    for (i <- 0 until BimBanks) {
117      XSDebug(true.B, p"bimCtr(${i.U})=${Binary(u.metas(i).bimCtr)} oldCtr=${Binary(oldCtrs(i))} newCtr=${Binary(newCtrs(i))}\n")
118    }
119    XSDebug("needToUpdate=%b updateRow=%x\n", needToUpdate.asUInt, updateRow)
120    XSDebug("[wrbypass] hit=%d hits=%b\n", wrbypass_hit, wrbypass_hits.asUInt)
121  }
122
123}