xref: /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala (revision 49272fa467f97c3293eb9ed685e99ecf79691182) 
1package xiangshan.frontend
2
3import chisel3._
4import chisel3.util._
5import xiangshan._
6import xiangshan.backend.ALUOpType
7import utils._
8import xiangshan.backend.decode.XSTrap
9import chisel3.experimental.chiselName
10
11trait BimParams extends HasXSParameter {
12  val BimBanks = PredictWidth
13  val BimSize = 4096
14  val nRows = BimSize / BimBanks
15  val bypassEntries = 4
16}
17
18@chiselName
19class BIM extends BasePredictor with BimParams {
20  class BIMResp extends Resp {
21    val ctrs = Vec(PredictWidth, UInt(2.W))
22  }
23  class BIMMeta extends Meta {
24    val ctrs = Vec(PredictWidth, UInt(2.W))
25  }
26  class BIMFromOthers extends FromOthers {}
27
28  class BIMIO extends DefaultBasePredictorIO {
29    val resp = Output(new BIMResp)
30    val meta = Output(new BIMMeta)
31  }
32
33  override val io = IO(new BIMIO)
34  override val debug = true
35
36  val bimAddr = new TableAddr(log2Up(BimSize), BimBanks)
37
38  val if1_bankAlignedPC = bankAligned(io.pc.bits)
39  val if2_pc = RegEnable(if1_bankAlignedPC, io.pc.valid)
40
41  val bim = List.fill(BimBanks) {
42    Module(new SRAMTemplate(UInt(2.W), set = nRows, shouldReset = false, holdRead = true))
43  }
44
45  val doing_reset = RegInit(true.B)
46  val resetRow = RegInit(0.U(log2Ceil(nRows).W))
47  resetRow := resetRow + doing_reset
48  when (resetRow === (nRows-1).U) { doing_reset := false.B }
49
50  // this bank means cache bank
51  val if1_startsAtOddBank = bankInGroup(if1_bankAlignedPC)(0)
52
53  val if1_realMask = Mux(if1_startsAtOddBank,
54                      Cat(io.inMask(bankWidth-1,0), io.inMask(PredictWidth-1, bankWidth)),
55                      io.inMask)
56
57
58  val if1_isInNextRow = VecInit((0 until BimBanks).map(i => Mux(if1_startsAtOddBank, (i < bankWidth).B, false.B)))
59
60  val if1_baseRow = bimAddr.getBankIdx(if1_bankAlignedPC)
61
62  val if1_realRow = VecInit((0 until BimBanks).map(b => Mux(if1_isInNextRow(b), (if1_baseRow+1.U)(log2Up(nRows)-1, 0), if1_baseRow)))
63
64  val if2_realRow = VecInit(if1_realRow.map(RegEnable(_, enable=io.pc.valid)))
65
66  for (b <- 0 until BimBanks) {
67    bim(b).io.r.req.valid       := if1_realMask(b) && io.pc.valid
68    bim(b).io.r.req.bits.setIdx := if1_realRow(b)
69  }
70
71  val if2_bimRead = VecInit(bim.map(_.io.r.resp.data(0)))
72
73  val if2_startsAtOddBank = bankInGroup(if2_pc)(0)
74
75  for (b <- 0 until BimBanks) {
76    val realBank = (if (b < bankWidth) Mux(if2_startsAtOddBank, (b+bankWidth).U, b.U)
77                    else Mux(if2_startsAtOddBank, (b-bankWidth).U, b.U))
78    val ctr = if2_bimRead(realBank)
79    io.resp.ctrs(b)  := ctr
80    io.meta.ctrs(b)  := ctr
81  }
82
83  val u = io.update.bits
84
85  val updateBank = bimAddr.getBank(u.pc)
86  val updateRow = bimAddr.getBankIdx(u.pc)
87
88
89  val wrbypass_ctrs       = Reg(Vec(bypassEntries, Vec(BimBanks, UInt(2.W))))
90  val wrbypass_ctr_valids = Reg(Vec(bypassEntries, Vec(BimBanks, Bool())))
91  val wrbypass_rows     = Reg(Vec(bypassEntries, UInt(log2Up(nRows).W)))
92  val wrbypass_enq_idx  = RegInit(0.U(log2Up(bypassEntries).W))
93
94  val wrbypass_hits = VecInit((0 until bypassEntries).map( i =>
95    !doing_reset && wrbypass_rows(i) === updateRow))
96  val wrbypass_hit = wrbypass_hits.reduce(_||_)
97  val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
98
99  val oldCtr = Mux(wrbypass_hit && wrbypass_ctr_valids(wrbypass_hit_idx)(updateBank), wrbypass_ctrs(wrbypass_hit_idx)(updateBank), u.bpuMeta.bimCtr)
100  val newTaken = u.taken
101  val newCtr = satUpdate(oldCtr, 2, newTaken)
102  // val oldSaturated = newCtr === oldCtr
103
104  val needToUpdate = io.update.valid && u.pd.isBr && !u.isReplay
105
106  when (reset.asBool) { wrbypass_ctr_valids.foreach(_.foreach(_ := false.B))}
107
108  when (needToUpdate) {
109    when (wrbypass_hit) {
110      wrbypass_ctrs(wrbypass_hit_idx)(updateBank) := newCtr
111      wrbypass_ctr_valids(wrbypass_enq_idx)(updateBank) := true.B
112    } .otherwise {
113      wrbypass_ctrs(wrbypass_hit_idx)(updateBank) := newCtr
114      (0 until BimBanks).foreach(b => wrbypass_ctr_valids(wrbypass_enq_idx)(b) := false.B) // reset valid bits
115      wrbypass_ctr_valids(wrbypass_enq_idx)(updateBank) := true.B
116      wrbypass_rows(wrbypass_enq_idx) := updateRow
117      wrbypass_enq_idx := (wrbypass_enq_idx + 1.U)(log2Up(bypassEntries)-1,0)
118    }
119  }
120
121  for (b <- 0 until BimBanks) {
122    bim(b).io.w.req.valid := needToUpdate && b.U === updateBank || doing_reset
123    bim(b).io.w.req.bits.setIdx := Mux(doing_reset, resetRow, updateRow)
124    bim(b).io.w.req.bits.data := Mux(doing_reset, 2.U(2.W), newCtr)
125  }
126
127  if (BPUDebug && debug) {
128    XSDebug(doing_reset, "Reseting...\n")
129    XSDebug("[update] v=%d pc=%x pnpc=%x tgt=%x", io.update.valid, u.pc, u.pnpc, u.target)
130    XSDebug("[update] taken=%d isMisPred=%d", u.taken, u.isMisPred)
131    XSDebug(false, true.B, p"brTag=${u.brTag} pd.isBr=${u.pd.isBr} brInfo.bimCtr=${Binary(u.bpuMeta.bimCtr)}\n")
132    XSDebug("needToUpdate=%d updateBank=%x updateRow=%x newCtr=%b oldCtr=%b\n", needToUpdate, updateBank, updateRow, newCtr, oldCtr)
133    XSDebug("[wrbypass] hit=%d hits=%b\n", wrbypass_hit, wrbypass_hits.asUInt)
134  }
135
136}