xref: /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala (revision 3802dba502b91d813c1e563035b876c4e6288166) 
1package xiangshan.frontend
2
3import chisel3._
4import chisel3.util._
5import xiangshan._
6import utils._
7import chisel3.experimental.chiselName
8
9trait BimParams extends HasXSParameter {
10  val BimBanks = PredictWidth
11  val BimSize = 4096
12  val nRows = BimSize / BimBanks
13  val bypassEntries = 4
14}
15
16@chiselName
17class BIM extends BasePredictor with BimParams {
18  class BIMResp extends Resp {
19    val ctrs = Vec(PredictWidth, UInt(2.W))
20  }
21  class BIMMeta extends Meta {
22    val ctrs = Vec(PredictWidth, UInt(2.W))
23  }
24  class BIMFromOthers extends FromOthers {}
25
26  class BIMIO extends DefaultBasePredictorIO {
27    val resp = Output(new BIMResp)
28    val meta = Output(new BIMMeta)
29  }
30
31  override val io = IO(new BIMIO)
32  override val debug = true
33
34  val bimAddr = new TableAddr(log2Up(BimSize), BimBanks)
35
36  val bim = List.fill(BimBanks) {
37    Module(new SRAMTemplate(UInt(2.W), set = nRows, shouldReset = false, holdRead = true))
38  }
39
40  val doing_reset = RegInit(true.B)
41  val resetRow = RegInit(0.U(log2Ceil(nRows).W))
42  resetRow := resetRow + doing_reset
43  when (resetRow === (nRows-1).U) { doing_reset := false.B }
44
45  val if1_packetAlignedPC = packetAligned(io.pc.bits)
46  val if2_pc = RegEnable(if1_packetAlignedPC, io.pc.valid)
47
48  val if1_mask = io.inMask
49  val if1_row  = bimAddr.getBankIdx(if1_packetAlignedPC)
50
51  for (b <- 0 until BimBanks) {
52    bim(b).io.r.req.valid       := if1_mask(b) && io.pc.valid
53    bim(b).io.r.req.bits.setIdx := if1_row
54  }
55
56  val if2_bimRead = VecInit(bim.map(_.io.r.resp.data(0)))
57
58  for (b <- 0 until BimBanks) {
59    io.resp.ctrs(b)  := if2_bimRead(b)
60    io.meta.ctrs(b)  := if2_bimRead(b)
61  }
62
63  val u = io.update.bits
64
65  val updateBank = bimAddr.getBank(u.pc)
66  val updateRow = bimAddr.getBankIdx(u.pc)
67
68
69  val wrbypass_ctrs       = Reg(Vec(bypassEntries, Vec(BimBanks, UInt(2.W))))
70  val wrbypass_ctr_valids = Reg(Vec(bypassEntries, Vec(BimBanks, Bool())))
71  val wrbypass_rows     = Reg(Vec(bypassEntries, UInt(log2Up(nRows).W)))
72  val wrbypass_enq_idx  = RegInit(0.U(log2Up(bypassEntries).W))
73
74  val wrbypass_hits = VecInit((0 until bypassEntries).map( i =>
75    !doing_reset && wrbypass_rows(i) === updateRow))
76  val wrbypass_hit = wrbypass_hits.reduce(_||_)
77  val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
78
79  val oldCtr = Mux(wrbypass_hit && wrbypass_ctr_valids(wrbypass_hit_idx)(updateBank), wrbypass_ctrs(wrbypass_hit_idx)(updateBank), u.bpuMeta.bimCtr)
80  val newTaken = u.taken
81  val newCtr = satUpdate(oldCtr, 2, newTaken)
82  // val oldSaturated = newCtr === oldCtr
83
84  val needToUpdate = io.update.valid && u.pd.isBr && !u.isReplay
85
86  when (reset.asBool) { wrbypass_ctr_valids.foreach(_.foreach(_ := false.B))}
87
88  when (needToUpdate) {
89    when (wrbypass_hit) {
90      wrbypass_ctrs(wrbypass_hit_idx)(updateBank) := newCtr
91      wrbypass_ctr_valids(wrbypass_hit_idx)(updateBank) := true.B
92    } .otherwise {
93      wrbypass_ctrs(wrbypass_enq_idx)(updateBank) := newCtr
94      (0 until BimBanks).foreach(b => wrbypass_ctr_valids(wrbypass_enq_idx)(b) := false.B) // reset valid bits
95      wrbypass_ctr_valids(wrbypass_enq_idx)(updateBank) := true.B
96      wrbypass_rows(wrbypass_enq_idx) := updateRow
97      wrbypass_enq_idx := (wrbypass_enq_idx + 1.U)(log2Up(bypassEntries)-1,0)
98    }
99  }
100
101  for (b <- 0 until BimBanks) {
102    bim(b).io.w.req.valid := needToUpdate && b.U === updateBank || doing_reset
103    bim(b).io.w.req.bits.setIdx := Mux(doing_reset, resetRow, updateRow)
104    bim(b).io.w.req.bits.data := Mux(doing_reset, 2.U(2.W), newCtr)
105  }
106
107  if (!env.FPGAPlatform && env.EnablePerfDebug) {
108    val bimResp = Wire(Vec(PredictWidth, Bool()))
109    for(i <- 0 until PredictWidth) {
110      bimResp(i) := io.resp.ctrs(i)(1)
111    }
112    ExcitingUtils.addSource(bimResp, "bimResp")
113  }
114
115  if (BPUDebug && debug) {
116    XSDebug(doing_reset, "Reseting...\n")
117    XSDebug("[update] v=%d pc=%x pnpc=%x tgt=%x", io.update.valid, u.pc, u.pnpc, u.target)
118    XSDebug("[update] taken=%d isMisPred=%d", u.taken, u.isMisPred)
119    XSDebug(false, true.B, p"brTag=${u.brTag} pd.isBr=${u.pd.isBr} brInfo.bimCtr=${Binary(u.bpuMeta.bimCtr)}\n")
120    XSDebug("needToUpdate=%d updateBank=%x updateRow=%x newCtr=%b oldCtr=%b\n", needToUpdate, updateBank, updateRow, newCtr, oldCtr)
121    XSDebug("[wrbypass] hit=%d hits=%b\n", wrbypass_hit, wrbypass_hits.asUInt)
122  }
123
124}