xref: /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala (revision 10b9babd805e02359c6fee797c66e99cd4a296ec) 
1package xiangshan.frontend
2
3import chisel3._
4import chisel3.util._
5import xiangshan._
6import xiangshan.backend.ALUOpType
7import utils._
8import chisel3.util.experimental.BoringUtils
9import xiangshan.backend.decode.XSTrap
10
11trait BimParams extends HasXSParameter {
12  val BimBanks = PredictWidth
13  val BimSize = 4096
14  val nRows = BimSize / BimBanks
15  val bypassEntries = 4
16}
17
18class BIM extends BasePredictor with BimParams{
19  class BIMResp extends Resp {
20    val ctrs = Vec(PredictWidth, UInt(2.W))
21  }
22  class BIMMeta extends Meta {
23    val ctrs = Vec(PredictWidth, UInt(2.W))
24  }
25  class BIMFromOthers extends FromOthers {}
26
27  class BIMIO extends DefaultBasePredictorIO {
28    val resp = Output(new BIMResp)
29    val meta = Output(new BIMMeta)
30  }
31
32  override val io = IO(new BIMIO)
33  // Update logic
34  // 1 calculate new 2-bit saturated counter value
35  def satUpdate(old: UInt, len: Int, taken: Bool): UInt = {
36    val oldSatTaken = old === ((1 << len)-1).U
37    val oldSatNotTaken = old === 0.U
38    Mux(oldSatTaken && taken, ((1 << len)-1).U,
39      Mux(oldSatNotTaken && !taken, 0.U,
40        Mux(taken, old + 1.U, old - 1.U)))
41  }
42
43  val bimAddr = new TableAddr(log2Up(BimSize), BimBanks)
44
45  val pcLatch = RegEnable(io.pc.bits, io.pc.valid)
46
47  val bim = List.fill(BimBanks) {
48    Module(new SRAMTemplate(UInt(2.W), set = nRows, shouldReset = false, holdRead = true))
49  }
50
51  val doing_reset = RegInit(true.B)
52  val resetRow = RegInit(0.U(log2Ceil(nRows).W))
53  resetRow := resetRow + doing_reset
54  when (resetRow === (nRows-1).U) { doing_reset := false.B }
55
56  val baseBank = bimAddr.getBank(io.pc.bits)
57
58  val realMask = circularShiftRight(io.inMask, BimBanks, baseBank)
59
60  // those banks whose indexes are less than baseBank are in the next row
61  val isInNextRow = VecInit((0 until BtbBanks).map(_.U < baseBank))
62
63  val baseRow = bimAddr.getBankIdx(io.pc.bits)
64
65  val realRow = VecInit((0 until BimBanks).map(b => Mux(isInNextRow(b.U), (baseRow+1.U)(log2Up(nRows)-1, 0), baseRow)))
66
67  val realRowLatch = VecInit(realRow.map(RegEnable(_, enable=io.pc.valid)))
68
69  for (b <- 0 until BimBanks) {
70    bim(b).reset                := reset.asBool
71    bim(b).io.r.req.valid       := realMask(b) && io.pc.valid
72    bim(b).io.r.req.bits.setIdx := realRow(b)
73  }
74
75  val bimRead = VecInit(bim.map(_.io.r.resp.data(0)))
76
77  val baseBankLatch = bimAddr.getBank(pcLatch)
78
79  // e.g: baseBank == 5 => (5, 6,..., 15, 0, 1, 2, 3, 4)
80  val bankIdxInOrder = VecInit((0 until BimBanks).map(b => (baseBankLatch +& b.U)(log2Up(BimBanks)-1, 0)))
81
82  for (b <- 0 until BimBanks) {
83    val ctr = bimRead(bankIdxInOrder(b))
84    io.resp.ctrs(b)  := ctr
85    io.meta.ctrs(b)  := ctr
86  }
87
88  val u = io.update.bits.ui
89
90  val updateBank = bimAddr.getBank(u.pc)
91  val updateRow = bimAddr.getBankIdx(u.pc)
92
93
94  val wrbypass_ctrs       = Reg(Vec(bypassEntries, Vec(BimBanks, UInt(2.W))))
95  val wrbypass_ctr_valids = Reg(Vec(bypassEntries, Vec(BimBanks, Bool())))
96  val wrbypass_rows     = Reg(Vec(bypassEntries, UInt(log2Up(nRows).W)))
97  val wrbypass_enq_idx  = RegInit(0.U(log2Up(bypassEntries).W))
98
99  val wrbypass_hits = VecInit((0 until bypassEntries).map( i =>
100    !doing_reset && wrbypass_rows(i) === updateRow))
101  val wrbypass_hit = wrbypass_hits.reduce(_||_)
102  val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
103
104  val oldCtr = Mux(wrbypass_hit && wrbypass_ctr_valids(wrbypass_hit_idx)(updateBank), wrbypass_ctrs(wrbypass_hit_idx)(updateBank), u.brInfo.bimCtr)
105  val newTaken = u.taken
106  val newCtr = satUpdate(oldCtr, 2, newTaken)
107  // val oldSaturated = newCtr === oldCtr
108
109  val needToUpdate = io.update.valid && u.pd.isBr
110
111  when (reset.asBool) { wrbypass_ctr_valids.foreach(_.foreach(_ := false.B))}
112
113  when (needToUpdate) {
114    when (wrbypass_hit) {
115      wrbypass_ctrs(wrbypass_hit_idx)(updateBank) := newCtr
116      wrbypass_ctr_valids(wrbypass_enq_idx)(updateBank) := true.B
117    } .otherwise {
118      wrbypass_ctrs(wrbypass_hit_idx)(updateBank) := newCtr
119      (0 until BimBanks).foreach(b => wrbypass_ctr_valids(wrbypass_enq_idx)(b) := false.B) // reset valid bits
120      wrbypass_ctr_valids(wrbypass_enq_idx)(updateBank) := true.B
121      wrbypass_rows(wrbypass_enq_idx) := updateRow
122      wrbypass_enq_idx := (wrbypass_enq_idx + 1.U)(log2Up(bypassEntries)-1,0)
123    }
124  }
125
126  for (b <- 0 until BimBanks) {
127    bim(b).io.w.req.valid := needToUpdate && b.U === updateBank || doing_reset
128    bim(b).io.w.req.bits.setIdx := Mux(doing_reset, resetRow, updateRow)
129    bim(b).io.w.req.bits.data := Mux(doing_reset, 2.U(2.W), newCtr)
130  }
131
132  if (BPUDebug && debug) {
133    XSDebug(doing_reset, "Reseting...\n")
134    XSDebug("[update] v=%d pc=%x pnpc=%x tgt=%x brTgt=%x\n", io.update.valid, u.pc, u.pnpc, u.target, u.brTarget)
135    XSDebug("[update] taken=%d isMisPred=%d", u.taken, u.isMisPred)
136    XSDebug(false, true.B, p"brTag=${u.brTag} pd.isBr=${u.pd.isBr} brInfo.bimCtr=${Binary(u.brInfo.bimCtr)}\n")
137    XSDebug("needToUpdate=%d updateBank=%x updateRow=%x newCtr=%b oldCtr=%b\n", needToUpdate, updateBank, updateRow, newCtr, oldCtr)
138    XSDebug("[wrbypass] hit=%d hits=%b\n", wrbypass_hit, wrbypass_hits.asUInt)
139  }
140
141}