1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import utils._ 24import xiangshan.backend.roq.RoqPtr 25import xiangshan.backend.fu.util.HasCSRConst 26 27class TLB(Width: Int, isDtlb: Boolean)(implicit p: Parameters) extends TlbModule with HasCSRConst{ 28 val io = IO(new TlbIO(Width)) 29 30 val req = io.requestor.map(_.req) 31 val resp = io.requestor.map(_.resp) 32 val ptw = io.ptw 33 34 val sfence = io.sfence 35 val csr = io.csr 36 val satp = csr.satp 37 val priv = csr.priv 38 val ifecth = if (isDtlb) false.B else true.B 39 val mode = if (isDtlb) priv.dmode else priv.imode 40 // val vmEnable = satp.mode === 8.U // && (mode < ModeM) // FIXME: fix me when boot xv6/linux... 41 val vmEnable = if(EnbaleTlbDebug) (satp.mode === 8.U) 42 else (satp.mode === 8.U && (mode < ModeM)) 43 44 val reqAddr = req.map(_.bits.vaddr.asTypeOf(vaBundle)) 45 val cmd = req.map(_.bits.cmd) 46 val valid = req.map(_.valid) 47 48 def widthMapSeq[T <: Seq[Data]](f: Int => T) = (0 until Width).map(f) 49 def widthMap[T <: Data](f: Int => T) = (0 until Width).map(f) 50 51 // Normal page && Super page 52 val nv = RegInit(VecInit(Seq.fill(TlbEntrySize)(false.B))) 53 val nMeta = Module(new CAMTemplate(UInt(vpnLen.W), TlbEntrySize, Width + 1)).io 54 val nData = Reg(Vec(TlbEntrySize, new TlbData(false))) 55 val sv = RegInit(VecInit(Seq.fill(TlbSPEntrySize)(false.B))) 56 val sMeta = Reg(Vec(TlbSPEntrySize, new TlbSPMeta)) 57 val sData = Reg(Vec(TlbSPEntrySize, new TlbData(true))) 58 val v = nv ++ sv 59 val data = nData ++ sData 60 val g = VecInit(data.map(_.perm.g)) 61 val pf = VecInit(data.zip(v).map{ case(e, vi) => e.perm.pf & vi }) 62 63 /** 64 * PTW refill 65 */ 66 val refill = ptw.resp.fire() && !sfence.valid 67 68 val normalReplacer = if (isDtlb) Some("random") else Some("plru") 69 val superReplacer = if (isDtlb) Some("random") else Some("plru") 70 val nReplace = ReplacementPolicy.fromString(normalReplacer, TlbEntrySize) 71 val sReplace = ReplacementPolicy.fromString(superReplacer, TlbSPEntrySize) 72 val nRefillIdx = replaceWrapper(nv, nReplace.way) 73 val sRefillIdx = replaceWrapper(sv, sReplace.way) 74 75 nMeta.w := DontCare 76 nMeta.w.valid := false.B 77 when (refill) { 78 val resp = ptw.resp.bits 79 when (resp.entry.level.getOrElse(0.U) === 2.U) { 80 val refillIdx = nRefillIdx 81 refillIdx.suggestName(s"NormalRefillIdx") 82 83 nv(refillIdx) := true.B 84 nMeta.w.bits.index := nRefillIdx 85 nMeta.w.bits.data := resp.entry.tag 86 nMeta.w.valid := true.B 87 nData(refillIdx).apply( 88 ppn = resp.entry.ppn, 89 level = resp.entry.level.getOrElse(0.U), 90 perm = VecInit(resp.entry.perm.getOrElse(0.U)).asUInt, 91 pf = resp.pf 92 ) 93 nReplace.access(nRefillIdx) 94 XSDebug(p"Refill normal: idx:${refillIdx} entry:${resp.entry} pf:${resp.pf}\n") 95 }.otherwise { 96 val refillIdx = sRefillIdx 97 refillIdx.suggestName(s"SuperRefillIdx") 98 99 val dup = Cat(sv.zip(sMeta).map{ case (v, m) => 100 v && m.hit(resp.entry.tag) 101 }).orR // NOTE: may have long latency, RegNext it 102 103 when (!dup) { 104 sv(refillIdx) := true.B 105 sMeta(refillIdx).apply( 106 vpn = resp.entry.tag, 107 level = resp.entry.level.getOrElse(0.U) 108 ) 109 sData(refillIdx).apply( 110 ppn = resp.entry.ppn, 111 level = resp.entry.level.getOrElse(0.U), 112 perm = VecInit(resp.entry.perm.getOrElse(0.U)).asUInt, 113 pf = resp.pf 114 ) 115 sReplace.access(sRefillIdx) 116 XSDebug(p"Refill superpage: idx:${refillIdx} entry:${resp.entry} pf:${resp.pf}\n") 117 } 118 } 119 } 120 121 /** 122 * L1 TLB read 123 */ 124 val sfenceVpn = sfence.bits.addr.asTypeOf(vaBundle).vpn 125 for (i <- 0 until Width) { 126 nMeta.r.req(i) := io.requestor(i).req.bits.vaddr.asTypeOf(vaBundle).vpn 127 } 128 nMeta.r.req(Width) := sfenceVpn 129 130 val nRefillMask = Mux(refill, UIntToOH(nRefillIdx)(TlbEntrySize-1, 0), 0.U).asBools 131 val sRefillMask = Mux(refill, UIntToOH(sRefillIdx)(TlbSPEntrySize-1, 0), 0.U).asBools 132 def TLBNormalRead(i: Int) = { 133 val entryHitVec = ( 134 if (isDtlb) 135 VecInit(nMeta.r.resp(i).zip(nRefillMask).map{ case (e, m) => ~m && e } ++ 136 sMeta.zip(sRefillMask).map{ case (e,m) => ~m && e.hit(reqAddr(i).vpn) }) 137 else 138 VecInit(nMeta.r.resp(i) ++ sMeta.map(_.hit(reqAddr(i).vpn/*, satp.asid*/))) 139 ) 140 141 val reqAddrReg = if (isDtlb) RegNext(reqAddr(i)) else reqAddr(i) 142 val cmdReg = if (isDtlb) RegNext(cmd(i)) else cmd(i) 143 val validReg = if (isDtlb) RegNext(valid(i)) else valid(i) 144 val entryHitVecReg = if (isDtlb) RegNext(entryHitVec) else entryHitVec 145 entryHitVecReg.suggestName(s"entryHitVecReg_${i}") 146 147 /***************** next cycle when two cycle is need********************/ 148 149 val hitVec = VecInit((v zip entryHitVecReg).map{ case (a,b) => a&b }) 150 val pfHitVec = VecInit((pf zip entryHitVecReg).map{ case (a,b) => a&b }) 151 val pfArray = ParallelOR(pfHitVec).asBool && validReg && vmEnable 152 val hit = ParallelOR(hitVec).asBool && validReg && vmEnable && ~pfArray 153 val miss = !hit && validReg && vmEnable && ~pfArray 154 val hitppn = ParallelMux(hitVec zip data.map(_.genPPN(reqAddrReg.vpn))) 155 val hitPerm = ParallelMux(hitVec zip data.map(_.perm)) 156 157 hitVec.suggestName(s"hitVec_${i}") 158 pfHitVec.suggestName(s"pfHitVec_${i}") 159 hit.suggestName(s"hit_${i}") 160 miss.suggestName(s"miss_${i}") 161 hitppn.suggestName(s"hitppn_${i}") 162 hitPerm.suggestName(s"hitPerm_${i}") 163 164 XSDebug(valid(i), p"(${i.U}) entryHit:${Hexadecimal(entryHitVec.asUInt)}\n") 165 XSDebug(validReg, p"(${i.U}) entryHitReg:${Hexadecimal(entryHitVecReg.asUInt)} hitVec:${Hexadecimal(hitVec.asUInt)} pfHitVec:${Hexadecimal(pfHitVec.asUInt)} pfArray:${Hexadecimal(pfArray.asUInt)} hit:${hit} miss:${miss} hitppn:${Hexadecimal(hitppn)} hitPerm:${hitPerm}\n") 166 167 // resp // TODO: A/D has not being concerned 168 val paddr = Cat(hitppn, reqAddrReg.off) 169 val vaddr = SignExt(req(i).bits.vaddr, PAddrBits) 170 171 req(i).ready := resp(i).ready 172 resp(i).valid := validReg 173 resp(i).bits.paddr := Mux(vmEnable, paddr, if (isDtlb) RegNext(vaddr) else vaddr) 174 resp(i).bits.miss := miss 175 resp(i).bits.ptwBack := io.ptw.resp.fire() 176 177 val perm = hitPerm // NOTE: given the excp, the out module choose one to use? 178 val update = hit && (!hitPerm.a || !hitPerm.d && TlbCmd.isWrite(cmdReg)) // update A/D through exception 179 val modeCheck = !(mode === ModeU && !perm.u || mode === ModeS && perm.u && (!priv.sum || ifecth)) 180 val ldPf = (pfArray && TlbCmd.isRead(cmdReg) && true.B /*!isAMO*/) || hit && !(modeCheck && (perm.r || priv.mxr && perm.x)) && (TlbCmd.isRead(cmdReg) && true.B/*!isAMO*/) // TODO: handle isAMO 181 val stPf = (pfArray && TlbCmd.isWrite(cmdReg) || false.B /*isAMO*/ ) || hit && !(modeCheck && perm.w) && (TlbCmd.isWrite(cmdReg) || false.B/*TODO isAMO. */) 182 val instrPf = (pfArray && TlbCmd.isExec(cmdReg)) || hit && !(modeCheck && perm.x) && TlbCmd.isExec(cmdReg) 183 resp(i).bits.excp.pf.ld := ldPf || update 184 resp(i).bits.excp.pf.st := stPf || update 185 resp(i).bits.excp.pf.instr := instrPf || update 186 187 // if vmenable, use pre-calcuated pma check result 188 resp(i).bits.mmio := Mux(TlbCmd.isExec(cmdReg), !perm.pi, !perm.pd) 189 resp(i).bits.excp.af.ld := Mux(TlbCmd.isAtom(cmdReg), !perm.pa, !perm.pr) && TlbCmd.isRead(cmdReg) 190 resp(i).bits.excp.af.st := Mux(TlbCmd.isAtom(cmdReg), !perm.pa, !perm.pw) && TlbCmd.isWrite(cmdReg) 191 resp(i).bits.excp.af.instr := Mux(TlbCmd.isAtom(cmdReg), false.B, !perm.pe) 192 193 // if !vmenable, check pma 194 val (pmaMode, accessWidth) = AddressSpace.memmapAddrMatch(resp(i).bits.paddr) 195 when(!vmEnable){ 196 resp(i).bits.mmio := Mux(TlbCmd.isExec(cmdReg), !PMAMode.icache(pmaMode), !PMAMode.dcache(pmaMode)) 197 resp(i).bits.excp.af.ld := Mux(TlbCmd.isAtom(cmdReg), !PMAMode.atomic(pmaMode), !PMAMode.read(pmaMode)) && TlbCmd.isRead(cmdReg) 198 resp(i).bits.excp.af.st := Mux(TlbCmd.isAtom(cmdReg), !PMAMode.atomic(pmaMode), !PMAMode.write(pmaMode)) && TlbCmd.isWrite(cmdReg) 199 resp(i).bits.excp.af.instr := Mux(TlbCmd.isAtom(cmdReg), false.B, !PMAMode.execute(pmaMode)) 200 } 201 202 // TODO: MMIO check 203 204 (hit, miss, hitVec, validReg) 205 } 206 207 val readResult = (0 until Width).map(TLBNormalRead(_)) 208 val hitVec = readResult.map(res => res._1) 209 val missVec = readResult.map(res => res._2) 210 val hitVecVec = readResult.map(res => res._3) 211 val validRegVec = readResult.map(res => res._4) 212 213 // replacement 214 def get_access_index(one_hot: UInt): Valid[UInt] = { 215 val res = Wire(Valid(UInt(log2Up(one_hot.getWidth).W))) 216 res.valid := Cat(one_hot).orR 217 res.bits := OHToUInt(one_hot) 218 res 219 } 220 def get_access(one_hot: Seq[Bool], stop: Int, start: Int): Valid[UInt] = { 221 val tmp = VecInit(one_hot).asUInt 222 get_access_index(tmp(stop, start)) 223 } 224 val nAccess = hitVecVec.map(a => get_access(a, TlbEntrySize - 1, 0)) 225 val sAccess = hitVecVec.map(a => get_access(a, TlbEntrySize + TlbSPEntrySize - 1, TlbEntrySize)) 226 if (Width == 1) { 227 when (nAccess(0).valid) { nReplace.access(nAccess(0).bits) } 228 when (sAccess(0).valid) { sReplace.access(sAccess(0).bits) } 229 } else { 230 nReplace.access(nAccess) 231 sReplace.access(sAccess) 232 } 233 234 for (i <- 0 until Width) { 235 io.ptw.req(i).valid := validRegVec(i) && missVec(i) && !RegNext(refill) 236 io.ptw.req(i).bits.vpn := RegNext(reqAddr(i).vpn) 237 } 238 io.ptw.resp.ready := true.B 239 240 // val tooManyPf = PopCount(pf) > 5.U 241 // when (tooManyPf) { // when too much pf, just clear 242 // XSDebug(p"Too many pf just flush all the pf v:${Hexadecimal(VecInit(v).asUInt)} pf:${Hexadecimal(pf.asUInt)}\n") 243 // v.zipWithIndex.map{ case (a, i) => a := a & !pf(i) } 244 // } 245 246 // sfence (flush) 247 val sfenceHit = nMeta.r.resp(Width) ++ sMeta.map(_.hit(sfenceVpn)) 248 when (sfence.valid) { 249 when (sfence.bits.rs1) { // virtual address *.rs1 <- (rs1===0.U) 250 when (sfence.bits.rs2) { // asid, but i do not want to support asid, *.rs2 <- (rs2===0.U) 251 // all addr and all asid 252 v.map(_ := false.B) 253 }.otherwise { 254 // all addr but specific asid 255 v.zipWithIndex.map{ case (a,i) => a := a & g(i) } 256 } 257 }.otherwise { 258 when (sfence.bits.rs2) { 259 // specific addr but all asid 260 v.zipWithIndex.map{ case (a,i) => a := a & !sfenceHit(i) } 261 }.otherwise { 262 // specific addr and specific asid 263 v.zipWithIndex.map{ case (a,i) => a := a & !sfenceHit(i) && !g(i) } 264 } 265 } 266 } 267 268 if (isDtlb) { 269 for (i <- 0 until Width) { 270 XSPerfAccumulate("first_access" + Integer.toString(i, 10), validRegVec(i) && vmEnable && RegNext(req(i).bits.debug.isFirstIssue)) 271 XSPerfAccumulate("access" + Integer.toString(i, 10), validRegVec(i) && vmEnable) 272 } 273 for (i <- 0 until Width) { 274 XSPerfAccumulate("first_miss" + Integer.toString(i, 10), validRegVec(i) && vmEnable && missVec(i) && RegNext(req(i).bits.debug.isFirstIssue)) 275 XSPerfAccumulate("miss" + Integer.toString(i, 10), validRegVec(i) && vmEnable && missVec(i)) 276 } 277 } else { 278 // NOTE: ITLB is blocked, so every resp will be valid only when hit 279 // every req will be ready only when hit 280 XSPerfAccumulate("access", io.requestor(0).req.fire() && vmEnable) 281 XSPerfAccumulate("miss", ptw.req(0).fire()) 282 } 283 //val reqCycleCnt = Reg(UInt(16.W)) 284 //reqCycleCnt := reqCycleCnt + BoolStopWatch(ptw.req(0).fire(), ptw.resp.fire || sfence.valid) 285 //XSPerfAccumulate("ptw_req_count", ptw.req.fire()) 286 //XSPerfAccumulate("ptw_req_cycle", Mux(ptw.resp.fire(), reqCycleCnt, 0.U)) 287 XSPerfAccumulate("ptw_resp_count", ptw.resp.fire()) 288 XSPerfAccumulate("ptw_resp_pf_count", ptw.resp.fire() && ptw.resp.bits.pf) 289 for (i <- 0 until TlbEntrySize) { 290 val indexHitVec = hitVecVec.zip(validRegVec).map{ case (h, v) => h(i) && v } 291 XSPerfAccumulate(s"NormalAccessIndex${i}", Mux(vmEnable, PopCount(indexHitVec), 0.U)) 292 } 293 for (i <- 0 until TlbSPEntrySize) { 294 val indexHitVec = hitVecVec.zip(validRegVec).map{ case (h, v) => h(i + TlbEntrySize) && v } 295 XSPerfAccumulate(s"SuperAccessIndex${i}", Mux(vmEnable, PopCount(indexHitVec), 0.U)) 296 } 297 for (i <- 0 until TlbEntrySize) { 298 XSPerfAccumulate(s"NormalRefillIndex${i}", refill && ptw.resp.bits.entry.level.getOrElse(0.U) === 2.U && i.U === nRefillIdx) 299 } 300 for (i <- 0 until TlbSPEntrySize) { 301 XSPerfAccumulate(s"SuperRefillIndex${i}", refill && ptw.resp.bits.entry.level.getOrElse(0.U) =/= 2.U && i.U === sRefillIdx) 302 } 303 304 // Log 305 for(i <- 0 until Width) { 306 XSDebug(req(i).valid, p"req(${i.U}): (${req(i).valid} ${req(i).ready}) ${req(i).bits}\n") 307 XSDebug(resp(i).valid, p"resp(${i.U}): (${resp(i).valid} ${resp(i).ready}) ${resp(i).bits}\n") 308 } 309 310 XSDebug(sfence.valid, p"Sfence: ${sfence}\n") 311 XSDebug(ParallelOR(valid)|| ptw.resp.valid, p"CSR: ${csr}\n") 312 XSDebug(ParallelOR(valid) || ptw.resp.valid, p"vmEnable:${vmEnable} hit:${Binary(VecInit(hitVec).asUInt)} miss:${Binary(VecInit(missVec).asUInt)} v:${Hexadecimal(VecInit(v).asUInt)} pf:${Hexadecimal(pf.asUInt)}\n") 313 for (i <- ptw.req.indices) { 314 XSDebug(ptw.req(i).fire(), p"PTW req:${ptw.req(i).bits}\n") 315 } 316 XSDebug(ptw.resp.valid, p"PTW resp:${ptw.resp.bits} (v:${ptw.resp.valid}r:${ptw.resp.ready}) \n") 317 318// // NOTE: just for simple tlb debug, comment it after tlb's debug 319 // assert(!io.ptw.resp.valid || io.ptw.resp.bits.entry.tag === io.ptw.resp.bits.entry.ppn, "Simple tlb debug requires vpn === ppn") 320} 321 322object TLB { 323 def apply 324 ( 325 in: Seq[BlockTlbRequestIO], 326 sfence: SfenceBundle, 327 csr: TlbCsrBundle, 328 width: Int, 329 isDtlb: Boolean, 330 shouldBlock: Boolean 331 )(implicit p: Parameters) = { 332 require(in.length == width) 333 334 val tlb = Module(new TLB(width, isDtlb)) 335 336 tlb.io.sfence <> sfence 337 tlb.io.csr <> csr 338 339 if (!shouldBlock) { // dtlb 340 for (i <- 0 until width) { 341 tlb.io.requestor(i) <> in(i) 342 // tlb.io.requestor(i).req.valid := in(i).req.valid 343 // tlb.io.requestor(i).req.bits := in(i).req.bits 344 // in(i).req.ready := tlb.io.requestor(i).req.ready 345 346 // in(i).resp.valid := tlb.io.requestor(i).resp.valid 347 // in(i).resp.bits := tlb.io.requestor(i).resp.bits 348 // tlb.io.requestor(i).resp.ready := in(i).resp.ready 349 } 350 } else { // itlb 351 require(width == 1) 352 tlb.io.requestor(0).req.valid := in(0).req.valid 353 tlb.io.requestor(0).req.bits := in(0).req.bits 354 in(0).req.ready := !tlb.io.requestor(0).resp.bits.miss && in(0).resp.ready && tlb.io.requestor(0).req.ready 355 356 in(0).resp.valid := tlb.io.requestor(0).resp.valid && !tlb.io.requestor(0).resp.bits.miss 357 in(0).resp.bits := tlb.io.requestor(0).resp.bits 358 tlb.io.requestor(0).resp.ready := in(0).resp.ready 359 } 360 361 tlb.io.ptw 362 } 363} 364