1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import difftest._ 23import freechips.rocketchip.util.SRAMAnnotation 24import xiangshan._ 25import utils._ 26import utility._ 27import xiangshan.backend.fu.{PMPChecker, PMPReqBundle, PMPConfig => XSPMPConfig} 28import xiangshan.backend.rob.RobPtr 29import xiangshan.backend.fu.util.HasCSRConst 30import freechips.rocketchip.rocket.PMPConfig 31 32/** TLB module 33 * support block request and non-block request io at the same time 34 * return paddr at next cycle, then go for pmp/pma check 35 * @param Width: The number of requestors 36 * @param Block: Blocked or not for each requestor ports 37 * @param q: TLB Parameters, like entry number, each TLB has its own parameters 38 * @param p: XiangShan Paramemters, like XLEN 39 */ 40 41class TLB(Width: Int, nRespDups: Int = 1, Block: Seq[Boolean], q: TLBParameters)(implicit p: Parameters) extends TlbModule 42 with HasCSRConst 43 with HasPerfEvents 44{ 45 val io = IO(new TlbIO(Width, nRespDups, q)) 46 47 val req = io.requestor.map(_.req) 48 val resp = io.requestor.map(_.resp) 49 val ptw = io.ptw 50 val pmp = io.pmp 51 val refill_to_mem = io.refill_to_mem 52 53 /** Sfence.vma & Svinval 54 * Sfence.vma will 1. flush old entries 2. flush inflight 3. flush pipe 55 * Svinval will 1. flush old entries 2. flush inflight 56 * So, Svinval will not flush pipe, which means 57 * it should not drop reqs from pipe and should return right resp 58 */ 59 val sfence = DelayN(io.sfence, q.fenceDelay) 60 val csr = io.csr 61 val satp = DelayN(io.csr.satp, q.fenceDelay) 62 val vsatp = DelayN(io.csr.vsatp, q.fenceDelay) 63 val hgatp = DelayN(io.csr.hgatp, q.fenceDelay) 64 65 val flush_mmu = DelayN(sfence.valid || csr.satp.changed || csr.vsatp.changed || csr.hgatp.changed, q.fenceDelay) 66 val mmu_flush_pipe = DelayN(sfence.valid && sfence.bits.flushPipe, q.fenceDelay) // for svinval, won't flush pipe 67 val flush_pipe = io.flushPipe 68 val redirect = io.redirect 69 val req_in = req 70 val req_out = req.map(a => RegEnable(a.bits, a.fire)) 71 val req_out_v = (0 until Width).map(i => ValidHold(req_in(i).fire && !req_in(i).bits.kill, resp(i).fire, flush_pipe(i))) 72 73 val isHyperInst = (0 until Width).map(i => req_out_v(i) && req_out(i).hyperinst) 74 75 // ATTENTION: csr and flush from backend are delayed. csr should not be later than flush. 76 // because, csr will influence tlb behavior. 77 val ifecth = if (q.fetchi) true.B else false.B 78 val mode_tmp = if (q.useDmode) csr.priv.dmode else csr.priv.imode 79 val mode = (0 until Width).map(i => Mux(isHyperInst(i), csr.priv.spvp, mode_tmp)) 80 val virt_in = csr.priv.virt 81 val virt_out = req.map(a => RegEnable(csr.priv.virt, a.fire)) 82 val sum = (0 until Width).map(i => Mux(virt_out(i) || isHyperInst(i), io.csr.priv.vsum, io.csr.priv.sum)) 83 val mxr = (0 until Width).map(i => Mux(virt_out(i) || isHyperInst(i), io.csr.priv.vmxr || io.csr.priv.mxr, io.csr.priv.mxr)) 84 val req_in_s2xlate = (0 until Width).map(i => MuxCase(noS2xlate, Seq( 85 (!(virt_in || req_in(i).bits.hyperinst)) -> noS2xlate, 86 (csr.vsatp.mode =/= 0.U && csr.hgatp.mode =/= 0.U) -> allStage, 87 (csr.vsatp.mode === 0.U) -> onlyStage2, 88 (csr.hgatp.mode === 0.U) -> onlyStage1 89 ))) 90 val req_out_s2xlate = (0 until Width).map(i => MuxCase(noS2xlate, Seq( 91 (!(virt_out(i) || isHyperInst(i))) -> noS2xlate, 92 (csr.vsatp.mode =/= 0.U && csr.hgatp.mode =/= 0.U) -> allStage, 93 (csr.vsatp.mode === 0.U) -> onlyStage2, 94 (csr.hgatp.mode === 0.U) -> onlyStage1 95 ))) 96 val need_gpa = RegInit(false.B) 97 val need_gpa_robidx = Reg(new RobPtr) 98 val need_gpa_vpn = Reg(UInt(vpnLen.W)) 99 val need_gpa_gvpn = Reg(UInt(vpnLen.W)) 100 val resp_gpa_refill = RegInit(false.B) 101 val hasGpf = Wire(Vec(Width, Bool())) 102 103 val Sv39Enable = satp.mode === 8.U 104 val Sv48Enable = satp.mode === 9.U 105 val Sv39x4Enable = vsatp.mode === 8.U || hgatp.mode === 8.U 106 val Sv48x4Enable = vsatp.mode === 9.U || hgatp.mode === 9.U 107 val vmEnable = (0 until Width).map(i => !(isHyperInst(i) || virt_out(i)) && ( 108 if (EnbaleTlbDebug) (Sv39Enable || Sv48Enable) 109 else (Sv39Enable || Sv48Enable) && (mode(i) < ModeM)) 110 ) 111 val s2xlateEnable = (0 until Width).map(i => (isHyperInst(i) || virt_out(i)) && (Sv39x4Enable || Sv48x4Enable) && (mode(i) < ModeM)) 112 val portTranslateEnable = (0 until Width).map(i => (vmEnable(i) || s2xlateEnable(i)) && RegEnable(!req(i).bits.no_translate, req(i).valid)) 113 114 115 val refill = ptw.resp.fire && !(ptw.resp.bits.getGpa) && !flush_mmu 116 refill_to_mem := DontCare 117 val entries = Module(new TlbStorageWrapper(Width, q, nRespDups)) 118 entries.io.base_connect(sfence, csr, satp) 119 if (q.outReplace) { io.replace <> entries.io.replace } 120 for (i <- 0 until Width) { 121 entries.io.r_req_apply(io.requestor(i).req.valid, get_pn(req_in(i).bits.vaddr), i, req_in_s2xlate(i)) 122 entries.io.w_apply(refill, ptw.resp.bits) 123 // TODO: RegNext enable:req.valid 124 resp(i).bits.debug.isFirstIssue := RegEnable(req(i).bits.debug.isFirstIssue, req(i).valid) 125 resp(i).bits.debug.robIdx := RegEnable(req(i).bits.debug.robIdx, req(i).valid) 126 } 127 128 // read TLB, get hit/miss, paddr, perm bits 129 val readResult = (0 until Width).map(TLBRead(_)) 130 val hitVec = readResult.map(_._1) 131 val missVec = readResult.map(_._2) 132 val pmp_addr = readResult.map(_._3) 133 val perm = readResult.map(_._4) 134 val g_perm = readResult.map(_._5) 135 // check pmp use paddr (for timing optization, use pmp_addr here) 136 // check permisson 137 (0 until Width).foreach{i => 138 when (RegNext(req(i).bits.no_translate)) { 139 pmp_check(req(i).bits.pmp_addr, req_out(i).size, req_out(i).cmd, i) 140 } .otherwise { 141 pmp_check(pmp_addr(i), req_out(i).size, req_out(i).cmd, i) 142 } 143 for (d <- 0 until nRespDups) { 144 perm_check(perm(i)(d), req_out(i).cmd, i, d, g_perm(i)(d), req_out(i).hlvx, req_out_s2xlate(i)) 145 } 146 hasGpf(i) := resp(i).bits.excp(0).gpf.ld || resp(i).bits.excp(0).gpf.st || resp(i).bits.excp(0).gpf.instr 147 } 148 149 // handle block or non-block io 150 // for non-block io, just return the above result, send miss to ptw 151 // for block io, hold the request, send miss to ptw, 152 // when ptw back, return the result 153 (0 until Width) foreach {i => 154 if (Block(i)) handle_block(i) 155 else handle_nonblock(i) 156 } 157 io.ptw.resp.ready := true.B 158 159 /************************ main body above | method/log/perf below ****************************/ 160 def TLBRead(i: Int) = { 161 val (e_hit, e_ppn, e_perm, e_g_perm, e_s2xlate) = entries.io.r_resp_apply(i) 162 val (p_hit, p_ppn, p_perm, p_gvpn, p_g_perm, p_s2xlate) = ptw_resp_bypass(get_pn(req_in(i).bits.vaddr), req_in_s2xlate(i)) 163 val enable = portTranslateEnable(i) 164 val isOnlys2xlate = req_out_s2xlate(i) === onlyStage2 165 val need_gpa_vpn_hit = need_gpa_vpn === get_pn(req_out(i).vaddr) 166 val isitlb = TlbCmd.isExec(req_out(i).cmd) 167 168 when (!isitlb && need_gpa_robidx.needFlush(redirect) || isitlb && flush_pipe(i)){ 169 need_gpa := false.B 170 resp_gpa_refill := false.B 171 need_gpa_vpn := 0.U 172 }.elsewhen (req_out_v(i) && !p_hit && !(resp_gpa_refill && need_gpa_vpn_hit) && !isOnlys2xlate && hasGpf(i) && need_gpa === false.B && !io.requestor(i).req_kill) { 173 need_gpa := true.B 174 need_gpa_vpn := get_pn(req_out(i).vaddr) 175 resp_gpa_refill := false.B 176 need_gpa_robidx := req_out(i).debug.robIdx 177 }.elsewhen (ptw.resp.fire && need_gpa && need_gpa_vpn === ptw.resp.bits.getVpn(need_gpa_vpn)) { 178 need_gpa_gvpn := ptw.resp.bits.s2.entry.tag 179 resp_gpa_refill := true.B 180 } 181 182 when (req_out_v(i) && hasGpf(i) && resp_gpa_refill && need_gpa_vpn_hit ){ 183 need_gpa := false.B 184 } 185 186 TimeOutAssert(need_gpa && !resp_gpa_refill, timeOutThreshold, s"port{i} need gpa long time not refill.") 187 188 val hit = e_hit || p_hit 189 val miss = (!hit && enable) || hasGpf(i) && !p_hit && !(resp_gpa_refill && need_gpa_vpn_hit) && !isOnlys2xlate 190 hit.suggestName(s"hit_read_${i}") 191 miss.suggestName(s"miss_read_${i}") 192 193 val vaddr = SignExt(req_out(i).vaddr, PAddrBits) 194 resp(i).bits.miss := miss 195 resp(i).bits.ptwBack := ptw.resp.fire 196 resp(i).bits.memidx := RegEnable(req_in(i).bits.memidx, req_in(i).valid) 197 198 val ppn = WireInit(VecInit(Seq.fill(nRespDups)(0.U(ppnLen.W)))) 199 val perm = WireInit(VecInit(Seq.fill(nRespDups)(0.U.asTypeOf(new TlbPermBundle)))) 200 val gvpn = WireInit(VecInit(Seq.fill(nRespDups)(0.U(vpnLen.W)))) 201 val g_perm = WireInit(VecInit(Seq.fill(nRespDups)(0.U.asTypeOf(new TlbPermBundle)))) 202 val r_s2xlate = WireInit(VecInit(Seq.fill(nRespDups)(0.U(2.W)))) 203 for (d <- 0 until nRespDups) { 204 ppn(d) := Mux(p_hit, p_ppn, e_ppn(d)) 205 perm(d) := Mux(p_hit, p_perm, e_perm(d)) 206 gvpn(d) := Mux(hasGpf(i), Mux(p_hit, p_gvpn, need_gpa_gvpn), 0.U) 207 g_perm(d) := Mux(p_hit, p_g_perm, e_g_perm(d)) 208 r_s2xlate(d) := Mux(p_hit, p_s2xlate, e_s2xlate(d)) 209 val paddr = Cat(ppn(d), get_off(req_out(i).vaddr)) 210 val gpaddr = Cat(gvpn(d), get_off(req_out(i).vaddr)) 211 resp(i).bits.paddr(d) := Mux(enable, paddr, vaddr) 212 resp(i).bits.gpaddr(d) := Mux(r_s2xlate(d) === onlyStage2, vaddr, gpaddr) 213 } 214 215 XSDebug(req_out_v(i), p"(${i.U}) hit:${hit} miss:${miss} ppn:${Hexadecimal(ppn(0))} perm:${perm(0)}\n") 216 217 val pmp_paddr = resp(i).bits.paddr(0) 218 219 (hit, miss, pmp_paddr, perm, g_perm) 220 } 221 222 def pmp_check(addr: UInt, size: UInt, cmd: UInt, idx: Int): Unit = { 223 pmp(idx).valid := resp(idx).valid 224 pmp(idx).bits.addr := addr 225 pmp(idx).bits.size := size 226 pmp(idx).bits.cmd := cmd 227 } 228 229 def perm_check(perm: TlbPermBundle, cmd: UInt, idx: Int, nDups: Int, g_perm: TlbPermBundle, hlvx: Bool, s2xlate: UInt) = { 230 // for timing optimization, pmp check is divided into dynamic and static 231 // dynamic: superpage (or full-connected reg entries) -> check pmp when translation done 232 // static: 4K pages (or sram entries) -> check pmp with pre-checked results 233 val hasS2xlate = s2xlate =/= noS2xlate 234 val onlyS1 = s2xlate === onlyStage1 235 val onlyS2 = s2xlate === onlyStage2 236 val af = perm.af || (hasS2xlate && g_perm.af) 237 238 // Stage 1 perm check 239 val pf = perm.pf 240 val ldUpdate = !perm.a && TlbCmd.isRead(cmd) && !TlbCmd.isAmo(cmd) // update A/D through exception 241 val stUpdate = (!perm.a || !perm.d) && (TlbCmd.isWrite(cmd) || TlbCmd.isAmo(cmd)) // update A/D through exception 242 val instrUpdate = !perm.a && TlbCmd.isExec(cmd) // update A/D through exception 243 val modeCheck = !(mode(idx) === ModeU && !perm.u || mode(idx) === ModeS && perm.u && (!sum(idx) || ifecth)) 244 val ldPermFail = !(modeCheck && Mux(hlvx, perm.x, perm.r || mxr(idx) && perm.x)) 245 val stPermFail = !(modeCheck && perm.w) 246 val instrPermFail = !(modeCheck && perm.x) 247 val ldPf = (ldPermFail || pf) && (TlbCmd.isRead(cmd) && !TlbCmd.isAmo(cmd)) 248 val stPf = (stPermFail || pf) && (TlbCmd.isWrite(cmd) || TlbCmd.isAmo(cmd)) 249 val instrPf = (instrPermFail || pf) && TlbCmd.isExec(cmd) 250 val s1_valid = portTranslateEnable(idx) && !onlyS2 251 252 // Stage 2 perm check 253 val gpf = g_perm.pf 254 val g_ldUpdate = !g_perm.a && TlbCmd.isRead(cmd) && !TlbCmd.isAmo(cmd) 255 val g_stUpdate = (!g_perm.a || !g_perm.d) && (TlbCmd.isWrite(cmd) || TlbCmd.isAmo(cmd)) 256 val g_instrUpdate = !g_perm.a && TlbCmd.isExec(cmd) 257 val g_ldPermFail = !Mux(hlvx, g_perm.x, (g_perm.r || io.csr.priv.mxr && g_perm.x)) 258 val g_stPermFail = !g_perm.w 259 val g_instrPermFail = !g_perm.x 260 val ldGpf = (g_ldPermFail || gpf) && (TlbCmd.isRead(cmd) && !TlbCmd.isAmo(cmd)) 261 val stGpf = (g_stPermFail || gpf) && (TlbCmd.isWrite(cmd) || TlbCmd.isAmo(cmd)) 262 val instrGpf = (g_instrPermFail || gpf) && TlbCmd.isExec(cmd) 263 val s2_valid = hasS2xlate && !onlyS1 && portTranslateEnable(idx) 264 265 val fault_valid = s1_valid || s2_valid 266 267 // when pf and gpf can't happens simultaneously 268 val hasPf = (ldPf || ldUpdate || stPf || stUpdate || instrPf || instrUpdate) && s1_valid && !af 269 resp(idx).bits.excp(nDups).pf.ld := (ldPf || ldUpdate) && s1_valid && !af 270 resp(idx).bits.excp(nDups).pf.st := (stPf || stUpdate) && s1_valid && !af 271 resp(idx).bits.excp(nDups).pf.instr := (instrPf || instrUpdate) && s1_valid && !af 272 // NOTE: pf need && with !af, page fault has higher priority than access fault 273 // but ptw may also have access fault, then af happens, the translation is wrong. 274 // In this case, pf has lower priority than af 275 276 resp(idx).bits.excp(nDups).gpf.ld := (ldGpf || g_ldUpdate) && s2_valid && !af && !hasPf 277 resp(idx).bits.excp(nDups).gpf.st := (stGpf || g_stUpdate) && s2_valid && !af && !hasPf 278 resp(idx).bits.excp(nDups).gpf.instr := (instrGpf || g_instrUpdate) && s2_valid && !af && !hasPf 279 280 resp(idx).bits.excp(nDups).af.ld := af && TlbCmd.isRead(cmd) && fault_valid 281 resp(idx).bits.excp(nDups).af.st := af && TlbCmd.isWrite(cmd) && fault_valid 282 resp(idx).bits.excp(nDups).af.instr := af && TlbCmd.isExec(cmd) && fault_valid 283 284 285 } 286 287 def handle_nonblock(idx: Int): Unit = { 288 io.requestor(idx).resp.valid := req_out_v(idx) 289 io.requestor(idx).req.ready := io.requestor(idx).resp.ready // should always be true 290 XSError(!io.requestor(idx).resp.ready, s"${q.name} port ${idx} is non-block, resp.ready must be true.B") 291 292 val req_need_gpa = hasGpf(idx) 293 val req_s2xlate = Wire(UInt(2.W)) 294 req_s2xlate := MuxCase(noS2xlate, Seq( 295 (!(virt_out(idx) || req_out(idx).hyperinst)) -> noS2xlate, 296 (csr.vsatp.mode =/= 0.U && csr.hgatp.mode =/= 0.U) -> allStage, 297 (csr.vsatp.mode === 0.U) -> onlyStage2, 298 (csr.hgatp.mode === 0.U || req_need_gpa) -> onlyStage1 299 )) 300 301 val ptw_just_back = ptw.resp.fire && req_s2xlate === ptw.resp.bits.s2xlate && ptw.resp.bits.hit(get_pn(req_out(idx).vaddr), io.csr.satp.asid, io.csr.vsatp.asid, io.csr.hgatp.asid, true, false) 302 // TODO: RegNext enable: ptw.resp.valid ? req.valid 303 val ptw_resp_bits_reg = RegEnable(ptw.resp.bits, ptw.resp.valid) 304 val ptw_already_back = GatedValidRegNext(ptw.resp.fire) && req_s2xlate === ptw_resp_bits_reg.s2xlate && ptw_resp_bits_reg.hit(get_pn(req_out(idx).vaddr), io.csr.satp.asid, io.csr.vsatp.asid, io.csr.hgatp.asid, allType = true) 305 io.ptw.req(idx).valid := req_out_v(idx) && missVec(idx) && !(ptw_just_back || ptw_already_back) // TODO: remove the regnext, timing 306 io.tlbreplay(idx) := req_out_v(idx) && missVec(idx) && (ptw_just_back || ptw_already_back) 307 when (io.requestor(idx).req_kill && GatedValidRegNext(io.requestor(idx).req.fire)) { 308 io.ptw.req(idx).valid := false.B 309 io.tlbreplay(idx) := true.B 310 } 311 io.ptw.req(idx).bits.vpn := get_pn(req_out(idx).vaddr) 312 io.ptw.req(idx).bits.s2xlate := req_s2xlate 313 io.ptw.req(idx).bits.getGpa := req_need_gpa && hitVec(idx) 314 io.ptw.req(idx).bits.memidx := req_out(idx).memidx 315 } 316 317 def handle_block(idx: Int): Unit = { 318 // three valid: 1.if exist a entry; 2.if sent to ptw; 3.unset resp.valid 319 io.requestor(idx).req.ready := !req_out_v(idx) || io.requestor(idx).resp.fire 320 // req_out_v for if there is a request, may long latency, fixme 321 322 // miss request entries 323 val req_need_gpa = hasGpf(idx) 324 val miss_req_vpn = get_pn(req_out(idx).vaddr) 325 val miss_req_memidx = req_out(idx).memidx 326 val miss_req_s2xlate = Wire(UInt(2.W)) 327 miss_req_s2xlate := MuxCase(noS2xlate, Seq( 328 (!(virt_out(idx) || req_out(idx).hyperinst)) -> noS2xlate, 329 (csr.vsatp.mode =/= 0.U && csr.hgatp.mode =/= 0.U) -> allStage, 330 (csr.vsatp.mode === 0.U) -> onlyStage2, 331 (csr.hgatp.mode === 0.U || req_need_gpa) -> onlyStage1 332 )) 333 val miss_req_s2xlate_reg = RegEnable(miss_req_s2xlate, io.ptw.req(idx).fire) 334 val hasS2xlate = miss_req_s2xlate_reg =/= noS2xlate 335 val onlyS2 = miss_req_s2xlate_reg === onlyStage2 336 val hit_s1 = io.ptw.resp.bits.s1.hit(miss_req_vpn, Mux(hasS2xlate, io.csr.vsatp.asid, io.csr.satp.asid), io.csr.hgatp.asid, allType = true, false, hasS2xlate) 337 val hit_s2 = io.ptw.resp.bits.s2.hit(miss_req_vpn, io.csr.hgatp.asid) 338 val hit = Mux(onlyS2, hit_s2, hit_s1) && io.ptw.resp.valid && miss_req_s2xlate_reg === io.ptw.resp.bits.s2xlate 339 340 val new_coming_valid = WireInit(false.B) 341 new_coming_valid := req_in(idx).fire && !req_in(idx).bits.kill && !flush_pipe(idx) 342 val new_coming = GatedValidRegNext(new_coming_valid) 343 val miss_wire = new_coming && missVec(idx) 344 val miss_v = ValidHoldBypass(miss_wire, resp(idx).fire, flush_pipe(idx)) 345 val miss_req_v = ValidHoldBypass(miss_wire || (miss_v && flush_mmu && !mmu_flush_pipe), 346 io.ptw.req(idx).fire || resp(idx).fire, flush_pipe(idx)) 347 348 // when ptw resp, check if hit, reset miss_v, resp to lsu/ifu 349 resp(idx).valid := req_out_v(idx) && !(miss_v && portTranslateEnable(idx)) 350 when (io.ptw.resp.fire && hit && req_out_v(idx) && portTranslateEnable(idx)) { 351 val stage1 = io.ptw.resp.bits.s1 352 val stage2 = io.ptw.resp.bits.s2 353 val s2xlate = io.ptw.resp.bits.s2xlate 354 resp(idx).valid := true.B 355 resp(idx).bits.miss := false.B 356 val s1_paddr = Cat(stage1.genPPN(get_pn(req_out(idx).vaddr)), get_off(req_out(idx).vaddr)) 357 val s2_paddr = Cat(stage2.genPPNS2(get_pn(req_out(idx).vaddr)), get_off(req_out(idx).vaddr)) 358 for (d <- 0 until nRespDups) { 359 resp(idx).bits.paddr(d) := Mux(s2xlate =/= noS2xlate, s2_paddr, s1_paddr) 360 resp(idx).bits.gpaddr(d) := s1_paddr 361 perm_check(stage1, req_out(idx).cmd, idx, d, stage2, req_out(idx).hlvx, s2xlate) 362 } 363 pmp_check(resp(idx).bits.paddr(0), req_out(idx).size, req_out(idx).cmd, idx) 364 365 // NOTE: the unfiltered req would be handled by Repeater 366 } 367 assert(RegNext(!resp(idx).valid || resp(idx).ready, true.B), "when tlb resp valid, ready should be true, must") 368 assert(RegNext(req_out_v(idx) || !(miss_v || miss_req_v), true.B), "when not req_out_v, should not set miss_v/miss_req_v") 369 370 val ptw_req = io.ptw.req(idx) 371 ptw_req.valid := miss_req_v 372 ptw_req.bits.vpn := miss_req_vpn 373 ptw_req.bits.s2xlate := miss_req_s2xlate 374 ptw_req.bits.getGpa := req_need_gpa && hitVec(idx) 375 ptw_req.bits.memidx := miss_req_memidx 376 377 io.tlbreplay(idx) := false.B 378 379 // NOTE: when flush pipe, tlb should abandon last req 380 // however, some outside modules like icache, dont care flushPipe, and still waiting for tlb resp 381 // just resp valid and raise page fault to go through. The pipe(ifu) will abandon it. 382 if (!q.outsideRecvFlush) { 383 when (req_out_v(idx) && flush_pipe(idx) && portTranslateEnable(idx)) { 384 resp(idx).valid := true.B 385 for (d <- 0 until nRespDups) { 386 resp(idx).bits.excp(d).pf.ld := true.B // sfence happened, pf for not to use this addr 387 resp(idx).bits.excp(d).pf.st := true.B 388 resp(idx).bits.excp(d).pf.instr := true.B 389 } 390 } 391 } 392 } 393 394 // when ptw resp, tlb at refill_idx maybe set to miss by force. 395 // Bypass ptw resp to check. 396 def ptw_resp_bypass(vpn: UInt, s2xlate: UInt) = { 397 // TODO: RegNext enable: ptw.resp.valid 398 val hasS2xlate = s2xlate =/= noS2xlate 399 val onlyS2 = s2xlate === onlyStage2 400 val onlyS1 = s2xlate === onlyStage1 401 val s2xlate_hit = s2xlate === ptw.resp.bits.s2xlate 402 val resp_hit = ptw.resp.bits.hit(vpn, io.csr.satp.asid, io.csr.vsatp.asid, io.csr.hgatp.asid, true, false) 403 val p_hit = GatedValidRegNext(resp_hit && io.ptw.resp.fire && s2xlate_hit) 404 val ppn_s1 = ptw.resp.bits.s1.genPPN(vpn) 405 val gvpn = Mux(onlyS2, vpn, ppn_s1) 406 val ppn_s2 = ptw.resp.bits.s2.genPPNS2(gvpn) 407 val p_ppn = RegEnable(Mux(hasS2xlate, ppn_s2, ppn_s1), io.ptw.resp.fire) 408 val p_perm = RegEnable(ptwresp_to_tlbperm(ptw.resp.bits.s1), io.ptw.resp.fire) 409 val p_gvpn = RegEnable(Mux(onlyS2, ptw.resp.bits.s2.entry.tag, ppn_s1), io.ptw.resp.fire) 410 val p_g_perm = RegEnable(hptwresp_to_tlbperm(ptw.resp.bits.s2), io.ptw.resp.fire) 411 val p_s2xlate = RegEnable(ptw.resp.bits.s2xlate, io.ptw.resp.fire) 412 (p_hit, p_ppn, p_perm, p_gvpn, p_g_perm, p_s2xlate) 413 } 414 415 // assert 416 for(i <- 0 until Width) { 417 TimeOutAssert(req_out_v(i) && !resp(i).valid, timeOutThreshold, s"{q.name} port{i} long time no resp valid.") 418 } 419 420 // perf event 421 val result_ok = req_in.map(a => GatedValidRegNext(a.fire)) 422 val perfEvents = 423 Seq( 424 ("access", PopCount((0 until Width).map{i => if (Block(i)) io.requestor(i).req.fire else portTranslateEnable(i) && result_ok(i) })), 425 ("miss ", PopCount((0 until Width).map{i => if (Block(i)) portTranslateEnable(i) && result_ok(i) && missVec(i) else ptw.req(i).fire })), 426 ) 427 generatePerfEvent() 428 429 // perf log 430 for (i <- 0 until Width) { 431 if (Block(i)) { 432 XSPerfAccumulate(s"access${i}",result_ok(i) && portTranslateEnable(i)) 433 XSPerfAccumulate(s"miss${i}", result_ok(i) && missVec(i)) 434 } else { 435 XSPerfAccumulate("first_access" + Integer.toString(i, 10), result_ok(i) && portTranslateEnable(i) && RegEnable(req(i).bits.debug.isFirstIssue, req(i).valid)) 436 XSPerfAccumulate("access" + Integer.toString(i, 10), result_ok(i) && portTranslateEnable(i)) 437 XSPerfAccumulate("first_miss" + Integer.toString(i, 10), result_ok(i) && portTranslateEnable(i) && missVec(i) && RegEnable(req(i).bits.debug.isFirstIssue, req(i).valid)) 438 XSPerfAccumulate("miss" + Integer.toString(i, 10), result_ok(i) && portTranslateEnable(i) && missVec(i)) 439 } 440 } 441 XSPerfAccumulate("ptw_resp_count", ptw.resp.fire) 442 XSPerfAccumulate("ptw_resp_pf_count", ptw.resp.fire && ptw.resp.bits.s1.pf) 443 444 // Log 445 for(i <- 0 until Width) { 446 XSDebug(req(i).valid, p"req(${i.U}): (${req(i).valid} ${req(i).ready}) ${req(i).bits}\n") 447 XSDebug(resp(i).valid, p"resp(${i.U}): (${resp(i).valid} ${resp(i).ready}) ${resp(i).bits}\n") 448 } 449 450 XSDebug(io.sfence.valid, p"Sfence: ${io.sfence}\n") 451 XSDebug(ParallelOR(req_out_v) || ptw.resp.valid, p"vmEnable:${vmEnable} hit:${Binary(VecInit(hitVec).asUInt)} miss:${Binary(VecInit(missVec).asUInt)}\n") 452 for (i <- ptw.req.indices) { 453 XSDebug(ptw.req(i).fire, p"L2TLB req:${ptw.req(i).bits}\n") 454 } 455 XSDebug(ptw.resp.valid, p"L2TLB resp:${ptw.resp.bits} (v:${ptw.resp.valid}r:${ptw.resp.ready}) \n") 456 457 println(s"${q.name}: page: ${q.NWays} ${q.Associative} ${q.Replacer.get}") 458 459 if (env.EnableDifftest) { 460 for (i <- 0 until Width) { 461 val pf = io.requestor(i).resp.bits.excp(0).pf.instr || io.requestor(i).resp.bits.excp(0).pf.st || io.requestor(i).resp.bits.excp(0).pf.ld 462 val gpf = io.requestor(i).resp.bits.excp(0).gpf.instr || io.requestor(i).resp.bits.excp(0).gpf.st || io.requestor(i).resp.bits.excp(0).gpf.ld 463 val af = io.requestor(i).resp.bits.excp(0).af.instr || io.requestor(i).resp.bits.excp(0).af.st || io.requestor(i).resp.bits.excp(0).af.ld 464 val difftest = DifftestModule(new DiffL1TLBEvent) 465 difftest.coreid := io.hartId 466 difftest.valid := RegNext(io.requestor(i).req.fire) && !io.requestor(i).req_kill && io.requestor(i).resp.fire && !io.requestor(i).resp.bits.miss && !pf && !af && !gpf && portTranslateEnable(i) 467 if (!Seq("itlb", "ldtlb", "sttlb").contains(q.name)) { 468 difftest.valid := false.B 469 } 470 difftest.index := TLBDiffId(p(XSCoreParamsKey).HartId).U 471 difftest.vpn := RegEnable(get_pn(req_in(i).bits.vaddr), req_in(i).valid) 472 difftest.ppn := get_pn(io.requestor(i).resp.bits.paddr(0)) 473 difftest.satp := Cat(io.csr.satp.mode, io.csr.satp.asid, io.csr.satp.ppn) 474 difftest.vsatp := Cat(io.csr.vsatp.mode, io.csr.vsatp.asid, io.csr.vsatp.ppn) 475 difftest.hgatp := Cat(io.csr.hgatp.mode, io.csr.hgatp.asid, io.csr.hgatp.ppn) 476 val req_need_gpa = gpf 477 val req_s2xlate = Wire(UInt(2.W)) 478 req_s2xlate := MuxCase(noS2xlate, Seq( 479 (!RegNext(virt_in || req_in(i).bits.hyperinst)) -> noS2xlate, 480 (vsatp.mode =/= 0.U && hgatp.mode =/= 0.U) -> allStage, 481 (vsatp.mode === 0.U) -> onlyStage2, 482 (hgatp.mode === 0.U || req_need_gpa) -> onlyStage1 483 )) 484 difftest.s2xlate := req_s2xlate 485 } 486 } 487} 488 489object TLBDiffId { 490 var i: Int = 0 491 var lastHartId: Int = -1 492 def apply(hartId: Int): Int = { 493 if (lastHartId != hartId) { 494 i = 0 495 lastHartId = hartId 496 } 497 i += 1 498 i - 1 499 } 500} 501 502class TLBNonBlock(Width: Int, nRespDups: Int = 1, q: TLBParameters)(implicit p: Parameters) extends TLB(Width, nRespDups, Seq.fill(Width)(false), q) 503class TLBBLock(Width: Int, nRespDups: Int = 1, q: TLBParameters)(implicit p: Parameters) extends TLB(Width, nRespDups, Seq.fill(Width)(true), q) 504 505class TlbReplace(Width: Int, q: TLBParameters)(implicit p: Parameters) extends TlbModule { 506 val io = IO(new TlbReplaceIO(Width, q)) 507 508 if (q.Associative == "fa") { 509 val re = ReplacementPolicy.fromString(q.Replacer, q.NWays) 510 re.access(io.page.access.map(_.touch_ways)) 511 io.page.refillIdx := re.way 512 } else { // set-acco && plru 513 val re = ReplacementPolicy.fromString(q.Replacer, q.NSets, q.NWays) 514 re.access(io.page.access.map(_.sets), io.page.access.map(_.touch_ways)) 515 io.page.refillIdx := { if (q.NWays == 1) 0.U else re.way(io.page.chosen_set) } 516 } 517} 518