1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15* 16* 17* Acknowledgement 18* 19* This implementation is inspired by several key papers: 20* [1] Binh Pham, Viswanathan Vaidyanathan, Aamer Jaleel, and Abhishek Bhattacharjee. "[Colt: Coalesced large-reach 21* tlbs.](https://doi.org/10.1109/MICRO.2012.32)" 45th Annual IEEE/ACM International Symposium on Microarchitecture 22* (MICRO). 2012. 23***************************************************************************************/ 24 25package xiangshan.cache.mmu 26 27import org.chipsalliance.cde.config.Parameters 28import chisel3._ 29import chisel3.util._ 30import difftest._ 31import freechips.rocketchip.util.SRAMAnnotation 32import xiangshan._ 33import utils._ 34import utility._ 35import xiangshan.backend.fu.{PMPChecker, PMPReqBundle, PMPConfig => XSPMPConfig} 36import xiangshan.backend.rob.RobPtr 37import xiangshan.backend.fu.util.HasCSRConst 38import freechips.rocketchip.rocket.PMPConfig 39 40/** TLB module 41 * support block request and non-block request io at the same time 42 * return paddr at next cycle, then go for pmp/pma check 43 * @param Width: The number of requestors 44 * @param Block: Blocked or not for each requestor ports 45 * @param q: TLB Parameters, like entry number, each TLB has its own parameters 46 * @param p: XiangShan Paramemters, like XLEN 47 */ 48 49class TLB(Width: Int, nRespDups: Int = 1, Block: Seq[Boolean], q: TLBParameters)(implicit p: Parameters) extends TlbModule 50 with HasCSRConst 51 with HasPerfEvents 52{ 53 val io = IO(new TlbIO(Width, nRespDups, q)) 54 55 val req = io.requestor.map(_.req) 56 val resp = io.requestor.map(_.resp) 57 val ptw = io.ptw 58 val pmp = io.pmp 59 val refill_to_mem = io.refill_to_mem 60 61 /** Sfence.vma & Svinval 62 * Sfence.vma will 1. flush old entries 2. flush inflight 3. flush pipe 63 * Svinval will 1. flush old entries 2. flush inflight 64 * So, Svinval will not flush pipe, which means 65 * it should not drop reqs from pipe and should return right resp 66 */ 67 val sfence = DelayN(io.sfence, q.fenceDelay) 68 val csr = io.csr 69 val satp = DelayN(io.csr.satp, q.fenceDelay) 70 val vsatp = DelayN(io.csr.vsatp, q.fenceDelay) 71 val hgatp = DelayN(io.csr.hgatp, q.fenceDelay) 72 val mPBMTE = DelayN(io.csr.mPBMTE, q.fenceDelay) 73 val hPBMTE = DelayN(io.csr.hPBMTE, q.fenceDelay) 74 75 val flush_mmu = DelayN(sfence.valid || csr.satp.changed || csr.vsatp.changed || csr.hgatp.changed, q.fenceDelay) 76 val mmu_flush_pipe = DelayN(sfence.valid && sfence.bits.flushPipe, q.fenceDelay) // for svinval, won't flush pipe 77 val flush_pipe = io.flushPipe 78 val redirect = io.redirect 79 val req_in = req 80 val req_out = req.map(a => RegEnable(a.bits, a.fire)) 81 val req_out_v = (0 until Width).map(i => ValidHold(req_in(i).fire && !req_in(i).bits.kill, resp(i).fire, flush_pipe(i))) 82 83 val isHyperInst = (0 until Width).map(i => req_out_v(i) && req_out(i).hyperinst) 84 85 // ATTENTION: csr and flush from backend are delayed. csr should not be later than flush. 86 // because, csr will influence tlb behavior. 87 val ifecth = if (q.fetchi) true.B else false.B 88 val mode_tmp = if (q.useDmode) csr.priv.dmode else csr.priv.imode 89 val mode = (0 until Width).map(i => Mux(isHyperInst(i), csr.priv.spvp, mode_tmp)) 90 val virt_in = csr.priv.virt 91 val virt_out = req.map(a => RegEnable(csr.priv.virt, a.fire)) 92 val sum = (0 until Width).map(i => Mux(virt_out(i) || isHyperInst(i), io.csr.priv.vsum, io.csr.priv.sum)) 93 val mxr = (0 until Width).map(i => Mux(virt_out(i) || isHyperInst(i), io.csr.priv.vmxr || io.csr.priv.mxr, io.csr.priv.mxr)) 94 val req_in_s2xlate = (0 until Width).map(i => MuxCase(noS2xlate, Seq( 95 (!(virt_in || req_in(i).bits.hyperinst)) -> noS2xlate, 96 (csr.vsatp.mode =/= 0.U && csr.hgatp.mode =/= 0.U) -> allStage, 97 (csr.vsatp.mode === 0.U) -> onlyStage2, 98 (csr.hgatp.mode === 0.U) -> onlyStage1 99 ))) 100 val req_out_s2xlate = (0 until Width).map(i => MuxCase(noS2xlate, Seq( 101 (!(virt_out(i) || isHyperInst(i))) -> noS2xlate, 102 (csr.vsatp.mode =/= 0.U && csr.hgatp.mode =/= 0.U) -> allStage, 103 (csr.vsatp.mode === 0.U) -> onlyStage2, 104 (csr.hgatp.mode === 0.U) -> onlyStage1 105 ))) 106 val need_gpa = RegInit(false.B) 107 val need_gpa_robidx = Reg(new RobPtr) 108 val need_gpa_vpn = Reg(UInt(vpnLen.W)) 109 val resp_gpa_gvpn = Reg(UInt(ptePPNLen.W)) 110 val resp_gpa_refill = RegInit(false.B) 111 val resp_s1_level = RegInit(0.U(log2Up(Level + 1).W)) 112 val resp_s1_isLeaf = RegInit(false.B) 113 val resp_s1_isFakePte = RegInit(false.B) 114 val hasGpf = Wire(Vec(Width, Bool())) 115 116 val Sv39Enable = satp.mode === 8.U 117 val Sv48Enable = satp.mode === 9.U 118 val Sv39x4Enable = vsatp.mode === 8.U || hgatp.mode === 8.U 119 val Sv48x4Enable = vsatp.mode === 9.U || hgatp.mode === 9.U 120 val vmEnable = (0 until Width).map(i => !(isHyperInst(i) || virt_out(i)) && ( 121 if (EnbaleTlbDebug) (Sv39Enable || Sv48Enable) 122 else (Sv39Enable || Sv48Enable) && (mode(i) < ModeM)) 123 ) 124 val s2xlateEnable = (0 until Width).map(i => (isHyperInst(i) || virt_out(i)) && (Sv39x4Enable || Sv48x4Enable) && (mode(i) < ModeM)) 125 val portTranslateEnable = (0 until Width).map(i => (vmEnable(i) || s2xlateEnable(i)) && RegEnable(!req(i).bits.no_translate, req(i).valid)) 126 127 // pre fault: check fault before real do translate 128 val prepf = WireInit(VecInit(Seq.fill(Width)(false.B))) 129 val pregpf = WireInit(VecInit(Seq.fill(Width)(false.B))) 130 val preaf = WireInit(VecInit(Seq.fill(Width)(false.B))) 131 val prevmEnable = (0 until Width).map(i => !(virt_in || req_in(i).bits.hyperinst) && ( 132 if (EnbaleTlbDebug) (Sv39Enable || Sv48Enable) 133 else (Sv39Enable || Sv48Enable) && (mode(i) < ModeM)) 134 ) 135 val pres2xlateEnable = (0 until Width).map(i => (virt_in || req_in(i).bits.hyperinst) && (Sv39x4Enable || Sv48x4Enable) && (mode(i) < ModeM)) 136 (0 until Width).foreach{i => 137 val pf48 = SignExt(req(i).bits.fullva(47, 0), XLEN) =/= req(i).bits.fullva 138 val pf39 = SignExt(req(i).bits.fullva(38, 0), XLEN) =/= req(i).bits.fullva 139 val gpf48 = req(i).bits.fullva(XLEN - 1, 48 + 2) =/= 0.U 140 val gpf39 = req(i).bits.fullva(XLEN - 1, 39 + 2) =/= 0.U 141 val af = req(i).bits.fullva(XLEN - 1, PAddrBits) =/= 0.U 142 when (req(i).valid && req(i).bits.checkfullva) { 143 when (prevmEnable(i) || pres2xlateEnable(i)) { 144 when (req_in_s2xlate(i) === onlyStage2) { 145 when (Sv48x4Enable) { 146 pregpf(i) := gpf48 147 } .elsewhen (Sv39x4Enable) { 148 pregpf(i) := gpf39 149 } 150 } .otherwise { 151 when (Sv48Enable) { 152 prepf(i) := pf48 153 } .elsewhen (Sv39Enable) { 154 prepf(i) := pf39 155 } 156 } 157 } .otherwise { 158 preaf(i) := af 159 } 160 } 161 } 162 163 val refill = ptw.resp.fire && !(ptw.resp.bits.getGpa) && !flush_mmu 164 refill_to_mem := DontCare 165 val entries = Module(new TlbStorageWrapper(Width, q, nRespDups)) 166 entries.io.base_connect(sfence, csr, satp) 167 if (q.outReplace) { io.replace <> entries.io.replace } 168 for (i <- 0 until Width) { 169 entries.io.r_req_apply(io.requestor(i).req.valid, get_pn(req_in(i).bits.vaddr), i, req_in_s2xlate(i)) 170 entries.io.w_apply(refill, ptw.resp.bits) 171 // TODO: RegNext enable:req.valid 172 resp(i).bits.debug.isFirstIssue := RegEnable(req(i).bits.debug.isFirstIssue, req(i).valid) 173 resp(i).bits.debug.robIdx := RegEnable(req(i).bits.debug.robIdx, req(i).valid) 174 } 175 176 // read TLB, get hit/miss, paddr, perm bits 177 val readResult = (0 until Width).map(TLBRead(_)) 178 val hitVec = readResult.map(_._1) 179 val missVec = readResult.map(_._2) 180 val pmp_addr = readResult.map(_._3) 181 val perm = readResult.map(_._4) 182 val g_perm = readResult.map(_._5) 183 val pbmt = readResult.map(_._6) 184 val g_pbmt = readResult.map(_._7) 185 // check pmp use paddr (for timing optization, use pmp_addr here) 186 // check permisson 187 (0 until Width).foreach{i => 188 val noTranslateReg = RegNext(req(i).bits.no_translate) 189 val addr = Mux(noTranslateReg, req(i).bits.pmp_addr, pmp_addr(i)) 190 pmp_check(addr, req_out(i).size, req_out(i).cmd, noTranslateReg, i) 191 for (d <- 0 until nRespDups) { 192 pbmt_check(i, d, pbmt(i)(d), g_pbmt(i)(d), req_out_s2xlate(i)) 193 perm_check(perm(i)(d), req_out(i).cmd, i, d, g_perm(i)(d), req_out(i).hlvx, req_out_s2xlate(i), prepf(i), pregpf(i), preaf(i)) 194 } 195 hasGpf(i) := hitVec(i) && (resp(i).bits.excp(0).gpf.ld || resp(i).bits.excp(0).gpf.st || resp(i).bits.excp(0).gpf.instr) 196 } 197 198 // handle block or non-block io 199 // for non-block io, just return the above result, send miss to ptw 200 // for block io, hold the request, send miss to ptw, 201 // when ptw back, return the result 202 (0 until Width) foreach {i => 203 if (Block(i)) handle_block(i) 204 else handle_nonblock(i) 205 } 206 io.ptw.resp.ready := true.B 207 208 /************************ main body above | method/log/perf below ****************************/ 209 def TLBRead(i: Int) = { 210 val (e_hit, e_ppn, e_perm, e_g_perm, e_s2xlate, e_pbmt, e_g_pbmt) = entries.io.r_resp_apply(i) 211 val (p_hit, p_ppn, p_pbmt, p_perm, p_gvpn, p_g_pbmt, p_g_perm, p_s2xlate, p_s1_level, p_s1_isLeaf, p_s1_isFakePte) = ptw_resp_bypass(get_pn(req_in(i).bits.vaddr), req_in_s2xlate(i)) 212 val enable = portTranslateEnable(i) 213 val isOnlys2xlate = req_out_s2xlate(i) === onlyStage2 214 val need_gpa_vpn_hit = need_gpa_vpn === get_pn(req_out(i).vaddr) 215 val isitlb = TlbCmd.isExec(req_out(i).cmd) 216 val isPrefetch = req_out(i).isPrefetch 217 val currentRedirect = req_out(i).debug.robIdx.needFlush(redirect) 218 val lastCycleRedirect = req_out(i).debug.robIdx.needFlush(RegNext(redirect)) 219 220 when (!isitlb && need_gpa_robidx.needFlush(redirect) || isitlb && flush_pipe(i)){ 221 need_gpa := false.B 222 resp_gpa_refill := false.B 223 need_gpa_vpn := 0.U 224 }.elsewhen (req_out_v(i) && !p_hit && !(resp_gpa_refill && need_gpa_vpn_hit) && !isOnlys2xlate && hasGpf(i) && need_gpa === false.B && !io.requestor(i).req_kill && !isPrefetch && !currentRedirect && !lastCycleRedirect) { 225 need_gpa := true.B 226 need_gpa_vpn := get_pn(req_out(i).vaddr) 227 resp_gpa_refill := false.B 228 need_gpa_robidx := req_out(i).debug.robIdx 229 }.elsewhen (ptw.resp.fire && need_gpa && need_gpa_vpn === ptw.resp.bits.getVpn(need_gpa_vpn)) { 230 resp_gpa_gvpn := Mux(ptw.resp.bits.s2xlate === onlyStage2, ptw.resp.bits.s2.entry.tag, ptw.resp.bits.s1.genGVPN(need_gpa_vpn)) 231 resp_s1_level := ptw.resp.bits.s1.entry.level.get 232 resp_s1_isLeaf := ptw.resp.bits.s1.isLeaf() 233 resp_s1_isFakePte := ptw.resp.bits.s1.isFakePte() 234 resp_gpa_refill := true.B 235 } 236 237 when (req_out_v(i) && hasGpf(i) && resp_gpa_refill && need_gpa_vpn_hit){ 238 need_gpa := false.B 239 } 240 241 val hit = e_hit || p_hit 242 val miss = (!hit && enable) || hasGpf(i) && !p_hit && !(resp_gpa_refill && need_gpa_vpn_hit) && !isOnlys2xlate && !isPrefetch && !lastCycleRedirect 243 hit.suggestName(s"hit_read_${i}") 244 miss.suggestName(s"miss_read_${i}") 245 246 val vaddr = SignExt(req_out(i).vaddr, PAddrBits) 247 resp(i).bits.miss := miss 248 resp(i).bits.ptwBack := ptw.resp.fire 249 resp(i).bits.memidx := RegEnable(req_in(i).bits.memidx, req_in(i).valid) 250 resp(i).bits.fastMiss := !hit && enable 251 252 val ppn = WireInit(VecInit(Seq.fill(nRespDups)(0.U(ppnLen.W)))) 253 val pbmt = WireInit(VecInit(Seq.fill(nRespDups)(0.U(ptePbmtLen.W)))) 254 val perm = WireInit(VecInit(Seq.fill(nRespDups)(0.U.asTypeOf(new TlbPermBundle)))) 255 val gvpn = WireInit(VecInit(Seq.fill(nRespDups)(0.U(ptePPNLen.W)))) 256 val level = WireInit(VecInit(Seq.fill(nRespDups)(0.U(log2Up(Level + 1).W)))) 257 val isLeaf = WireInit(VecInit(Seq.fill(nRespDups)(false.B))) 258 val isFakePte = WireInit(VecInit(Seq.fill(nRespDups)(false.B))) 259 val g_pbmt = WireInit(VecInit(Seq.fill(nRespDups)(0.U(ptePbmtLen.W)))) 260 val g_perm = WireInit(VecInit(Seq.fill(nRespDups)(0.U.asTypeOf(new TlbPermBundle)))) 261 val r_s2xlate = WireInit(VecInit(Seq.fill(nRespDups)(0.U(2.W)))) 262 for (d <- 0 until nRespDups) { 263 ppn(d) := Mux(p_hit, p_ppn, e_ppn(d)) 264 pbmt(d) := Mux(p_hit, p_pbmt, e_pbmt(d)) 265 perm(d) := Mux(p_hit, p_perm, e_perm(d)) 266 gvpn(d) := Mux(p_hit, p_gvpn, resp_gpa_gvpn) 267 level(d) := Mux(p_hit, p_s1_level, resp_s1_level) 268 isLeaf(d) := Mux(p_hit, p_s1_isLeaf, resp_s1_isLeaf) 269 isFakePte(d) := Mux(p_hit, p_s1_isFakePte, resp_s1_isFakePte) 270 g_pbmt(d) := Mux(p_hit, p_g_pbmt, e_g_pbmt(d)) 271 g_perm(d) := Mux(p_hit, p_g_perm, e_g_perm(d)) 272 r_s2xlate(d) := Mux(p_hit, p_s2xlate, e_s2xlate(d)) 273 val paddr = Cat(ppn(d), get_off(req_out(i).vaddr)) 274 val vpn_idx = Mux1H(Seq( 275 (isFakePte(d) && vsatp.mode === Sv39) -> 2.U, 276 (isFakePte(d) && vsatp.mode === Sv48) -> 3.U, 277 (!isFakePte(d)) -> (level(d) - 1.U), 278 )) 279 // We use `fullva` here when `isLeaf`, in order to cope with the situation of an unaligned load/store cross page 280 // for example, a `ld` instruction on address 0x81000ffb will be splited into two loads 281 // 1. ld 0x81000ff8. vaddr = 0x81000ff8, fullva = 0x80000ffb 282 // 2. ld 0x81001000. vaddr = 0x81001000, fullva = 0x80000ffb 283 // When load 1 trigger a guest page fault, we should use offset of fullva when generate gpaddr 284 // and when load 2 trigger a guest page fault, we should just use offset of vaddr(all zero). 285 // Also, when onlyS2, if crosspage, gpaddr = vaddr(start address of a new page), else gpaddr = fullva(original vaddr) 286 // By the way, frontend handles the cross page instruction fetch by itself, so TLB doesn't need to do anything extra. 287 // Also, the fullva of iTLB is not used and always zero. crossPageVaddr should never use fullva in iTLB. 288 val crossPageVaddr = Mux(isitlb || req_out(i).fullva(12) =/= vaddr(12), vaddr, req_out(i).fullva) 289 val gpaddr_offset = Mux(isLeaf(d), get_off(crossPageVaddr), Cat(getVpnn(get_pn(crossPageVaddr), vpn_idx), 0.U(log2Up(XLEN/8).W))) 290 val gpaddr = Cat(gvpn(d), gpaddr_offset) 291 resp(i).bits.paddr(d) := Mux(enable, paddr, vaddr) 292 resp(i).bits.gpaddr(d) := Mux(r_s2xlate(d) === onlyStage2, crossPageVaddr, gpaddr) 293 } 294 295 XSDebug(req_out_v(i), p"(${i.U}) hit:${hit} miss:${miss} ppn:${Hexadecimal(ppn(0))} perm:${perm(0)}\n") 296 297 val pmp_paddr = resp(i).bits.paddr(0) 298 299 (hit, miss, pmp_paddr, perm, g_perm, pbmt, g_pbmt) 300 } 301 302 def getVpnn(vpn: UInt, idx: UInt): UInt = { 303 MuxLookup(idx, 0.U)(Seq( 304 0.U -> vpn(vpnnLen - 1, 0), 305 1.U -> vpn(vpnnLen * 2 - 1, vpnnLen), 306 2.U -> vpn(vpnnLen * 3 - 1, vpnnLen * 2), 307 3.U -> vpn(vpnnLen * 4 - 1, vpnnLen * 3)) 308 ) 309 } 310 311 def pmp_check(addr: UInt, size: UInt, cmd: UInt, noTranslate: Bool, idx: Int): Unit = { 312 pmp(idx).valid := resp(idx).valid || noTranslate 313 pmp(idx).bits.addr := addr 314 pmp(idx).bits.size := size 315 pmp(idx).bits.cmd := cmd 316 } 317 318 def pbmt_check(idx: Int, d: Int, pbmt: UInt, g_pbmt: UInt, s2xlate: UInt):Unit = { 319 val onlyS1 = s2xlate === onlyStage1 || s2xlate === noS2xlate 320 val pbmtRes = pbmt 321 val gpbmtRes = g_pbmt 322 val res = MuxLookup(s2xlate, 0.U)(Seq( 323 onlyStage1 -> pbmtRes, 324 onlyStage2 -> gpbmtRes, 325 allStage -> Mux(pbmtRes =/= 0.U, pbmtRes, gpbmtRes), 326 noS2xlate -> pbmtRes 327 )) 328 resp(idx).bits.pbmt(d) := Mux(portTranslateEnable(idx), res, 0.U) 329 } 330 331 // for timing optimization, pmp check is divided into dynamic and static 332 def perm_check(perm: TlbPermBundle, cmd: UInt, idx: Int, nDups: Int, g_perm: TlbPermBundle, hlvx: Bool, s2xlate: UInt, prepf: Bool = false.B, pregpf: Bool = false.B, preaf: Bool = false.B) = { 333 // dynamic: superpage (or full-connected reg entries) -> check pmp when translation done 334 // static: 4K pages (or sram entries) -> check pmp with pre-checked results 335 val hasS2xlate = s2xlate =/= noS2xlate 336 val onlyS1 = s2xlate === onlyStage1 337 val onlyS2 = s2xlate === onlyStage2 338 val af = perm.af || (hasS2xlate && g_perm.af) 339 340 // Stage 1 perm check 341 val pf = perm.pf 342 val isLd = TlbCmd.isRead(cmd) && !TlbCmd.isAmo(cmd) 343 val isSt = TlbCmd.isWrite(cmd) || TlbCmd.isAmo(cmd) 344 val isInst = TlbCmd.isExec(cmd) 345 val ldUpdate = !perm.a && isLd // update A/D through exception 346 val stUpdate = (!perm.a || !perm.d) && isSt // update A/D through exception 347 val instrUpdate = !perm.a && isInst // update A/D through exception 348 val modeCheck = !(mode(idx) === ModeU && !perm.u || mode(idx) === ModeS && perm.u && (!sum(idx) || ifecth)) 349 val ldPermFail = !(modeCheck && Mux(hlvx, perm.x, perm.r || mxr(idx) && perm.x)) 350 val stPermFail = !(modeCheck && perm.w) 351 val instrPermFail = !(modeCheck && perm.x) 352 val ldPf = (ldPermFail || pf) && isLd 353 val stPf = (stPermFail || pf) && isSt 354 val instrPf = (instrPermFail || pf) && isInst 355 val isFakePte = !perm.v && !perm.pf && !perm.af && !onlyS2 356 val isNonLeaf = !(perm.r || perm.w || perm.x) && perm.v && !perm.pf && !perm.af 357 val s1_valid = portTranslateEnable(idx) && !onlyS2 358 359 // Stage 2 perm check 360 val gpf = g_perm.pf 361 val g_ldUpdate = !g_perm.a && isLd 362 val g_stUpdate = (!g_perm.a || !g_perm.d) && isSt 363 val g_instrUpdate = !g_perm.a && isInst 364 val g_ldPermFail = !Mux(hlvx, g_perm.x, (g_perm.r || io.csr.priv.mxr && g_perm.x)) 365 val g_stPermFail = !g_perm.w 366 val g_instrPermFail = !g_perm.x 367 val ldGpf = (g_ldPermFail || gpf) && isLd 368 val stGpf = (g_stPermFail || gpf) && isSt 369 val instrGpf = (g_instrPermFail || gpf) && isInst 370 val s2_valid = portTranslateEnable(idx) && hasS2xlate && !onlyS1 371 372 val fault_valid = s1_valid || s2_valid 373 374 // when pf and gpf can't happens simultaneously 375 val hasPf = (ldPf || ldUpdate || stPf || stUpdate || instrPf || instrUpdate) && s1_valid && !af && !isFakePte && !isNonLeaf 376 // Only lsu need check related to high address truncation 377 when (RegNext(prepf || pregpf || preaf)) { 378 resp(idx).bits.isForVSnonLeafPTE := false.B 379 resp(idx).bits.excp(nDups).pf.ld := RegNext(prepf) && isLd 380 resp(idx).bits.excp(nDups).pf.st := RegNext(prepf) && isSt 381 resp(idx).bits.excp(nDups).pf.instr := false.B 382 383 resp(idx).bits.excp(nDups).gpf.ld := RegNext(pregpf) && isLd 384 resp(idx).bits.excp(nDups).gpf.st := RegNext(pregpf) && isSt 385 resp(idx).bits.excp(nDups).gpf.instr := false.B 386 387 resp(idx).bits.excp(nDups).af.ld := RegNext(preaf) && TlbCmd.isRead(cmd) 388 resp(idx).bits.excp(nDups).af.st := RegNext(preaf) && TlbCmd.isWrite(cmd) 389 resp(idx).bits.excp(nDups).af.instr := false.B 390 391 resp(idx).bits.excp(nDups).vaNeedExt := false.B 392 // overwrite miss & gpaddr when exception related to high address truncation happens 393 resp(idx).bits.miss := false.B 394 resp(idx).bits.gpaddr(nDups) := RegNext(req(idx).bits.fullva) 395 } .otherwise { 396 // isForVSnonLeafPTE is used only when gpf happens and it caused by a G-stage translation which supports VS-stage translation 397 // it will be sent to CSR in order to modify the m/htinst. 398 // Ref: The RISC-V Instruction Set Manual: Volume II: Privileged Architecture - 19.6.3. Transformed Instruction or Pseudoinstruction for mtinst or htinst 399 val isForVSnonLeafPTE = isNonLeaf || isFakePte 400 resp(idx).bits.isForVSnonLeafPTE := isForVSnonLeafPTE 401 resp(idx).bits.excp(nDups).pf.ld := (ldPf || ldUpdate) && s1_valid && !af && !isFakePte && !isNonLeaf 402 resp(idx).bits.excp(nDups).pf.st := (stPf || stUpdate) && s1_valid && !af && !isFakePte && !isNonLeaf 403 resp(idx).bits.excp(nDups).pf.instr := (instrPf || instrUpdate) && s1_valid && !af && !isFakePte && !isNonLeaf 404 // NOTE: pf need && with !af, page fault has higher priority than access fault 405 // but ptw may also have access fault, then af happens, the translation is wrong. 406 // In this case, pf has lower priority than af 407 408 resp(idx).bits.excp(nDups).gpf.ld := (ldGpf || g_ldUpdate) && s2_valid && !af && !hasPf 409 resp(idx).bits.excp(nDups).gpf.st := (stGpf || g_stUpdate) && s2_valid && !af && !hasPf 410 resp(idx).bits.excp(nDups).gpf.instr := (instrGpf || g_instrUpdate) && s2_valid && !af && !hasPf 411 412 resp(idx).bits.excp(nDups).af.ld := af && TlbCmd.isRead(cmd) && fault_valid 413 resp(idx).bits.excp(nDups).af.st := af && TlbCmd.isWrite(cmd) && fault_valid 414 resp(idx).bits.excp(nDups).af.instr := af && TlbCmd.isExec(cmd) && fault_valid 415 416 resp(idx).bits.excp(nDups).vaNeedExt := true.B 417 } 418 419 resp(idx).bits.excp(nDups).isHyper := isHyperInst(idx) 420 } 421 422 def handle_nonblock(idx: Int): Unit = { 423 io.requestor(idx).resp.valid := req_out_v(idx) 424 io.requestor(idx).req.ready := io.requestor(idx).resp.ready // should always be true 425 XSError(!io.requestor(idx).resp.ready, s"${q.name} port ${idx} is non-block, resp.ready must be true.B") 426 427 val req_need_gpa = hasGpf(idx) 428 val req_s2xlate = Wire(UInt(2.W)) 429 req_s2xlate := MuxCase(noS2xlate, Seq( 430 (!(virt_out(idx) || req_out(idx).hyperinst)) -> noS2xlate, 431 (csr.vsatp.mode =/= 0.U && csr.hgatp.mode =/= 0.U) -> allStage, 432 (csr.vsatp.mode === 0.U) -> onlyStage2, 433 (csr.hgatp.mode === 0.U || req_need_gpa) -> onlyStage1 434 )) 435 436 val ptw_just_back = ptw.resp.fire && req_s2xlate === ptw.resp.bits.s2xlate && ptw.resp.bits.hit(get_pn(req_out(idx).vaddr), io.csr.satp.asid, io.csr.vsatp.asid, io.csr.hgatp.vmid, true, false) 437 // TODO: RegNext enable: ptw.resp.valid ? req.valid 438 val ptw_resp_bits_reg = RegEnable(ptw.resp.bits, ptw.resp.valid) 439 val ptw_already_back = GatedValidRegNext(ptw.resp.fire) && req_s2xlate === ptw_resp_bits_reg.s2xlate && ptw_resp_bits_reg.hit(get_pn(req_out(idx).vaddr), io.csr.satp.asid, io.csr.vsatp.asid, io.csr.hgatp.vmid, allType = true) 440 val ptw_getGpa = req_need_gpa && hitVec(idx) 441 val need_gpa_vpn_hit = need_gpa_vpn === get_pn(req_out(idx).vaddr) 442 io.ptw.req(idx).valid := req_out_v(idx) && missVec(idx) && !(ptw_just_back || ptw_already_back || (!need_gpa_vpn_hit && req_out_v(idx) && need_gpa && !resp_gpa_refill && ptw_getGpa)) // TODO: remove the regnext, timing 443 io.tlbreplay(idx) := req_out_v(idx) && missVec(idx) && (ptw_just_back || ptw_already_back || (!need_gpa_vpn_hit && req_out_v(idx) && need_gpa && !resp_gpa_refill && ptw_getGpa)) 444 when (io.requestor(idx).req_kill && GatedValidRegNext(io.requestor(idx).req.fire)) { 445 io.ptw.req(idx).valid := false.B 446 io.tlbreplay(idx) := true.B 447 } 448 io.ptw.req(idx).bits.vpn := get_pn(req_out(idx).vaddr) 449 io.ptw.req(idx).bits.s2xlate := req_s2xlate 450 io.ptw.req(idx).bits.getGpa := ptw_getGpa 451 io.ptw.req(idx).bits.memidx := req_out(idx).memidx 452 } 453 454 def handle_block(idx: Int): Unit = { 455 // three valid: 1.if exist a entry; 2.if sent to ptw; 3.unset resp.valid 456 io.requestor(idx).req.ready := !req_out_v(idx) || io.requestor(idx).resp.fire 457 // req_out_v for if there is a request, may long latency, fixme 458 459 // miss request entries 460 val req_need_gpa = hasGpf(idx) 461 val miss_req_vpn = get_pn(req_out(idx).vaddr) 462 val miss_req_memidx = req_out(idx).memidx 463 val miss_req_s2xlate = Wire(UInt(2.W)) 464 miss_req_s2xlate := MuxCase(noS2xlate, Seq( 465 (!(virt_out(idx) || req_out(idx).hyperinst)) -> noS2xlate, 466 (csr.vsatp.mode =/= 0.U && csr.hgatp.mode =/= 0.U) -> allStage, 467 (csr.vsatp.mode === 0.U) -> onlyStage2, 468 (csr.hgatp.mode === 0.U || req_need_gpa) -> onlyStage1 469 )) 470 val miss_req_s2xlate_reg = RegEnable(miss_req_s2xlate, io.ptw.req(idx).fire) 471 val hasS2xlate = miss_req_s2xlate_reg =/= noS2xlate 472 val onlyS2 = miss_req_s2xlate_reg === onlyStage2 473 val hit_s1 = io.ptw.resp.bits.s1.hit(miss_req_vpn, Mux(hasS2xlate, io.csr.vsatp.asid, io.csr.satp.asid), io.csr.hgatp.vmid, allType = true, false, hasS2xlate) 474 val hit_s2 = io.ptw.resp.bits.s2.hit(miss_req_vpn, io.csr.hgatp.vmid) 475 val hit = Mux(onlyS2, hit_s2, hit_s1) && io.ptw.resp.valid && miss_req_s2xlate_reg === io.ptw.resp.bits.s2xlate 476 477 val new_coming_valid = WireInit(false.B) 478 new_coming_valid := req_in(idx).fire && !req_in(idx).bits.kill && !flush_pipe(idx) 479 val new_coming = GatedValidRegNext(new_coming_valid) 480 val miss_wire = new_coming && missVec(idx) 481 val miss_v = ValidHoldBypass(miss_wire, resp(idx).fire, flush_pipe(idx)) 482 val miss_req_v = ValidHoldBypass(miss_wire || (miss_v && flush_mmu && !mmu_flush_pipe), 483 io.ptw.req(idx).fire || resp(idx).fire, flush_pipe(idx)) 484 485 // when ptw resp, check if hit, reset miss_v, resp to lsu/ifu 486 resp(idx).valid := req_out_v(idx) && !(miss_v && portTranslateEnable(idx)) 487 when (io.ptw.resp.fire && hit && req_out_v(idx) && portTranslateEnable(idx)) { 488 val stage1 = io.ptw.resp.bits.s1 489 val stage2 = io.ptw.resp.bits.s2 490 val s2xlate = io.ptw.resp.bits.s2xlate 491 resp(idx).valid := true.B 492 resp(idx).bits.miss := false.B 493 val s1_paddr = Cat(stage1.genPPN(get_pn(req_out(idx).vaddr)), get_off(req_out(idx).vaddr)) 494 val s2_paddr = Cat(stage2.genPPNS2(get_pn(req_out(idx).vaddr)), get_off(req_out(idx).vaddr)) 495 for (d <- 0 until nRespDups) { 496 resp(idx).bits.paddr(d) := Mux(s2xlate =/= noS2xlate, s2_paddr, s1_paddr) 497 resp(idx).bits.gpaddr(d) := s1_paddr 498 pbmt_check(idx, d, io.ptw.resp.bits.s1.entry.pbmt, io.ptw.resp.bits.s2.entry.pbmt, s2xlate) 499 perm_check(stage1, req_out(idx).cmd, idx, d, stage2, req_out(idx).hlvx, s2xlate) 500 } 501 pmp_check(resp(idx).bits.paddr(0), req_out(idx).size, req_out(idx).cmd, false.B, idx) 502 503 // NOTE: the unfiltered req would be handled by Repeater 504 } 505 assert(RegNext(!resp(idx).valid || resp(idx).ready, true.B), "when tlb resp valid, ready should be true, must") 506 assert(RegNext(req_out_v(idx) || !(miss_v || miss_req_v), true.B), "when not req_out_v, should not set miss_v/miss_req_v") 507 508 val ptw_req = io.ptw.req(idx) 509 ptw_req.valid := miss_req_v 510 ptw_req.bits.vpn := miss_req_vpn 511 ptw_req.bits.s2xlate := miss_req_s2xlate 512 ptw_req.bits.getGpa := req_need_gpa && hitVec(idx) 513 ptw_req.bits.memidx := miss_req_memidx 514 515 io.tlbreplay(idx) := false.B 516 517 // NOTE: when flush pipe, tlb should abandon last req 518 // however, some outside modules like icache, dont care flushPipe, and still waiting for tlb resp 519 // just resp valid and raise page fault to go through. The pipe(ifu) will abandon it. 520 if (!q.outsideRecvFlush) { 521 when (req_out_v(idx) && flush_pipe(idx) && portTranslateEnable(idx)) { 522 resp(idx).valid := true.B 523 for (d <- 0 until nRespDups) { 524 resp(idx).bits.pbmt(d) := 0.U 525 resp(idx).bits.excp(d).pf.ld := true.B // sfence happened, pf for not to use this addr 526 resp(idx).bits.excp(d).pf.st := true.B 527 resp(idx).bits.excp(d).pf.instr := true.B 528 } 529 } 530 } 531 } 532 533 // when ptw resp, tlb at refill_idx maybe set to miss by force. 534 // Bypass ptw resp to check. 535 def ptw_resp_bypass(vpn: UInt, s2xlate: UInt) = { 536 // TODO: RegNext enable: ptw.resp.valid 537 val hasS2xlate = s2xlate =/= noS2xlate 538 val onlyS2 = s2xlate === onlyStage2 539 val onlyS1 = s2xlate === onlyStage1 540 val s2xlate_hit = s2xlate === ptw.resp.bits.s2xlate 541 val resp_hit = ptw.resp.bits.hit(vpn, io.csr.satp.asid, io.csr.vsatp.asid, io.csr.hgatp.vmid, true, false) 542 val p_hit = GatedValidRegNext(resp_hit && io.ptw.resp.fire && s2xlate_hit) 543 val ppn_s1 = ptw.resp.bits.s1.genPPN(vpn) 544 val gvpn = Mux(onlyS2, vpn, ppn_s1) 545 val ppn_s2 = ptw.resp.bits.s2.genPPNS2(gvpn) 546 val p_ppn = RegEnable(Mux(s2xlate === onlyStage2 || s2xlate === allStage, ppn_s2, ppn_s1), io.ptw.resp.fire) 547 val p_pbmt = RegEnable(ptw.resp.bits.s1.entry.pbmt,io.ptw.resp.fire) 548 val p_perm = RegEnable(ptwresp_to_tlbperm(ptw.resp.bits.s1), io.ptw.resp.fire) 549 val p_gvpn = RegEnable(Mux(onlyS2, ptw.resp.bits.s2.entry.tag, ptw.resp.bits.s1.genGVPN(vpn)), io.ptw.resp.fire) 550 val p_g_pbmt = RegEnable(ptw.resp.bits.s2.entry.pbmt,io.ptw.resp.fire) 551 val p_g_perm = RegEnable(hptwresp_to_tlbperm(ptw.resp.bits.s2), io.ptw.resp.fire) 552 val p_s2xlate = RegEnable(ptw.resp.bits.s2xlate, io.ptw.resp.fire) 553 val p_s1_level = RegEnable(ptw.resp.bits.s1.entry.level.get, io.ptw.resp.fire) 554 val p_s1_isLeaf = RegEnable(ptw.resp.bits.s1.isLeaf(), io.ptw.resp.fire) 555 val p_s1_isFakePte = RegEnable(ptw.resp.bits.s1.isFakePte(), io.ptw.resp.fire) 556 (p_hit, p_ppn, p_pbmt, p_perm, p_gvpn, p_g_pbmt, p_g_perm, p_s2xlate, p_s1_level, p_s1_isLeaf, p_s1_isFakePte) 557 } 558 559 // perf event 560 val result_ok = req_in.map(a => GatedValidRegNext(a.fire)) 561 val perfEvents = 562 Seq( 563 ("access", PopCount((0 until Width).map{i => if (Block(i)) io.requestor(i).req.fire else portTranslateEnable(i) && result_ok(i) })), 564 ("miss ", PopCount((0 until Width).map{i => if (Block(i)) portTranslateEnable(i) && result_ok(i) && missVec(i) else ptw.req(i).fire })), 565 ) 566 generatePerfEvent() 567 568 // perf log 569 for (i <- 0 until Width) { 570 if (Block(i)) { 571 XSPerfAccumulate(s"access${i}",result_ok(i) && portTranslateEnable(i)) 572 XSPerfAccumulate(s"miss${i}", result_ok(i) && missVec(i)) 573 } else { 574 XSPerfAccumulate("first_access" + Integer.toString(i, 10), result_ok(i) && portTranslateEnable(i) && RegEnable(req(i).bits.debug.isFirstIssue, req(i).valid)) 575 XSPerfAccumulate("access" + Integer.toString(i, 10), result_ok(i) && portTranslateEnable(i)) 576 XSPerfAccumulate("first_miss" + Integer.toString(i, 10), result_ok(i) && portTranslateEnable(i) && missVec(i) && RegEnable(req(i).bits.debug.isFirstIssue, req(i).valid)) 577 XSPerfAccumulate("miss" + Integer.toString(i, 10), result_ok(i) && portTranslateEnable(i) && missVec(i)) 578 } 579 } 580 XSPerfAccumulate("ptw_resp_count", ptw.resp.fire) 581 XSPerfAccumulate("ptw_resp_pf_count", ptw.resp.fire && ptw.resp.bits.s1.pf) 582 583 // Log 584 for(i <- 0 until Width) { 585 XSDebug(req(i).valid, p"req(${i.U}): (${req(i).valid} ${req(i).ready}) ${req(i).bits}\n") 586 XSDebug(resp(i).valid, p"resp(${i.U}): (${resp(i).valid} ${resp(i).ready}) ${resp(i).bits}\n") 587 } 588 589 XSDebug(io.sfence.valid, p"Sfence: ${io.sfence}\n") 590 XSDebug(ParallelOR(req_out_v) || ptw.resp.valid, p"vmEnable:${vmEnable} hit:${Binary(VecInit(hitVec).asUInt)} miss:${Binary(VecInit(missVec).asUInt)}\n") 591 for (i <- ptw.req.indices) { 592 XSDebug(ptw.req(i).fire, p"L2TLB req:${ptw.req(i).bits}\n") 593 } 594 XSDebug(ptw.resp.valid, p"L2TLB resp:${ptw.resp.bits} (v:${ptw.resp.valid}r:${ptw.resp.ready}) \n") 595 596 println(s"${q.name}: page: ${q.NWays} ${q.Associative} ${q.Replacer.get}") 597 598 if (env.EnableDifftest) { 599 for (i <- 0 until Width) { 600 val pf = io.requestor(i).resp.bits.excp(0).pf.instr || io.requestor(i).resp.bits.excp(0).pf.st || io.requestor(i).resp.bits.excp(0).pf.ld 601 val gpf = io.requestor(i).resp.bits.excp(0).gpf.instr || io.requestor(i).resp.bits.excp(0).gpf.st || io.requestor(i).resp.bits.excp(0).gpf.ld 602 val af = io.requestor(i).resp.bits.excp(0).af.instr || io.requestor(i).resp.bits.excp(0).af.st || io.requestor(i).resp.bits.excp(0).af.ld 603 val difftest = DifftestModule(new DiffL1TLBEvent) 604 difftest.coreid := io.hartId 605 difftest.valid := RegNext(io.requestor(i).req.fire) && !io.requestor(i).req_kill && io.requestor(i).resp.fire && !io.requestor(i).resp.bits.miss && !pf && !af && !gpf && portTranslateEnable(i) 606 if (!Seq("itlb", "ldtlb", "sttlb").contains(q.name)) { 607 difftest.valid := false.B 608 } 609 difftest.index := TLBDiffId(p(XSCoreParamsKey).HartId).U 610 difftest.vpn := RegEnable(get_pn(req_in(i).bits.vaddr), req_in(i).valid) 611 difftest.ppn := get_pn(io.requestor(i).resp.bits.paddr(0)) 612 difftest.satp := Cat(io.csr.satp.mode, io.csr.satp.asid, io.csr.satp.ppn) 613 difftest.vsatp := Cat(io.csr.vsatp.mode, io.csr.vsatp.asid, io.csr.vsatp.ppn) 614 difftest.hgatp := Cat(io.csr.hgatp.mode, io.csr.hgatp.vmid, io.csr.hgatp.ppn) 615 val req_need_gpa = gpf 616 val req_s2xlate = Wire(UInt(2.W)) 617 req_s2xlate := MuxCase(noS2xlate, Seq( 618 (!RegNext(virt_in || req_in(i).bits.hyperinst)) -> noS2xlate, 619 (vsatp.mode =/= 0.U && hgatp.mode =/= 0.U) -> allStage, 620 (vsatp.mode === 0.U) -> onlyStage2, 621 (hgatp.mode === 0.U || req_need_gpa) -> onlyStage1 622 )) 623 difftest.s2xlate := req_s2xlate 624 } 625 } 626} 627 628object TLBDiffId { 629 var i: Int = 0 630 var lastHartId: Int = -1 631 def apply(hartId: Int): Int = { 632 if (lastHartId != hartId) { 633 i = 0 634 lastHartId = hartId 635 } 636 i += 1 637 i - 1 638 } 639} 640 641class TLBNonBlock(Width: Int, nRespDups: Int = 1, q: TLBParameters)(implicit p: Parameters) extends TLB(Width, nRespDups, Seq.fill(Width)(false), q) 642class TLBBLock(Width: Int, nRespDups: Int = 1, q: TLBParameters)(implicit p: Parameters) extends TLB(Width, nRespDups, Seq.fill(Width)(true), q) 643 644class TlbReplace(Width: Int, q: TLBParameters)(implicit p: Parameters) extends TlbModule { 645 val io = IO(new TlbReplaceIO(Width, q)) 646 647 if (q.Associative == "fa") { 648 val re = ReplacementPolicy.fromString(q.Replacer, q.NWays) 649 re.access(io.page.access.map(_.touch_ways)) 650 io.page.refillIdx := re.way 651 } else { // set-acco && plru 652 val re = ReplacementPolicy.fromString(q.Replacer, q.NSets, q.NWays) 653 re.access(io.page.access.map(_.sets), io.page.access.map(_.touch_ways)) 654 io.page.refillIdx := { if (q.NWays == 1) 0.U else re.way(io.page.chosen_set) } 655 } 656} 657