1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 24import utils._ 25import utility._ 26import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 27import freechips.rocketchip.tilelink._ 28 29class PTWReapterIO(Width: Int)(implicit p: Parameters) extends MMUIOBaseBundle { 30 val tlb = Flipped(new TlbPtwIO(Width)) 31 val ptw = new TlbPtwIO 32 33 def apply(tlb: TlbPtwIO, ptw: TlbPtwIO, sfence: SfenceBundle, csr: TlbCsrBundle): Unit = { 34 this.tlb <> tlb 35 this.ptw <> ptw 36 this.sfence <> sfence 37 this.csr <> csr 38 } 39 40 def apply(tlb: TlbPtwIO, sfence: SfenceBundle, csr: TlbCsrBundle): Unit = { 41 this.tlb <> tlb 42 this.sfence <> sfence 43 this.csr <> csr 44 } 45 46} 47 48class PTWRepeater(Width: Int = 1, FenceDelay: Int)(implicit p: Parameters) extends XSModule with HasPtwConst { 49 val io = IO(new PTWReapterIO(Width)) 50 51 val req_in = if (Width == 1) { 52 io.tlb.req(0) 53 } else { 54 val arb = Module(new RRArbiter(io.tlb.req(0).bits.cloneType, Width)) 55 arb.io.in <> io.tlb.req 56 arb.io.out 57 } 58 val (tlb, ptw, flush) = (io.tlb, io.ptw, DelayN(io.sfence.valid || io.csr.satp.changed, FenceDelay)) 59 val req = RegEnable(req_in.bits, req_in.fire()) 60 val resp = RegEnable(ptw.resp.bits, ptw.resp.fire()) 61 val haveOne = BoolStopWatch(req_in.fire(), tlb.resp.fire() || flush) 62 val sent = BoolStopWatch(ptw.req(0).fire(), req_in.fire() || flush) 63 val recv = BoolStopWatch(ptw.resp.fire() && haveOne, req_in.fire() || flush) 64 65 req_in.ready := !haveOne 66 ptw.req(0).valid := haveOne && !sent 67 ptw.req(0).bits := req 68 69 tlb.resp.bits := resp 70 tlb.resp.valid := haveOne && recv 71 ptw.resp.ready := !recv 72 73 XSPerfAccumulate("req_count", ptw.req(0).fire()) 74 XSPerfAccumulate("tlb_req_cycle", BoolStopWatch(req_in.fire(), tlb.resp.fire() || flush)) 75 XSPerfAccumulate("ptw_req_cycle", BoolStopWatch(ptw.req(0).fire(), ptw.resp.fire() || flush)) 76 77 XSDebug(haveOne, p"haveOne:${haveOne} sent:${sent} recv:${recv} sfence:${flush} req:${req} resp:${resp}") 78 XSDebug(req_in.valid || io.tlb.resp.valid, p"tlb: ${tlb}\n") 79 XSDebug(io.ptw.req(0).valid || io.ptw.resp.valid, p"ptw: ${ptw}\n") 80 assert(!RegNext(recv && io.ptw.resp.valid, init = false.B), "re-receive ptw.resp") 81 XSError(io.ptw.req(0).valid && io.ptw.resp.valid && !flush, "ptw repeater recv resp when sending") 82 XSError(io.ptw.resp.valid && (req.vpn =/= io.ptw.resp.bits.entry.tag), "ptw repeater recv resp with wrong tag") 83 XSError(io.ptw.resp.valid && !io.ptw.resp.ready, "ptw repeater's ptw resp back, but not ready") 84 TimeOutAssert(sent && !recv, timeOutThreshold, "Repeater doesn't recv resp in time") 85} 86 87/* dtlb 88 * 89 */ 90 91class PTWRepeaterNB(Width: Int = 1, passReady: Boolean = false, FenceDelay: Int)(implicit p: Parameters) extends XSModule with HasPtwConst { 92 val io = IO(new PTWReapterIO(Width)) 93 94 val req_in = if (Width == 1) { 95 io.tlb.req(0) 96 } else { 97 val arb = Module(new RRArbiter(io.tlb.req(0).bits.cloneType, Width)) 98 arb.io.in <> io.tlb.req 99 arb.io.out 100 } 101 val (tlb, ptw, flush) = (io.tlb, io.ptw, DelayN(io.sfence.valid || io.csr.satp.changed, FenceDelay)) 102 /* sent: tlb -> repeater -> ptw 103 * recv: ptw -> repeater -> tlb 104 * different from PTWRepeater 105 */ 106 107 // tlb -> repeater -> ptw 108 val req = RegEnable(req_in.bits, req_in.fire()) 109 val sent = BoolStopWatch(req_in.fire(), ptw.req(0).fire() || flush) 110 req_in.ready := !sent || { if (passReady) ptw.req(0).ready else false.B } 111 ptw.req(0).valid := sent 112 ptw.req(0).bits := req 113 114 // ptw -> repeater -> tlb 115 val resp = RegEnable(ptw.resp.bits, ptw.resp.fire()) 116 val recv = BoolStopWatch(ptw.resp.fire(), tlb.resp.fire() || flush) 117 ptw.resp.ready := !recv || { if (passReady) tlb.resp.ready else false.B } 118 tlb.resp.valid := recv 119 tlb.resp.bits := resp 120 121 XSPerfAccumulate("req", req_in.fire()) 122 XSPerfAccumulate("resp", tlb.resp.fire()) 123 if (!passReady) { 124 XSPerfAccumulate("req_blank", req_in.valid && sent && ptw.req(0).ready) 125 XSPerfAccumulate("resp_blank", ptw.resp.valid && recv && tlb.resp.ready) 126 XSPerfAccumulate("req_blank_ignore_ready", req_in.valid && sent) 127 XSPerfAccumulate("resp_blank_ignore_ready", ptw.resp.valid && recv) 128 } 129 XSDebug(req_in.valid || io.tlb.resp.valid, p"tlb: ${tlb}\n") 130 XSDebug(io.ptw.req(0).valid || io.ptw.resp.valid, p"ptw: ${ptw}\n") 131} 132 133class PTWFilterIO(Width: Int)(implicit p: Parameters) extends MMUIOBaseBundle { 134 val tlb = Flipped(new VectorTlbPtwIO(Width)) 135 val ptw = new TlbPtwIO() 136 137 def apply(tlb: VectorTlbPtwIO, ptw: TlbPtwIO, sfence: SfenceBundle, csr: TlbCsrBundle): Unit = { 138 this.tlb <> tlb 139 this.ptw <> ptw 140 this.sfence <> sfence 141 this.csr <> csr 142 } 143 144 def apply(tlb: VectorTlbPtwIO, sfence: SfenceBundle, csr: TlbCsrBundle): Unit = { 145 this.tlb <> tlb 146 this.sfence <> sfence 147 this.csr <> csr 148 } 149 150} 151 152class PTWFilter(Width: Int, Size: Int, FenceDelay: Int)(implicit p: Parameters) extends XSModule with HasPtwConst { 153 require(Size >= Width) 154 155 val io = IO(new PTWFilterIO(Width)) 156 157 val v = RegInit(VecInit(Seq.fill(Size)(false.B))) 158 val ports = Reg(Vec(Size, Vec(Width, Bool()))) // record which port(s) the entry come from, may not able to cover all the ports 159 val vpn = Reg(Vec(Size, UInt(vpnLen.W))) 160 val enqPtr = RegInit(0.U(log2Up(Size).W)) // Enq 161 val issPtr = RegInit(0.U(log2Up(Size).W)) // Iss to Ptw 162 val deqPtr = RegInit(0.U(log2Up(Size).W)) // Deq 163 val mayFullDeq = RegInit(false.B) 164 val mayFullIss = RegInit(false.B) 165 val counter = RegInit(0.U(log2Up(Size+1).W)) 166 167 val flush = DelayN(io.sfence.valid || io.csr.satp.changed, FenceDelay) 168 val tlb_req = WireInit(io.tlb.req) // NOTE: tlb_req is not io.tlb.req, see below codes, just use cloneType 169 tlb_req.suggestName("tlb_req") 170 171 val inflight_counter = RegInit(0.U(log2Up(Size + 1).W)) 172 val inflight_full = inflight_counter === Size.U 173 when (io.ptw.req(0).fire() =/= io.ptw.resp.fire()) { 174 inflight_counter := Mux(io.ptw.req(0).fire(), inflight_counter + 1.U, inflight_counter - 1.U) 175 } 176 177 val canEnqueue = Wire(Bool()) // NOTE: actually enqueue 178 val ptwResp = RegEnable(io.ptw.resp.bits, io.ptw.resp.fire()) 179 val ptwResp_OldMatchVec = vpn.zip(v).map{ case (pi, vi) => 180 vi && io.ptw.resp.bits.entry.hit(pi, io.csr.satp.asid, true, true)} 181 val ptwResp_valid = RegNext(io.ptw.resp.fire() && Cat(ptwResp_OldMatchVec).orR, init = false.B) 182 val oldMatchVec_early = io.tlb.req.map(a => vpn.zip(v).map{ case (pi, vi) => vi && pi === a.bits.vpn}) 183 val lastReqMatchVec_early = io.tlb.req.map(a => tlb_req.map{ b => b.valid && b.bits.vpn === a.bits.vpn && canEnqueue}) 184 val newMatchVec_early = io.tlb.req.map(a => io.tlb.req.map(b => a.bits.vpn === b.bits.vpn)) 185 186 (0 until Width) foreach { i => 187 tlb_req(i).valid := RegNext(io.tlb.req(i).valid && 188 !(ptwResp_valid && ptwResp.entry.hit(io.tlb.req(i).bits.vpn, 0.U, true, true)) && 189 !Cat(lastReqMatchVec_early(i)).orR, 190 init = false.B) 191 tlb_req(i).bits := RegEnable(io.tlb.req(i).bits, io.tlb.req(i).valid) 192 } 193 194 val oldMatchVec = oldMatchVec_early.map(a => RegNext(Cat(a).orR)) 195 val newMatchVec = (0 until Width).map(i => (0 until Width).map(j => 196 RegNext(newMatchVec_early(i)(j)) && tlb_req(j).valid 197 )) 198 val ptwResp_newMatchVec = tlb_req.map(a => 199 ptwResp_valid && ptwResp.entry.hit(a.bits.vpn, 0.U, allType = true, true)) 200 201 val oldMatchVec2 = (0 until Width).map(i => oldMatchVec_early(i).map(RegNext(_)).map(_ & tlb_req(i).valid)) 202 val update_ports = v.indices.map(i => oldMatchVec2.map(j => j(i))) 203 val ports_init = (0 until Width).map(i => (1 << i).U(Width.W)) 204 val filter_ports = (0 until Width).map(i => ParallelMux(newMatchVec(i).zip(ports_init).drop(i))) 205 val resp_vector = RegEnable(ParallelMux(ptwResp_OldMatchVec zip ports), io.ptw.resp.fire()) 206 207 def canMerge(index: Int) : Bool = { 208 ptwResp_newMatchVec(index) || oldMatchVec(index) || 209 Cat(newMatchVec(index).take(index)).orR 210 } 211 212 def filter_req() = { 213 val reqs = tlb_req.indices.map{ i => 214 val req = Wire(ValidIO(new PtwReq())) 215 val merge = canMerge(i) 216 req.bits := tlb_req(i).bits 217 req.valid := !merge && tlb_req(i).valid 218 req 219 } 220 reqs 221 } 222 223 val reqs = filter_req() 224 val req_ports = filter_ports 225 val isFull = enqPtr === deqPtr && mayFullDeq 226 val isEmptyDeq = enqPtr === deqPtr && !mayFullDeq 227 val isEmptyIss = enqPtr === issPtr && !mayFullIss 228 val accumEnqNum = (0 until Width).map(i => PopCount(reqs.take(i).map(_.valid))) 229 val enqPtrVecInit = VecInit((0 until Width).map(i => enqPtr + i.U)) 230 val enqPtrVec = VecInit((0 until Width).map(i => enqPtrVecInit(accumEnqNum(i)))) 231 val enqNum = PopCount(reqs.map(_.valid)) 232 canEnqueue := counter +& enqNum <= Size.U 233 234 // the req may recv false ready, but actually received. Filter and TLB will handle it. 235 val enqNum_fake = PopCount(io.tlb.req.map(_.valid)) 236 val canEnqueue_fake = counter +& enqNum_fake <= Size.U 237 io.tlb.req.map(_.ready := canEnqueue_fake) // NOTE: just drop un-fire reqs 238 239 // tlb req flushed by ptw resp: last ptw resp && current ptw resp 240 // the flushed tlb req will fakely enq, with a false valid 241 val tlb_req_flushed = reqs.map(a => io.ptw.resp.valid && io.ptw.resp.bits.entry.hit(a.bits.vpn, 0.U, true, true)) 242 243 io.tlb.resp.valid := ptwResp_valid 244 io.tlb.resp.bits.data := ptwResp 245 io.tlb.resp.bits.vector := resp_vector 246 247 val issue_valid = v(issPtr) && !isEmptyIss && !inflight_full 248 val issue_filtered = ptwResp_valid && ptwResp.entry.hit(io.ptw.req(0).bits.vpn, io.csr.satp.asid, allType=true, ignoreAsid=true) 249 val issue_fire_fake = issue_valid && (io.ptw.req(0).ready || (issue_filtered && false.B /*timing-opt*/)) 250 io.ptw.req(0).valid := issue_valid && !issue_filtered 251 io.ptw.req(0).bits.vpn := vpn(issPtr) 252 io.ptw.resp.ready := true.B 253 254 reqs.zipWithIndex.map{ 255 case (req, i) => 256 when (req.valid && canEnqueue) { 257 v(enqPtrVec(i)) := !tlb_req_flushed(i) 258 vpn(enqPtrVec(i)) := req.bits.vpn 259 ports(enqPtrVec(i)) := req_ports(i).asBools 260 } 261 } 262 for (i <- ports.indices) { 263 when (v(i)) { 264 ports(i) := ports(i).zip(update_ports(i)).map(a => a._1 || a._2) 265 } 266 } 267 268 val do_enq = canEnqueue && Cat(reqs.map(_.valid)).orR 269 val do_deq = (!v(deqPtr) && !isEmptyDeq) 270 val do_iss = issue_fire_fake || (!v(issPtr) && !isEmptyIss) 271 when (do_enq) { 272 enqPtr := enqPtr + enqNum 273 } 274 when (do_deq) { 275 deqPtr := deqPtr + 1.U 276 } 277 when (do_iss) { 278 issPtr := issPtr + 1.U 279 } 280 when (issue_fire_fake && issue_filtered) { // issued but is filtered 281 v(issPtr) := false.B 282 } 283 when (do_enq =/= do_deq) { 284 mayFullDeq := do_enq 285 } 286 when (do_enq =/= do_iss) { 287 mayFullIss := do_enq 288 } 289 290 when (io.ptw.resp.fire()) { 291 v.zip(ptwResp_OldMatchVec).map{ case (vi, mi) => when (mi) { vi := false.B }} 292 } 293 294 counter := counter - do_deq + Mux(do_enq, enqNum, 0.U) 295 assert(counter <= Size.U, "counter should be no more than Size") 296 assert(inflight_counter <= Size.U, "inflight should be no more than Size") 297 when (counter === 0.U) { 298 assert(!io.ptw.req(0).fire(), "when counter is 0, should not req") 299 assert(isEmptyDeq && isEmptyIss, "when counter is 0, should be empty") 300 } 301 when (counter === Size.U) { 302 assert(mayFullDeq, "when counter is Size, should be full") 303 } 304 305 when (flush) { 306 v.map(_ := false.B) 307 deqPtr := 0.U 308 enqPtr := 0.U 309 issPtr := 0.U 310 ptwResp_valid := false.B 311 mayFullDeq := false.B 312 mayFullIss := false.B 313 counter := 0.U 314 inflight_counter := 0.U 315 } 316 317 // perf 318 XSPerfAccumulate("tlb_req_count", PopCount(Cat(io.tlb.req.map(_.valid)))) 319 XSPerfAccumulate("tlb_req_count_filtered", Mux(do_enq, accumEnqNum(Width - 1), 0.U)) 320 XSPerfAccumulate("ptw_req_count", io.ptw.req(0).fire()) 321 XSPerfAccumulate("ptw_req_cycle", inflight_counter) 322 XSPerfAccumulate("tlb_resp_count", io.tlb.resp.fire()) 323 XSPerfAccumulate("ptw_resp_count", io.ptw.resp.fire()) 324 XSPerfAccumulate("inflight_cycle", !isEmptyDeq) 325 for (i <- 0 until Size + 1) { 326 XSPerfAccumulate(s"counter${i}", counter === i.U) 327 } 328 329 for (i <- 0 until Size) { 330 TimeOutAssert(v(i), timeOutThreshold, s"Filter ${i} doesn't recv resp in time") 331 } 332} 333 334object PTWRepeater { 335 def apply(fenceDelay: Int, 336 tlb: TlbPtwIO, 337 sfence: SfenceBundle, 338 csr: TlbCsrBundle 339 )(implicit p: Parameters) = { 340 val width = tlb.req.size 341 val repeater = Module(new PTWRepeater(width, fenceDelay)) 342 repeater.io.apply(tlb, sfence, csr) 343 repeater 344 } 345 346 def apply(fenceDelay: Int, 347 tlb: TlbPtwIO, 348 ptw: TlbPtwIO, 349 sfence: SfenceBundle, 350 csr: TlbCsrBundle 351 )(implicit p: Parameters) = { 352 val width = tlb.req.size 353 val repeater = Module(new PTWRepeater(width, fenceDelay)) 354 repeater.io.apply(tlb, ptw, sfence, csr) 355 repeater 356 } 357} 358 359object PTWRepeaterNB { 360 def apply(passReady: Boolean, fenceDelay: Int, 361 tlb: TlbPtwIO, 362 sfence: SfenceBundle, 363 csr: TlbCsrBundle 364 )(implicit p: Parameters) = { 365 val width = tlb.req.size 366 val repeater = Module(new PTWRepeaterNB(width, passReady,fenceDelay)) 367 repeater.io.apply(tlb, sfence, csr) 368 repeater 369 } 370 371 def apply(passReady: Boolean, fenceDelay: Int, 372 tlb: TlbPtwIO, 373 ptw: TlbPtwIO, 374 sfence: SfenceBundle, 375 csr: TlbCsrBundle 376 )(implicit p: Parameters) = { 377 val width = tlb.req.size 378 val repeater = Module(new PTWRepeaterNB(width, passReady, fenceDelay)) 379 repeater.io.apply(tlb, ptw, sfence, csr) 380 repeater 381 } 382} 383 384object PTWFilter { 385 def apply(fenceDelay: Int, 386 tlb: VectorTlbPtwIO, 387 ptw: TlbPtwIO, 388 sfence: SfenceBundle, 389 csr: TlbCsrBundle, 390 size: Int 391 )(implicit p: Parameters) = { 392 val width = tlb.req.size 393 val filter = Module(new PTWFilter(width, size, fenceDelay)) 394 filter.io.apply(tlb, ptw, sfence, csr) 395 filter 396 } 397 398 def apply(fenceDelay: Int, 399 tlb: VectorTlbPtwIO, 400 sfence: SfenceBundle, 401 csr: TlbCsrBundle, 402 size: Int 403 )(implicit p: Parameters) = { 404 val width = tlb.req.size 405 val filter = Module(new PTWFilter(width, size, fenceDelay)) 406 filter.io.apply(tlb, sfence, csr) 407 filter 408 } 409 410} 411