1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 24import utils._ 25import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 26import freechips.rocketchip.tilelink._ 27 28class PTWReapterIO(Width: Int)(implicit p: Parameters) extends MMUIOBaseBundle { 29 val tlb = Flipped(new TlbPtwIO(Width)) 30 val ptw = new TlbPtwIO 31 32 def apply(tlb: TlbPtwIO, ptw: TlbPtwIO, sfence: SfenceBundle, csr: TlbCsrBundle): Unit = { 33 this.tlb <> tlb 34 this.ptw <> ptw 35 this.sfence <> sfence 36 this.csr <> csr 37 } 38 39 def apply(tlb: TlbPtwIO, sfence: SfenceBundle, csr: TlbCsrBundle): Unit = { 40 this.tlb <> tlb 41 this.sfence <> sfence 42 this.csr <> csr 43 } 44 45 override def cloneType: this.type = (new PTWReapterIO(Width)).asInstanceOf[this.type] 46} 47 48class PTWRepeater(Width: Int = 1)(implicit p: Parameters) extends XSModule with HasPtwConst { 49 val io = IO(new PTWReapterIO(Width)) 50 51 val req_in = if (Width == 1) { 52 io.tlb.req(0) 53 } else { 54 val arb = Module(new RRArbiter(io.tlb.req(0).bits.cloneType, Width)) 55 arb.io.in <> io.tlb.req 56 arb.io.out 57 } 58 val (tlb, ptw, flush) = (io.tlb, io.ptw, RegNext(io.sfence.valid || io.csr.satp.changed)) 59 val req = RegEnable(req_in.bits, req_in.fire()) 60 val resp = RegEnable(ptw.resp.bits, ptw.resp.fire()) 61 val haveOne = BoolStopWatch(req_in.fire(), tlb.resp.fire() || flush) 62 val sent = BoolStopWatch(ptw.req(0).fire(), req_in.fire() || flush) 63 val recv = BoolStopWatch(ptw.resp.fire(), req_in.fire() || flush) 64 65 req_in.ready := !haveOne 66 ptw.req(0).valid := haveOne && !sent 67 ptw.req(0).bits := req 68 69 tlb.resp.bits := resp 70 tlb.resp.valid := haveOne && recv 71 ptw.resp.ready := !recv 72 73 XSPerfAccumulate("req_count", ptw.req(0).fire()) 74 XSPerfAccumulate("tlb_req_cycle", BoolStopWatch(req_in.fire(), tlb.resp.fire() || flush)) 75 XSPerfAccumulate("ptw_req_cycle", BoolStopWatch(ptw.req(0).fire(), ptw.resp.fire() || flush)) 76 77 XSDebug(haveOne, p"haveOne:${haveOne} sent:${sent} recv:${recv} sfence:${flush} req:${req} resp:${resp}") 78 XSDebug(req_in.valid || io.tlb.resp.valid, p"tlb: ${tlb}\n") 79 XSDebug(io.ptw.req(0).valid || io.ptw.resp.valid, p"ptw: ${ptw}\n") 80 assert(!RegNext(recv && io.ptw.resp.valid, init = false.B), "re-receive ptw.resp") 81 TimeOutAssert(sent && !recv, timeOutThreshold, "Repeater doesn't recv resp in time") 82} 83 84/* dtlb 85 * 86 */ 87 88class PTWRepeaterNB(Width: Int = 1, passReady: Boolean = false)(implicit p: Parameters) extends XSModule with HasPtwConst { 89 val io = IO(new PTWReapterIO(Width)) 90 91 val req_in = if (Width == 1) { 92 io.tlb.req(0) 93 } else { 94 val arb = Module(new RRArbiter(io.tlb.req(0).bits.cloneType, Width)) 95 arb.io.in <> io.tlb.req 96 arb.io.out 97 } 98 val (tlb, ptw, flush) = (io.tlb, io.ptw, RegNext(io.sfence.valid || io.csr.satp.changed)) 99 /* sent: tlb -> repeater -> ptw 100 * recv: ptw -> repeater -> tlb 101 * different from PTWRepeater 102 */ 103 104 // tlb -> repeater -> ptw 105 val req = RegEnable(req_in.bits, req_in.fire()) 106 val sent = BoolStopWatch(req_in.fire(), ptw.req(0).fire() || flush) 107 req_in.ready := !sent || { if (passReady) ptw.req(0).ready else false.B } 108 ptw.req(0).valid := sent 109 ptw.req(0).bits := req 110 111 // ptw -> repeater -> tlb 112 val resp = RegEnable(ptw.resp.bits, ptw.resp.fire()) 113 val recv = BoolStopWatch(ptw.resp.fire(), tlb.resp.fire() || flush) 114 ptw.resp.ready := !recv || { if (passReady) tlb.resp.ready else false.B } 115 tlb.resp.valid := recv 116 tlb.resp.bits := resp 117 118 XSPerfAccumulate("req", req_in.fire()) 119 XSPerfAccumulate("resp", tlb.resp.fire()) 120 if (!passReady) { 121 XSPerfAccumulate("req_blank", req_in.valid && sent && ptw.req(0).ready) 122 XSPerfAccumulate("resp_blank", ptw.resp.valid && recv && tlb.resp.ready) 123 XSPerfAccumulate("req_blank_ignore_ready", req_in.valid && sent) 124 XSPerfAccumulate("resp_blank_ignore_ready", ptw.resp.valid && recv) 125 } 126 XSDebug(req_in.valid || io.tlb.resp.valid, p"tlb: ${tlb}\n") 127 XSDebug(io.ptw.req(0).valid || io.ptw.resp.valid, p"ptw: ${ptw}\n") 128} 129 130class PTWFilterIO(Width: Int)(implicit p: Parameters) extends MMUIOBaseBundle { 131 val tlb = Flipped(new BTlbPtwIO(Width)) 132 val ptw = new TlbPtwIO() 133 134 def apply(tlb: BTlbPtwIO, ptw: TlbPtwIO, sfence: SfenceBundle, csr: TlbCsrBundle): Unit = { 135 this.tlb <> tlb 136 this.ptw <> ptw 137 this.sfence <> sfence 138 this.csr <> csr 139 } 140 141 def apply(tlb: BTlbPtwIO, sfence: SfenceBundle, csr: TlbCsrBundle): Unit = { 142 this.tlb <> tlb 143 this.sfence <> sfence 144 this.csr <> csr 145 } 146 147 override def cloneType: this.type = (new PTWFilterIO(Width)).asInstanceOf[this.type] 148} 149 150class PTWFilter(Width: Int, Size: Int)(implicit p: Parameters) extends XSModule with HasPtwConst { 151 require(Size >= Width) 152 153 val io = IO(new PTWFilterIO(Width)) 154 155 val v = RegInit(VecInit(Seq.fill(Size)(false.B))) 156 val ports = Reg(Vec(Size, Vec(Width, Bool()))) // record which port(s) the entry come from, may not able to cover all the ports 157 val vpn = Reg(Vec(Size, UInt(vpnLen.W))) 158 val enqPtr = RegInit(0.U(log2Up(Size).W)) // Enq 159 val issPtr = RegInit(0.U(log2Up(Size).W)) // Iss to Ptw 160 val deqPtr = RegInit(0.U(log2Up(Size).W)) // Deq 161 val mayFullDeq = RegInit(false.B) 162 val mayFullIss = RegInit(false.B) 163 val counter = RegInit(0.U(log2Up(Size+1).W)) 164 165 val flush = RegNext(io.sfence.valid || io.csr.satp.changed) 166 val tlb_req = WireInit(io.tlb.req) 167 tlb_req.suggestName("tlb_req") 168 169 val ptwResp = RegEnable(io.ptw.resp.bits, io.ptw.resp.fire()) 170 val ptwResp_OldMatchVec = vpn.zip(v).map{ case (pi, vi) => 171 vi && io.ptw.resp.bits.entry.hit(pi, io.csr.satp.asid, true, true)} 172 val ptwResp_valid = RegNext(io.ptw.resp.fire() && Cat(ptwResp_OldMatchVec).orR, init = false.B) 173 val oldMatchVec_early = io.tlb.req.map(a => vpn.zip(v).map{ case (pi, vi) => vi && pi === a.bits.vpn}) 174 val lastReqMatchVec_early = io.tlb.req.map(a => tlb_req.map{ b => b.valid && b.bits.vpn === a.bits.vpn}) 175 val newMatchVec_early = io.tlb.req.map(a => io.tlb.req.map(b => a.bits.vpn === b.bits.vpn)) 176 177 (0 until Width) foreach { i => 178 tlb_req(i).valid := RegNext(io.tlb.req(i).valid && 179 !(ptwResp_valid && ptwResp.entry.hit(io.tlb.req(i).bits.vpn, 0.U, true, true)) && 180 !Cat(lastReqMatchVec_early(i)).orR, 181 init = false.B) 182 tlb_req(i).bits := RegEnable(io.tlb.req(i).bits, io.tlb.req(i).valid) 183 } 184 185 val oldMatchVec = oldMatchVec_early.map(a => RegNext(Cat(a).orR)) 186 val newMatchVec = (0 until Width).map(i => (0 until Width).map(j => 187 RegNext(newMatchVec_early(i)(j)) && tlb_req(j).valid 188 )) 189 val ptwResp_newMatchVec = tlb_req.map(a => 190 ptwResp_valid && ptwResp.entry.hit(a.bits.vpn, 0.U, allType = true, true)) 191 192 val oldMatchVec2 = (0 until Width).map(i => oldMatchVec_early(i).map(RegNext(_)).map(_ & tlb_req(i).valid)) 193 val update_ports = v.indices.map(i => oldMatchVec2.map(j => j(i))) 194 val ports_init = (0 until Width).map(i => (1 << i).U(Width.W)) 195 val filter_ports = (0 until Width).map(i => ParallelMux(newMatchVec(i).zip(ports_init).drop(i))) 196 val resp_vector = RegEnable(ParallelMux(ptwResp_OldMatchVec zip ports), io.ptw.resp.fire()) 197 198 def canMerge(index: Int) : Bool = { 199 ptwResp_newMatchVec(index) || oldMatchVec(index) || 200 Cat(newMatchVec(index).take(index)).orR 201 } 202 203 def filter_req() = { 204 val reqs = tlb_req.indices.map{ i => 205 val req = Wire(ValidIO(new PtwReq())) 206 val merge = canMerge(i) 207 req.bits := tlb_req(i).bits 208 req.valid := !merge && tlb_req(i).valid 209 req 210 } 211 reqs 212 } 213 214 val reqs = filter_req() 215 val req_ports = filter_ports 216 val isFull = enqPtr === deqPtr && mayFullDeq 217 val isEmptyDeq = enqPtr === deqPtr && !mayFullDeq 218 val isEmptyIss = enqPtr === issPtr && !mayFullIss 219 val accumEnqNum = (0 until Width).map(i => PopCount(reqs.take(i).map(_.valid))) 220 val enqPtrVecInit = VecInit((0 until Width).map(i => enqPtr + i.U)) 221 val enqPtrVec = VecInit((0 until Width).map(i => enqPtrVecInit(accumEnqNum(i)))) 222 val enqNum = PopCount(reqs.map(_.valid)) 223 val canEnqueue = counter +& enqNum <= Size.U 224 225 io.tlb.req.map(_.ready := true.B) // NOTE: just drop un-fire reqs 226 io.tlb.resp.valid := ptwResp_valid 227 io.tlb.resp.bits.data := ptwResp 228 io.tlb.resp.bits.vector := resp_vector 229 io.ptw.req(0).valid := v(issPtr) && !isEmptyIss && !(ptwResp_valid && ptwResp.entry.hit(io.ptw.req(0).bits.vpn, io.csr.satp.asid, ignoreAsid = true)) 230 io.ptw.req(0).bits.vpn := vpn(issPtr) 231 io.ptw.resp.ready := true.B 232 233 reqs.zipWithIndex.map{ 234 case (req, i) => 235 when (req.valid && canEnqueue) { 236 v(enqPtrVec(i)) := true.B 237 vpn(enqPtrVec(i)) := req.bits.vpn 238 ports(enqPtrVec(i)) := req_ports(i).asBools 239 } 240 } 241 for (i <- ports.indices) { 242 when (v(i)) { 243 ports(i) := ports(i).zip(update_ports(i)).map(a => a._1 || a._2) 244 } 245 } 246 247 val do_enq = canEnqueue && Cat(reqs.map(_.valid)).orR 248 val do_deq = (!v(deqPtr) && !isEmptyDeq) 249 val do_iss = Mux(v(issPtr), io.ptw.req(0).fire(), !isEmptyIss) 250 when (do_enq) { 251 enqPtr := enqPtr + enqNum 252 } 253 when (do_deq) { 254 deqPtr := deqPtr + 1.U 255 } 256 when (do_iss) { 257 issPtr := issPtr + 1.U 258 } 259 when (do_enq =/= do_deq) { 260 mayFullDeq := do_enq 261 } 262 when (do_enq =/= do_iss) { 263 mayFullIss := do_enq 264 } 265 266 when (io.ptw.resp.fire()) { 267 v.zip(ptwResp_OldMatchVec).map{ case (vi, mi) => when (mi) { vi := false.B }} 268 } 269 270 counter := counter - do_deq + Mux(do_enq, enqNum, 0.U) 271 assert(counter <= Size.U, "counter should be less than Size") 272 when (counter === 0.U) { 273 assert(!io.ptw.req(0).fire(), "when counter is 0, should not req") 274 assert(isEmptyDeq && isEmptyIss, "when counter is 0, should be empty") 275 } 276 when (counter === Size.U) { 277 assert(mayFullDeq, "when counter is Size, should be full") 278 } 279 280 when (flush) { 281 v.map(_ := false.B) 282 deqPtr := 0.U 283 enqPtr := 0.U 284 issPtr := 0.U 285 ptwResp_valid := false.B 286 mayFullDeq := false.B 287 mayFullIss := false.B 288 counter := 0.U 289 } 290 291 // perf 292 val inflight_counter = RegInit(0.U(log2Up(Size + 1).W)) 293 when (io.ptw.req(0).fire() =/= io.ptw.resp.fire()) { 294 inflight_counter := Mux(io.ptw.req(0).fire(), inflight_counter + 1.U, inflight_counter - 1.U) 295 } 296 when (flush) { 297 inflight_counter := 0.U 298 } 299 XSPerfAccumulate("tlb_req_count", PopCount(Cat(io.tlb.req.map(_.valid)))) 300 XSPerfAccumulate("tlb_req_count_filtered", Mux(do_enq, accumEnqNum(Width - 1), 0.U)) 301 XSPerfAccumulate("ptw_req_count", io.ptw.req(0).fire()) 302 XSPerfAccumulate("ptw_req_cycle", inflight_counter) 303 XSPerfAccumulate("tlb_resp_count", io.tlb.resp.fire()) 304 XSPerfAccumulate("ptw_resp_count", io.ptw.resp.fire()) 305 XSPerfAccumulate("inflight_cycle", !isEmptyDeq) 306 for (i <- 0 until Size + 1) { 307 XSPerfAccumulate(s"counter${i}", counter === i.U) 308 } 309 310 for (i <- 0 until Size) { 311 TimeOutAssert(v(i), timeOutThreshold, s"Filter ${i} doesn't recv resp in time") 312 } 313} 314 315object PTWRepeater { 316 def apply( 317 tlb: TlbPtwIO, 318 sfence: SfenceBundle, 319 csr: TlbCsrBundle 320 )(implicit p: Parameters) = { 321 val width = tlb.req.size 322 val repeater = Module(new PTWRepeater(width)) 323 repeater.io.apply(tlb, sfence, csr) 324 repeater 325 } 326 327 def apply( 328 tlb: TlbPtwIO, 329 ptw: TlbPtwIO, 330 sfence: SfenceBundle, 331 csr: TlbCsrBundle 332 )(implicit p: Parameters) = { 333 val width = tlb.req.size 334 val repeater = Module(new PTWRepeater(width)) 335 repeater.io.apply(tlb, ptw, sfence, csr) 336 repeater 337 } 338} 339 340object PTWRepeaterNB { 341 def apply(passReady: Boolean, 342 tlb: TlbPtwIO, 343 sfence: SfenceBundle, 344 csr: TlbCsrBundle 345 )(implicit p: Parameters) = { 346 val width = tlb.req.size 347 val repeater = Module(new PTWRepeaterNB(width, passReady)) 348 repeater.io.apply(tlb, sfence, csr) 349 repeater 350 } 351 352 def apply(passReady: Boolean, 353 tlb: TlbPtwIO, 354 ptw: TlbPtwIO, 355 sfence: SfenceBundle, 356 csr: TlbCsrBundle 357 )(implicit p: Parameters) = { 358 val width = tlb.req.size 359 val repeater = Module(new PTWRepeaterNB(width, passReady)) 360 repeater.io.apply(tlb, ptw, sfence, csr) 361 repeater 362 } 363} 364 365object PTWFilter { 366 def apply( 367 tlb: BTlbPtwIO, 368 ptw: TlbPtwIO, 369 sfence: SfenceBundle, 370 csr: TlbCsrBundle, 371 size: Int 372 )(implicit p: Parameters) = { 373 val width = tlb.req.size 374 val filter = Module(new PTWFilter(width, size)) 375 filter.io.apply(tlb, ptw, sfence, csr) 376 filter 377 } 378 379 def apply( 380 tlb: BTlbPtwIO, 381 sfence: SfenceBundle, 382 csr: TlbCsrBundle, 383 size: Int 384 )(implicit p: Parameters) = { 385 val width = tlb.req.size 386 val filter = Module(new PTWFilter(width, size)) 387 filter.io.apply(tlb, sfence, csr) 388 filter 389 } 390 391}