1/*************************************************************************************** 2* Copyright (c) 2021-2025 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* Copyright (c) 2024-2025 Institute of Information Engineering, Chinese Academy of Sciences 6* 7* XiangShan is licensed under Mulan PSL v2. 8* You can use this software according to the terms and conditions of the Mulan PSL v2. 9* You may obtain a copy of Mulan PSL v2 at: 10* http://license.coscl.org.cn/MulanPSL2 11* 12* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 13* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 14* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 15* 16* See the Mulan PSL v2 for more details. 17***************************************************************************************/ 18 19package xiangshan.cache.mmu 20 21import org.chipsalliance.cde.config.Parameters 22import chisel3._ 23import chisel3.util._ 24import xiangshan._ 25import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 26import utils._ 27import utility._ 28import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 29import freechips.rocketchip.tilelink._ 30import xiangshan.backend.fu.{PMPReqBundle, PMPRespBundle} 31 32/** Page Table Walk is divided into two parts 33 * One, PTW: page walk for pde, except for leaf entries, one by one 34 * Two, LLPTW: page walk for pte, only the leaf entries(4KB), in parallel 35 */ 36 37 38/** PTW : page table walker 39 * a finite state machine 40 * only take 1GB and 2MB page walks 41 * or in other words, except the last level(leaf) 42 **/ 43class PTWIO()(implicit p: Parameters) extends MMUIOBaseBundle with HasPtwConst { 44 val req = Flipped(DecoupledIO(new Bundle { 45 val req_info = new L2TlbInnerBundle() 46 val l3Hit = if (EnableSv48) Some(new Bool()) else None 47 val l2Hit = Bool() 48 val ppn = UInt(ptePPNLen.W) 49 val stage1Hit = Bool() 50 val stage1 = new PtwMergeResp 51 val bitmapCheck = Option.when(HasBitmapCheck)(new Bundle { 52 val jmp_bitmap_check = Bool() // super page in PtwCache ptw hit, but need bitmap check 53 val pte = UInt(XLEN.W) // Page Table Entry 54 val cfs = Vec(tlbcontiguous, Bool()) // Bitmap Check Failed Vector 55 val SPlevel = UInt(log2Up(Level).W) 56 }) 57 })) 58 val resp = DecoupledIO(new Bundle { 59 val source = UInt(bSourceWidth.W) 60 val s2xlate = UInt(2.W) 61 val resp = new PtwMergeResp 62 val h_resp = new HptwResp 63 }) 64 65 val llptw = DecoupledIO(new LLPTWInBundle()) 66 // NOTE: llptw change from "connect to llptw" to "connect to page cache" 67 // to avoid corner case that caused duplicate entries 68 69 val hptw = new Bundle { 70 val req = DecoupledIO(new Bundle { 71 val source = UInt(bSourceWidth.W) 72 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 73 val gvpn = UInt(ptePPNLen.W) 74 }) 75 val resp = Flipped(Valid(new Bundle { 76 val h_resp = Output(new HptwResp) 77 })) 78 } 79 val mem = new Bundle { 80 val req = DecoupledIO(new L2TlbMemReqBundle()) 81 val resp = Flipped(ValidIO(UInt(XLEN.W))) 82 val mask = Input(Bool()) 83 } 84 val pmp = new Bundle { 85 val req = ValidIO(new PMPReqBundle()) 86 val resp = Flipped(new PMPRespBundle()) 87 } 88 89 val refill = Output(new Bundle { 90 val req_info = new L2TlbInnerBundle() 91 val level = UInt(log2Up(Level + 1).W) 92 }) 93 val bitmap = Option.when(HasBitmapCheck)(new Bundle { 94 val req = DecoupledIO(new bitmapReqBundle()) 95 val resp = Flipped(DecoupledIO(new bitmapRespBundle())) 96 }) 97} 98 99class PTW()(implicit p: Parameters) extends XSModule with HasPtwConst with HasPerfEvents { 100 val io = IO(new PTWIO) 101 val sfence = io.sfence 102 val mem = io.mem 103 val req_s2xlate = Reg(UInt(2.W)) 104 val enableS2xlate = req_s2xlate =/= noS2xlate 105 val onlyS1xlate = req_s2xlate === onlyStage1 106 val onlyS2xlate = req_s2xlate === onlyStage2 107 108 // mbmc:bitmap csr 109 val mbmc = io.csr.mbmc 110 val bitmap_enable = (if (HasBitmapCheck) true.B else false.B) && mbmc.BME === 1.U && mbmc.CMODE === 0.U 111 112 val satp = Wire(new TlbSatpBundle()) 113 when (io.req.fire) { 114 satp := Mux(io.req.bits.req_info.s2xlate =/= noS2xlate, io.csr.vsatp, io.csr.satp) 115 } .otherwise { 116 satp := Mux(enableS2xlate, io.csr.vsatp, io.csr.satp) 117 } 118 val s1Pbmte = Mux(req_s2xlate =/= noS2xlate, io.csr.hPBMTE, io.csr.mPBMTE) 119 120 val mode = satp.mode 121 val hgatp = io.csr.hgatp 122 val flush = io.sfence.valid || io.csr.satp.changed || io.csr.vsatp.changed || io.csr.hgatp.changed 123 val s2xlate = enableS2xlate && !onlyS1xlate 124 val level = RegInit(3.U(log2Up(Level + 1).W)) 125 val af_level = RegInit(3.U(log2Up(Level + 1).W)) // access fault return this level 126 val gpf_level = RegInit(3.U(log2Up(Level + 1).W)) 127 val ppn = Reg(UInt(ptePPNLen.W)) 128 val vpn = Reg(UInt(vpnLen.W)) // vpn or gvpn(onlyS2xlate) 129 val levelNext = level - 1.U 130 val l3Hit = Reg(Bool()) 131 val l2Hit = Reg(Bool()) 132 val jmp_bitmap_check_w = if (HasBitmapCheck) { io.req.bits.bitmapCheck.get.jmp_bitmap_check && io.req.bits.req_info.s2xlate =/= onlyStage2 } else { false.B } 133 val jmp_bitmap_check_r = if (HasBitmapCheck) { RegEnable(jmp_bitmap_check_w, io.req.fire) } else { false.B } 134 val cache_pte = Option.when(HasBitmapCheck)(RegEnable(io.req.bits.bitmapCheck.get.pte.asTypeOf(new PteBundle().cloneType), io.req.fire)) 135 val pte = if (HasBitmapCheck) { Mux(jmp_bitmap_check_r, cache_pte.get, io.mem.resp.bits.asTypeOf(new PteBundle().cloneType)) } else { mem.resp.bits.asTypeOf(new PteBundle()) } 136 137 // s/w register 138 val s_pmp_check = RegInit(true.B) 139 val s_mem_req = RegInit(true.B) 140 val s_llptw_req = RegInit(true.B) 141 val w_mem_resp = RegInit(true.B) 142 val s_hptw_req = RegInit(true.B) 143 val w_hptw_resp = RegInit(true.B) 144 val s_last_hptw_req = RegInit(true.B) 145 val w_last_hptw_resp = RegInit(true.B) 146 // for updating "level" 147 val mem_addr_update = RegInit(false.B) 148 149 val s_bitmap_check = RegInit(true.B) 150 val w_bitmap_resp = RegInit(true.B) 151 val whether_need_bitmap_check = RegInit(false.B) 152 val bitmap_checkfailed = RegInit(false.B) 153 154 val idle = RegInit(true.B) 155 val finish = WireInit(false.B) 156 157 val hptw_pageFault = RegInit(false.B) 158 val hptw_accessFault = RegInit(false.B) 159 val need_last_s2xlate = RegInit(false.B) 160 val stage1Hit = RegEnable(io.req.bits.stage1Hit, io.req.fire) 161 val stage1 = RegEnable(io.req.bits.stage1, io.req.fire) 162 val hptw_resp_stage2 = Reg(Bool()) 163 val first_gvpn_check_fail = RegInit(false.B) 164 165 // use accessfault repersent bitmap check failed 166 val pte_isAf = Mux(bitmap_enable, pte.isAf() || bitmap_checkfailed, pte.isAf()) 167 val ppn_af = if (HasBitmapCheck) { 168 Mux(enableS2xlate, Mux(onlyS1xlate, pte_isAf, false.B), pte_isAf) // In two-stage address translation, stage 1 ppn is a vpn for host, so don't need to check ppn_high 169 } else { 170 Mux(enableS2xlate, Mux(onlyS1xlate, pte.isAf(), false.B), pte.isAf()) // In two-stage address translation, stage 1 ppn is a vpn for host, so don't need to check ppn_high 171 } 172 val pte_valid = RegInit(false.B) // avoid l1tlb pf from stage1 when gpf happens in the first s2xlate in PTW 173 174 val pageFault = pte.isPf(level, s1Pbmte) 175 val find_pte = pte.isLeaf() || ppn_af || pageFault 176 val to_find_pte = level === 1.U && find_pte === false.B 177 val source = RegEnable(io.req.bits.req_info.source, io.req.fire) 178 179 val sent_to_pmp = idle === false.B && (s_pmp_check === false.B || mem_addr_update) && !finish && !(find_pte && pte_valid) 180 val accessFault = RegEnable(io.pmp.resp.ld || io.pmp.resp.mmio, false.B, sent_to_pmp) 181 182 val l3addr = Wire(UInt(ptePaddrLen.W)) 183 val l2addr = Wire(UInt(ptePaddrLen.W)) 184 val l1addr = Wire(UInt(ptePaddrLen.W)) 185 val hptw_addr = Wire(UInt(ptePaddrLen.W)) 186 val mem_addr = Wire(UInt(PAddrBits.W)) 187 188 l3addr := MakeAddr(satp.ppn, getVpnn(vpn, 3)) 189 if (EnableSv48) { 190 when (mode === Sv48) { 191 l2addr := MakeAddr(Mux(l3Hit, ppn, pte.getPPN()), getVpnn(vpn, 2)) 192 } .otherwise { 193 l2addr := MakeAddr(satp.ppn, getVpnn(vpn, 2)) 194 } 195 } else { 196 l2addr := MakeAddr(satp.ppn, getVpnn(vpn, 2)) 197 } 198 l1addr := MakeAddr(Mux(l2Hit, ppn, pte.getPPN()), getVpnn(vpn, 1)) 199 hptw_addr := Mux(af_level === 3.U, l3addr, Mux(af_level === 2.U, l2addr, l1addr)) 200 mem_addr := hptw_addr(PAddrBits - 1, 0) 201 202 val hptw_resp = Reg(new HptwResp) 203 204 val update_full_gvpn_mem_resp = RegInit(false.B) 205 val full_gvpn_reg = Reg(UInt(ptePPNLen.W)) 206 val full_gvpn_wire = pte.getPPN() 207 val full_gvpn = Mux(update_full_gvpn_mem_resp, full_gvpn_wire, full_gvpn_reg) 208 209 val gpaddr = MuxCase(hptw_addr, Seq( 210 (stage1Hit || onlyS2xlate) -> Cat(full_gvpn, 0.U(offLen.W)), 211 !s_last_hptw_req -> Cat(MuxLookup(level, pte.getPPN())(Seq( 212 3.U -> Cat(pte.getPPN()(ptePPNLen - 1, vpnnLen * 3), vpn(vpnnLen * 3 - 1, 0)), 213 2.U -> Cat(pte.getPPN()(ptePPNLen - 1, vpnnLen * 2), vpn(vpnnLen * 2 - 1, 0)), 214 1.U -> Cat(pte.getPPN()(ptePPNLen - 1, vpnnLen), vpn(vpnnLen - 1, 0) 215 ))), 216 0.U(offLen.W)) 217 )) 218 val gvpn_gpf = 219 (!(hptw_pageFault || hptw_accessFault || ((pageFault || ppn_af) && pte_valid)) && 220 Mux( 221 s2xlate && io.csr.hgatp.mode === Sv39x4, 222 full_gvpn(ptePPNLen - 1, GPAddrBitsSv39x4 - offLen) =/= 0.U, 223 Mux( 224 s2xlate && io.csr.hgatp.mode === Sv48x4, 225 full_gvpn(ptePPNLen - 1, GPAddrBitsSv48x4 - offLen) =/= 0.U, 226 false.B 227 ) 228 )) || first_gvpn_check_fail 229 230 val guestFault = hptw_pageFault || hptw_accessFault || gvpn_gpf 231 val hpaddr = Cat(hptw_resp.genPPNS2(get_pn(gpaddr)), get_off(gpaddr)) 232 val fake_h_resp = WireInit(0.U.asTypeOf(new HptwResp)) 233 fake_h_resp.entry.tag := get_pn(gpaddr) 234 fake_h_resp.entry.vmid.map(_ := io.csr.hgatp.vmid) 235 fake_h_resp.gpf := true.B 236 237 val fake_pte = WireInit(0.U.asTypeOf(new PteBundle())) 238 fake_pte.perm.v := false.B // tell L1TLB this is fake pte 239 fake_pte.ppn := ppn(ppnLen - 1, 0) 240 fake_pte.ppn_high := ppn(ptePPNLen - 1, ppnLen) 241 242 io.req.ready := idle 243 val ptw_resp = Wire(new PtwMergeResp) 244 ptw_resp.apply(Mux(pte_valid, pageFault && !accessFault, false.B), accessFault || (ppn_af && !(pte_valid && (pageFault || guestFault))), Mux(accessFault, af_level, Mux(guestFault, gpf_level, level)), Mux(pte_valid, pte, fake_pte), vpn, satp.asid, hgatp.vmid, vpn(sectortlbwidth - 1, 0), not_super = false, not_merge = false, bitmap_checkfailed.asBool) 245 246 val normal_resp = idle === false.B && mem_addr_update && !need_last_s2xlate && (guestFault || (w_mem_resp && find_pte) || (s_pmp_check && accessFault) || onlyS2xlate ) 247 val stageHit_resp = idle === false.B && hptw_resp_stage2 248 io.resp.valid := Mux(stage1Hit, stageHit_resp, normal_resp) 249 io.resp.bits.source := source 250 io.resp.bits.resp := Mux(stage1Hit || (l3Hit || l2Hit) && guestFault && !pte_valid, stage1, ptw_resp) 251 io.resp.bits.h_resp := Mux(gvpn_gpf, fake_h_resp, hptw_resp) 252 io.resp.bits.s2xlate := req_s2xlate 253 254 io.llptw.valid := s_llptw_req === false.B && to_find_pte && !accessFault && !guestFault 255 io.llptw.bits.req_info.source := source 256 io.llptw.bits.req_info.vpn := vpn 257 io.llptw.bits.req_info.s2xlate := req_s2xlate 258 io.llptw.bits.ppn := DontCare 259 if (HasBitmapCheck) { 260 io.llptw.bits.bitmapCheck.get.jmp_bitmap_check := DontCare 261 io.llptw.bits.bitmapCheck.get.ptes := DontCare 262 io.llptw.bits.bitmapCheck.get.cfs := DontCare 263 io.llptw.bits.bitmapCheck.get.hitway := DontCare 264 } 265 266 io.pmp.req.valid := DontCare // samecycle, do not use valid 267 io.pmp.req.bits.addr := Mux(s2xlate, hpaddr, mem_addr) 268 io.pmp.req.bits.size := 3.U // TODO: fix it 269 io.pmp.req.bits.cmd := TlbCmd.read 270 271 if (HasBitmapCheck) { 272 val cache_level = RegEnable(io.req.bits.bitmapCheck.get.SPlevel, io.req.fire) 273 io.bitmap.get.req.valid := !s_bitmap_check 274 io.bitmap.get.req.bits.bmppn := pte.ppn 275 io.bitmap.get.req.bits.id := FsmReqID.U(bMemID.W) 276 io.bitmap.get.req.bits.vpn := vpn 277 io.bitmap.get.req.bits.level := Mux(jmp_bitmap_check_r, cache_level, level) 278 io.bitmap.get.req.bits.way_info := DontCare 279 io.bitmap.get.req.bits.hptw_bypassed := false.B 280 io.bitmap.get.resp.ready := !w_bitmap_resp 281 } 282 mem.req.valid := s_mem_req === false.B && !mem.mask && !accessFault && s_pmp_check 283 mem.req.bits.addr := Mux(s2xlate, hpaddr, mem_addr) 284 mem.req.bits.id := FsmReqID.U(bMemID.W) 285 mem.req.bits.hptw_bypassed := false.B 286 287 io.refill.req_info.s2xlate := req_s2xlate 288 io.refill.req_info.vpn := vpn 289 io.refill.level := level 290 io.refill.req_info.source := source 291 292 io.hptw.req.valid := !s_hptw_req || !s_last_hptw_req 293 io.hptw.req.bits.id := FsmReqID.U(bMemID.W) 294 io.hptw.req.bits.gvpn := get_pn(gpaddr) 295 io.hptw.req.bits.source := source 296 297 if (HasBitmapCheck) { 298 when (io.req.fire && jmp_bitmap_check_w) { 299 idle := false.B 300 req_s2xlate := io.req.bits.req_info.s2xlate 301 vpn := io.req.bits.req_info.vpn 302 s_bitmap_check := false.B 303 need_last_s2xlate := false.B 304 hptw_pageFault := false.B 305 hptw_accessFault := false.B 306 level := io.req.bits.bitmapCheck.get.SPlevel 307 pte_valid := true.B 308 accessFault := false.B 309 } 310 } 311 312 when (io.req.fire && io.req.bits.stage1Hit && (if (HasBitmapCheck) !jmp_bitmap_check_w else true.B)) { 313 idle := false.B 314 req_s2xlate := io.req.bits.req_info.s2xlate 315 s_last_hptw_req := false.B 316 hptw_resp_stage2 := false.B 317 need_last_s2xlate := false.B 318 hptw_pageFault := false.B 319 hptw_accessFault := false.B 320 full_gvpn_reg := io.req.bits.stage1.genPPN() 321 } 322 323 when (io.resp.fire && stage1Hit){ 324 idle := true.B 325 } 326 327 when (io.req.fire && !io.req.bits.stage1Hit && (if (HasBitmapCheck) !jmp_bitmap_check_w else true.B)) { 328 val req = io.req.bits 329 val gvpn_wire = Wire(UInt(ptePPNLen.W)) 330 if (EnableSv48) { 331 when (mode === Sv48) { 332 level := Mux(req.l2Hit, 1.U, Mux(req.l3Hit.get, 2.U, 3.U)) 333 af_level := Mux(req.l2Hit, 1.U, Mux(req.l3Hit.get, 2.U, 3.U)) 334 gpf_level := Mux(req.l2Hit, 2.U, Mux(req.l3Hit.get, 3.U, 0.U)) 335 ppn := Mux(req.l2Hit || req.l3Hit.get, io.req.bits.ppn, satp.ppn) 336 l3Hit := req.l3Hit.get 337 gvpn_wire := Mux(req.l2Hit || req.l3Hit.get, io.req.bits.ppn, satp.ppn) 338 } .otherwise { 339 level := Mux(req.l2Hit, 1.U, 2.U) 340 af_level := Mux(req.l2Hit, 1.U, 2.U) 341 gpf_level := Mux(req.l2Hit, 2.U, 0.U) 342 ppn := Mux(req.l2Hit, io.req.bits.ppn, satp.ppn) 343 l3Hit := false.B 344 gvpn_wire := Mux(req.l2Hit, io.req.bits.ppn, satp.ppn) 345 } 346 } else { 347 level := Mux(req.l2Hit, 1.U, 2.U) 348 af_level := Mux(req.l2Hit, 1.U, 2.U) 349 gpf_level := Mux(req.l2Hit, 2.U, 0.U) 350 ppn := Mux(req.l2Hit, io.req.bits.ppn, satp.ppn) 351 l3Hit := false.B 352 gvpn_wire := Mux(req.l2Hit, io.req.bits.ppn, satp.ppn) 353 } 354 vpn := io.req.bits.req_info.vpn 355 l2Hit := req.l2Hit 356 accessFault := false.B 357 idle := false.B 358 hptw_pageFault := false.B 359 hptw_accessFault := false.B 360 pte_valid := false.B 361 req_s2xlate := io.req.bits.req_info.s2xlate 362 when(io.req.bits.req_info.s2xlate === onlyStage2){ 363 full_gvpn_reg := io.req.bits.req_info.vpn 364 val onlys2_gpaddr = Cat(io.req.bits.req_info.vpn, 0.U(offLen.W)) // is 50 bits, don't need to check high bits when sv48x4 is enabled 365 val check_gpa_high_fail = Mux(io.req.bits.req_info.s2xlate === onlyStage2 && io.csr.hgatp.mode === Sv39x4, onlys2_gpaddr(onlys2_gpaddr.getWidth - 1, GPAddrBitsSv39x4) =/= 0.U, false.B) 366 need_last_s2xlate := false.B 367 when(check_gpa_high_fail){ 368 mem_addr_update := true.B 369 first_gvpn_check_fail := true.B 370 }.otherwise{ 371 s_last_hptw_req := false.B 372 } 373 }.elsewhen(io.req.bits.req_info.s2xlate === allStage){ 374 full_gvpn_reg := 0.U 375 val allstage_gpaddr = Cat(gvpn_wire, 0.U(offLen.W)) 376 val check_gpa_high_fail = Mux(io.csr.hgatp.mode === Sv39x4, allstage_gpaddr(allstage_gpaddr.getWidth - 1, GPAddrBitsSv39x4) =/= 0.U, Mux(io.csr.hgatp.mode === Sv48x4, allstage_gpaddr(allstage_gpaddr.getWidth - 1, GPAddrBitsSv48x4) =/= 0.U, false.B)) 377 when(check_gpa_high_fail){ 378 mem_addr_update := true.B 379 first_gvpn_check_fail := true.B 380 }.otherwise{ 381 need_last_s2xlate := true.B 382 s_hptw_req := false.B 383 } 384 }.otherwise { 385 full_gvpn_reg := 0.U 386 need_last_s2xlate := false.B 387 s_pmp_check := false.B 388 } 389 } 390 391 when(io.hptw.req.fire && s_hptw_req === false.B){ 392 s_hptw_req := true.B 393 w_hptw_resp := false.B 394 } 395 396 when(io.hptw.resp.fire && w_hptw_resp === false.B) { 397 w_hptw_resp := true.B 398 val g_perm_fail = !io.hptw.resp.bits.h_resp.gaf && (!io.hptw.resp.bits.h_resp.entry.perm.get.r && !(io.csr.priv.mxr && io.hptw.resp.bits.h_resp.entry.perm.get.x)) 399 hptw_pageFault := io.hptw.resp.bits.h_resp.gpf || g_perm_fail 400 hptw_accessFault := io.hptw.resp.bits.h_resp.gaf 401 hptw_resp := io.hptw.resp.bits.h_resp 402 hptw_resp.gpf := io.hptw.resp.bits.h_resp.gpf || g_perm_fail 403 when(!(g_perm_fail || io.hptw.resp.bits.h_resp.gpf || io.hptw.resp.bits.h_resp.gaf)) { 404 s_pmp_check := false.B 405 }.otherwise { 406 mem_addr_update := true.B 407 need_last_s2xlate := false.B 408 } 409 } 410 411 when(io.hptw.req.fire && s_last_hptw_req === false.B) { 412 w_last_hptw_resp := false.B 413 s_last_hptw_req := true.B 414 } 415 416 when (io.hptw.resp.fire && w_last_hptw_resp === false.B && stage1Hit){ 417 w_last_hptw_resp := true.B 418 hptw_resp_stage2 := true.B 419 hptw_resp := io.hptw.resp.bits.h_resp 420 } 421 422 when(io.hptw.resp.fire && w_last_hptw_resp === false.B && !stage1Hit){ 423 hptw_pageFault := io.hptw.resp.bits.h_resp.gpf 424 hptw_accessFault := io.hptw.resp.bits.h_resp.gaf 425 hptw_resp := io.hptw.resp.bits.h_resp 426 w_last_hptw_resp := true.B 427 mem_addr_update := true.B 428 } 429 430 when(sent_to_pmp && mem_addr_update === false.B){ 431 s_mem_req := false.B 432 s_pmp_check := true.B 433 } 434 435 when(accessFault && !io.hptw.req.valid && idle === false.B){ 436 s_pmp_check := true.B 437 s_mem_req := true.B 438 w_mem_resp := true.B 439 s_llptw_req := true.B 440 s_hptw_req := true.B 441 w_hptw_resp := true.B 442 s_last_hptw_req := true.B 443 w_last_hptw_resp := true.B 444 mem_addr_update := true.B 445 need_last_s2xlate := false.B 446 if (HasBitmapCheck) { 447 s_bitmap_check := true.B 448 w_bitmap_resp := true.B 449 whether_need_bitmap_check := false.B 450 bitmap_checkfailed := false.B 451 } 452 } 453 454 when(guestFault && idle === false.B){ 455 s_pmp_check := true.B 456 s_mem_req := true.B 457 w_mem_resp := true.B 458 s_llptw_req := true.B 459 s_hptw_req := true.B 460 w_hptw_resp := true.B 461 s_last_hptw_req := true.B 462 w_last_hptw_resp := true.B 463 mem_addr_update := true.B 464 need_last_s2xlate := false.B 465 if (HasBitmapCheck) { 466 s_bitmap_check := true.B 467 w_bitmap_resp := true.B 468 whether_need_bitmap_check := false.B 469 bitmap_checkfailed := false.B 470 } 471 } 472 473 when (mem.req.fire){ 474 s_mem_req := true.B 475 w_mem_resp := false.B 476 } 477 478 when(mem.resp.fire && w_mem_resp === false.B){ 479 w_mem_resp := true.B 480 af_level := af_level - 1.U 481 gpf_level := Mux(mode === Sv39 && !pte_valid && !l2Hit, gpf_level - 2.U, gpf_level - 1.U) 482 pte_valid := true.B 483 update_full_gvpn_mem_resp := true.B 484 if (HasBitmapCheck) { 485 when (bitmap_enable) { 486 whether_need_bitmap_check := true.B 487 } .otherwise { 488 s_llptw_req := false.B 489 mem_addr_update := true.B 490 whether_need_bitmap_check := false.B 491 } 492 } else { 493 s_llptw_req := false.B 494 mem_addr_update := true.B 495 } 496 } 497 498 when(update_full_gvpn_mem_resp) { 499 update_full_gvpn_mem_resp := false.B 500 full_gvpn_reg := pte.getPPN() 501 } 502 503 if (HasBitmapCheck) { 504 when (whether_need_bitmap_check) { 505 when (bitmap_enable && (!enableS2xlate || onlyS1xlate) && pte.isLeaf()) { 506 s_bitmap_check := false.B 507 whether_need_bitmap_check := false.B 508 } .otherwise { 509 mem_addr_update := true.B 510 s_llptw_req := false.B 511 whether_need_bitmap_check := false.B 512 } 513 } 514 // bitmapcheck 515 when (io.bitmap.get.req.fire) { 516 s_bitmap_check := true.B 517 w_bitmap_resp := false.B 518 } 519 when (io.bitmap.get.resp.fire) { 520 w_bitmap_resp := true.B 521 mem_addr_update := true.B 522 bitmap_checkfailed := io.bitmap.get.resp.bits.cf 523 } 524 } 525 526 when(mem_addr_update){ 527 when(level >= 2.U && !onlyS2xlate && !(guestFault || find_pte || accessFault)) { 528 level := levelNext 529 when(s2xlate){ 530 s_hptw_req := false.B 531 }.otherwise{ 532 s_mem_req := false.B 533 } 534 s_llptw_req := true.B 535 mem_addr_update := false.B 536 }.elsewhen(io.llptw.valid){ 537 when(io.llptw.fire) { 538 idle := true.B 539 s_llptw_req := true.B 540 mem_addr_update := false.B 541 need_last_s2xlate := false.B 542 } 543 finish := true.B 544 }.elsewhen(s2xlate && need_last_s2xlate === true.B) { 545 need_last_s2xlate := false.B 546 when(!(guestFault || accessFault || pageFault || ppn_af)){ 547 s_last_hptw_req := false.B 548 mem_addr_update := false.B 549 } 550 }.elsewhen(io.resp.valid){ 551 when(io.resp.fire) { 552 idle := true.B 553 s_llptw_req := true.B 554 mem_addr_update := false.B 555 accessFault := false.B 556 first_gvpn_check_fail := false.B 557 } 558 finish := true.B 559 } 560 } 561 562 563 when (flush) { 564 idle := true.B 565 s_pmp_check := true.B 566 s_mem_req := true.B 567 s_llptw_req := true.B 568 w_mem_resp := true.B 569 accessFault := false.B 570 mem_addr_update := false.B 571 first_gvpn_check_fail := false.B 572 s_hptw_req := true.B 573 w_hptw_resp := true.B 574 s_last_hptw_req := true.B 575 w_last_hptw_resp := true.B 576 if (HasBitmapCheck) { 577 s_bitmap_check := true.B 578 w_bitmap_resp := true.B 579 whether_need_bitmap_check := false.B 580 bitmap_checkfailed := false.B 581 } 582 } 583 584 585 XSDebug(p"[ptw] level:${level} notFound:${pageFault}\n") 586 587 // perf 588 XSPerfAccumulate("fsm_count", io.req.fire) 589 for (i <- 0 until PtwWidth) { 590 XSPerfAccumulate(s"fsm_count_source${i}", io.req.fire && io.req.bits.req_info.source === i.U) 591 } 592 XSPerfAccumulate("fsm_busy", !idle) 593 XSPerfAccumulate("fsm_idle", idle) 594 XSPerfAccumulate("resp_blocked", io.resp.valid && !io.resp.ready) 595 XSPerfAccumulate("ptw_ppn_af", io.resp.fire && ppn_af) 596 XSPerfAccumulate("mem_count", mem.req.fire) 597 XSPerfAccumulate("mem_cycle", BoolStopWatch(mem.req.fire, mem.resp.fire, true)) 598 XSPerfAccumulate("mem_blocked", mem.req.valid && !mem.req.ready) 599 600 val perfEvents = Seq( 601 ("fsm_count ", io.req.fire ), 602 ("fsm_busy ", !idle ), 603 ("fsm_idle ", idle ), 604 ("resp_blocked ", io.resp.valid && !io.resp.ready ), 605 ("mem_count ", mem.req.fire ), 606 ("mem_cycle ", BoolStopWatch(mem.req.fire, mem.resp.fire, true)), 607 ("mem_blocked ", mem.req.valid && !mem.req.ready ), 608 ) 609 generatePerfEvent() 610} 611 612/*========================= LLPTW ==============================*/ 613 614/** LLPTW : Last Level Page Table Walker 615 * the page walker that only takes 4KB(last level) page walk. 616 **/ 617 618class LLPTWInBundle(implicit p: Parameters) extends XSBundle with HasPtwConst { 619 val req_info = Output(new L2TlbInnerBundle()) 620 val ppn = Output(UInt(ptePPNLen.W)) 621 val bitmapCheck = Option.when(HasBitmapCheck)(new Bundle { 622 val jmp_bitmap_check = Bool() // find pte in l0 or sp, but need bitmap check 623 val ptes = Vec(tlbcontiguous, UInt(XLEN.W)) // Page Table Entry Vector 624 val cfs = Vec(tlbcontiguous, Bool()) // Bitmap Check Failed Vector 625 val hitway = UInt(l2tlbParams.l0nWays.W) 626 }) 627} 628 629class LLPTWIO(implicit p: Parameters) extends MMUIOBaseBundle with HasPtwConst { 630 val in = Flipped(DecoupledIO(new LLPTWInBundle())) 631 val out = DecoupledIO(new Bundle { 632 val req_info = Output(new L2TlbInnerBundle()) 633 val id = Output(UInt(bMemID.W)) 634 val h_resp = Output(new HptwResp) 635 val first_s2xlate_fault = Output(Bool()) // Whether the first stage 2 translation occurs pf/af 636 val af = Output(Bool()) 637 val bitmapCheck = Option.when(HasBitmapCheck)(new Bundle { 638 val jmp_bitmap_check = Bool() // find pte in l0 or sp, but need bitmap check 639 val ptes = Vec(tlbcontiguous, UInt(XLEN.W)) // Page Table Entry Vector 640 val cfs = Vec(tlbcontiguous, Bool()) // Bitmap Check Failed Vector 641 }) 642 }) 643 val mem = new Bundle { 644 val req = DecoupledIO(new L2TlbMemReqBundle()) 645 val resp = Flipped(Valid(new Bundle { 646 val id = Output(UInt(log2Up(l2tlbParams.llptwsize).W)) 647 val value = Output(UInt(blockBits.W)) 648 })) 649 val enq_ptr = Output(UInt(log2Ceil(l2tlbParams.llptwsize).W)) 650 val buffer_it = Output(Vec(l2tlbParams.llptwsize, Bool())) 651 val refill = Output(new L2TlbInnerBundle()) 652 val req_mask = Input(Vec(l2tlbParams.llptwsize, Bool())) 653 val flush_latch = Input(Vec(l2tlbParams.llptwsize, Bool())) 654 } 655 val cache = DecoupledIO(new L2TlbInnerBundle()) 656 val pmp = new Bundle { 657 val req = Valid(new PMPReqBundle()) 658 val resp = Flipped(new PMPRespBundle()) 659 } 660 val hptw = new Bundle { 661 val req = DecoupledIO(new Bundle{ 662 val source = UInt(bSourceWidth.W) 663 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 664 val gvpn = UInt(ptePPNLen.W) 665 }) 666 val resp = Flipped(Valid(new Bundle { 667 val id = Output(UInt(log2Up(l2tlbParams.llptwsize).W)) 668 val h_resp = Output(new HptwResp) 669 })) 670 } 671 val bitmap = Option.when(HasBitmapCheck)(new Bundle { 672 val req = DecoupledIO(new bitmapReqBundle()) 673 val resp = Flipped(DecoupledIO(new bitmapRespBundle())) 674 }) 675 676 val l0_way_info = Option.when(HasBitmapCheck)(Input(UInt(l2tlbParams.l0nWays.W))) 677} 678 679class LLPTWEntry(implicit p: Parameters) extends XSBundle with HasPtwConst { 680 val req_info = new L2TlbInnerBundle() 681 val ppn = UInt(ptePPNLen.W) 682 val wait_id = UInt(log2Up(l2tlbParams.llptwsize).W) 683 val af = Bool() 684 val hptw_resp = new HptwResp() 685 val first_s2xlate_fault = Output(Bool()) 686 val cf = Bool() 687 val from_l0 = Bool() 688 val way_info = UInt(l2tlbParams.l0nWays.W) 689 val jmp_bitmap_check = Bool() 690 val ptes = Vec(tlbcontiguous, UInt(XLEN.W)) 691 val cfs = Vec(tlbcontiguous, Bool()) 692} 693 694 695class LLPTW(implicit p: Parameters) extends XSModule with HasPtwConst with HasPerfEvents { 696 val io = IO(new LLPTWIO()) 697 val enableS2xlate = io.in.bits.req_info.s2xlate =/= noS2xlate 698 val satp = Mux(enableS2xlate, io.csr.vsatp, io.csr.satp) 699 val s1Pbmte = Mux(enableS2xlate, io.csr.hPBMTE, io.csr.mPBMTE) 700 701 // mbmc:bitmap csr 702 val mbmc = io.csr.mbmc 703 val bitmap_enable = (if (HasBitmapCheck) true.B else false.B) && mbmc.BME === 1.U && mbmc.CMODE === 0.U 704 705 val flush = io.sfence.valid || io.csr.satp.changed || io.csr.vsatp.changed || io.csr.hgatp.changed 706 val entries = RegInit(VecInit(Seq.fill(l2tlbParams.llptwsize)(0.U.asTypeOf(new LLPTWEntry())))) 707 val state_idle :: state_hptw_req :: state_hptw_resp :: state_addr_check :: state_mem_req :: state_mem_waiting :: state_mem_out :: state_last_hptw_req :: state_last_hptw_resp :: state_cache :: state_bitmap_check :: state_bitmap_resp :: Nil = Enum(12) 708 val state = RegInit(VecInit(Seq.fill(l2tlbParams.llptwsize)(state_idle))) 709 710 val is_emptys = state.map(_ === state_idle) 711 val is_mems = state.map(_ === state_mem_req) 712 val is_waiting = state.map(_ === state_mem_waiting) 713 val is_having = state.map(_ === state_mem_out) 714 val is_cache = state.map(_ === state_cache) 715 val is_hptw_req = state.map(_ === state_hptw_req) 716 val is_last_hptw_req = state.map(_ === state_last_hptw_req) 717 val is_hptw_resp = state.map(_ === state_hptw_resp) 718 val is_last_hptw_resp = state.map(_ === state_last_hptw_resp) 719 val is_bitmap_req = state.map(_ === state_bitmap_check) 720 val is_bitmap_resp = state.map(_ === state_bitmap_resp) 721 722 val full = !ParallelOR(is_emptys).asBool 723 val enq_ptr = ParallelPriorityEncoder(is_emptys) 724 725 val mem_ptr = ParallelPriorityEncoder(is_having) // TODO: optimize timing, bad: entries -> ptr -> entry 726 val mem_arb = Module(new RRArbiterInit(new LLPTWEntry(), l2tlbParams.llptwsize)) 727 for (i <- 0 until l2tlbParams.llptwsize) { 728 mem_arb.io.in(i).bits := entries(i) 729 mem_arb.io.in(i).valid := is_mems(i) && !io.mem.req_mask(i) 730 } 731 732 // process hptw requests in serial 733 val hyper_arb1 = Module(new RRArbiterInit(new LLPTWEntry(), l2tlbParams.llptwsize)) 734 for (i <- 0 until l2tlbParams.llptwsize) { 735 hyper_arb1.io.in(i).bits := entries(i) 736 hyper_arb1.io.in(i).valid := is_hptw_req(i) && !(Cat(is_hptw_resp).orR) && !(Cat(is_last_hptw_resp).orR) 737 } 738 val hyper_arb2 = Module(new RRArbiterInit(new LLPTWEntry(), l2tlbParams.llptwsize)) 739 for(i <- 0 until l2tlbParams.llptwsize) { 740 hyper_arb2.io.in(i).bits := entries(i) 741 hyper_arb2.io.in(i).valid := is_last_hptw_req(i) && !(Cat(is_hptw_resp).orR) && !(Cat(is_last_hptw_resp).orR) 742 } 743 744 745 val bitmap_arb = Option.when(HasBitmapCheck)(Module(new RRArbiter(new bitmapReqBundle(), l2tlbParams.llptwsize))) 746 val way_info = Option.when(HasBitmapCheck)(Wire(Vec(l2tlbParams.llptwsize, UInt(l2tlbParams.l0nWays.W)))) 747 if (HasBitmapCheck) { 748 for (i <- 0 until l2tlbParams.llptwsize) { 749 bitmap_arb.get.io.in(i).valid := is_bitmap_req(i) 750 bitmap_arb.get.io.in(i).bits.bmppn := entries(i).ppn 751 bitmap_arb.get.io.in(i).bits.vpn := entries(i).req_info.vpn 752 bitmap_arb.get.io.in(i).bits.id := i.U 753 bitmap_arb.get.io.in(i).bits.level := 0.U // last level 754 bitmap_arb.get.io.in(i).bits.way_info := Mux(entries(i).from_l0, entries(i).way_info, way_info.get(i)) 755 bitmap_arb.get.io.in(i).bits.hptw_bypassed := false.B 756 } 757 } 758 759 val cache_ptr = ParallelMux(is_cache, (0 until l2tlbParams.llptwsize).map(_.U(log2Up(l2tlbParams.llptwsize).W))) 760 761 // duplicate req 762 // to_wait: wait for the last to access mem, set to mem_resp 763 // to_cache: the last is back just right now, set to mem_cache 764 val dup_vec = state.indices.map(i => 765 dup(io.in.bits.req_info.vpn, entries(i).req_info.vpn) && io.in.bits.req_info.s2xlate === entries(i).req_info.s2xlate 766 ) 767 val dup_req_fire = mem_arb.io.out.fire && dup(io.in.bits.req_info.vpn, mem_arb.io.out.bits.req_info.vpn) && io.in.bits.req_info.s2xlate === mem_arb.io.out.bits.req_info.s2xlate // dup with the req fire entry 768 val dup_vec_wait = dup_vec.zip(is_waiting).map{case (d, w) => d && w} // dup with "mem_waiting" entries, sending mem req already 769 val dup_vec_having = dup_vec.zipWithIndex.map{case (d, i) => d && is_having(i)} // dup with the "mem_out" entry recv the data just now 770 val dup_vec_bitmap = dup_vec.zipWithIndex.map{case (d, i) => d && (is_bitmap_req(i) || is_bitmap_resp(i))} 771 val dup_vec_last_hptw = dup_vec.zipWithIndex.map{case (d, i) => d && (is_last_hptw_req(i) || is_last_hptw_resp(i))} 772 val wait_id = Mux(dup_req_fire, mem_arb.io.chosen, ParallelMux(dup_vec_wait zip entries.map(_.wait_id))) 773 val dup_wait_resp = io.mem.resp.fire && VecInit(dup_vec_wait)(io.mem.resp.bits.id) && !io.mem.flush_latch(io.mem.resp.bits.id) // dup with the entry that data coming next cycle 774 val to_wait = Cat(dup_vec_wait).orR || dup_req_fire 775 val to_mem_out = dup_wait_resp && ((entries(io.mem.resp.bits.id).req_info.s2xlate === noS2xlate) || (entries(io.mem.resp.bits.id).req_info.s2xlate === onlyStage1)) && !bitmap_enable 776 val to_bitmap_req = (if (HasBitmapCheck) true.B else false.B) && dup_wait_resp && ((entries(io.mem.resp.bits.id).req_info.s2xlate === noS2xlate) || (entries(io.mem.resp.bits.id).req_info.s2xlate === onlyStage1)) && bitmap_enable 777 val to_cache = if (HasBitmapCheck) Cat(dup_vec_bitmap).orR || Cat(dup_vec_having).orR || Cat(dup_vec_last_hptw).orR 778 else Cat(dup_vec_having).orR || Cat(dup_vec_last_hptw).orR 779 val to_hptw_req = io.in.bits.req_info.s2xlate === allStage 780 val to_last_hptw_req = dup_wait_resp && entries(io.mem.resp.bits.id).req_info.s2xlate === allStage 781 val last_hptw_req_id = io.mem.resp.bits.id 782 val req_paddr = MakeAddr(io.in.bits.ppn(ppnLen-1, 0), getVpnn(io.in.bits.req_info.vpn, 0)) 783 val req_hpaddr = MakeAddr(entries(last_hptw_req_id).hptw_resp.genPPNS2(get_pn(req_paddr)), getVpnn(io.in.bits.req_info.vpn, 0)) 784 val index = Mux(entries(last_hptw_req_id).req_info.s2xlate === allStage, req_hpaddr, req_paddr)(log2Up(l2tlbParams.blockBytes)-1, log2Up(XLEN/8)) 785 val last_hptw_req_ppn = io.mem.resp.bits.value.asTypeOf(Vec(blockBits / XLEN, new PteBundle()))(index).getPPN() 786 XSError(RegNext(dup_req_fire && Cat(dup_vec_wait).orR, init = false.B), "mem req but some entries already waiting, should not happed") 787 788 XSError(io.in.fire && ((to_mem_out && to_cache) || (to_wait && to_cache)), "llptw enq, to cache conflict with to mem") 789 val mem_resp_hit = RegInit(VecInit(Seq.fill(l2tlbParams.llptwsize)(false.B))) 790 val enq_state_normal = MuxCase(state_addr_check, Seq( 791 to_mem_out -> state_mem_out, // same to the blew, but the mem resp now 792 to_bitmap_req -> state_bitmap_check, 793 to_last_hptw_req -> state_last_hptw_req, 794 to_wait -> state_mem_waiting, 795 to_cache -> state_cache, 796 to_hptw_req -> state_hptw_req 797 )) 798 val enq_state = Mux(from_pre(io.in.bits.req_info.source) && enq_state_normal =/= state_addr_check, state_idle, enq_state_normal) 799 when (io.in.fire && (if (HasBitmapCheck) !io.in.bits.bitmapCheck.get.jmp_bitmap_check else true.B)) { 800 // if prefetch req does not need mem access, just give it up. 801 // so there will be at most 1 + FilterSize entries that needs re-access page cache 802 // so 2 + FilterSize is enough to avoid dead-lock 803 state(enq_ptr) := enq_state 804 entries(enq_ptr).req_info := io.in.bits.req_info 805 entries(enq_ptr).ppn := Mux(to_last_hptw_req, last_hptw_req_ppn, io.in.bits.ppn) 806 entries(enq_ptr).wait_id := Mux(to_wait, wait_id, enq_ptr) 807 entries(enq_ptr).af := false.B 808 if (HasBitmapCheck) { 809 entries(enq_ptr).cf := false.B 810 entries(enq_ptr).from_l0 := false.B 811 entries(enq_ptr).way_info := 0.U 812 entries(enq_ptr).jmp_bitmap_check := false.B 813 for (i <- 0 until tlbcontiguous) { 814 entries(enq_ptr).ptes(i) := 0.U 815 } 816 entries(enq_ptr).cfs := io.in.bits.bitmapCheck.get.cfs 817 } 818 entries(enq_ptr).hptw_resp := Mux(to_last_hptw_req, entries(last_hptw_req_id).hptw_resp, Mux(to_wait, entries(wait_id).hptw_resp, entries(enq_ptr).hptw_resp)) 819 entries(enq_ptr).first_s2xlate_fault := false.B 820 mem_resp_hit(enq_ptr) := to_bitmap_req || to_mem_out || to_last_hptw_req 821 } 822 823 if (HasBitmapCheck) { 824 when (io.in.bits.bitmapCheck.get.jmp_bitmap_check && io.in.fire) { 825 state(enq_ptr) := state_bitmap_check 826 entries(enq_ptr).req_info := io.in.bits.req_info 827 entries(enq_ptr).ppn := io.in.bits.bitmapCheck.get.ptes(io.in.bits.req_info.vpn(sectortlbwidth - 1, 0)).asTypeOf(new PteBundle().cloneType).ppn 828 entries(enq_ptr).wait_id := enq_ptr 829 entries(enq_ptr).af := false.B 830 entries(enq_ptr).cf := false.B 831 entries(enq_ptr).from_l0 := true.B 832 entries(enq_ptr).way_info := io.in.bits.bitmapCheck.get.hitway 833 entries(enq_ptr).jmp_bitmap_check := io.in.bits.bitmapCheck.get.jmp_bitmap_check 834 entries(enq_ptr).ptes := io.in.bits.bitmapCheck.get.ptes 835 entries(enq_ptr).cfs := io.in.bits.bitmapCheck.get.cfs 836 mem_resp_hit(enq_ptr) := false.B 837 } 838 } 839 840 val enq_ptr_reg = RegNext(enq_ptr) 841 val need_addr_check = GatedValidRegNext(enq_state === state_addr_check && io.in.fire && !flush && (if (HasBitmapCheck) !io.in.bits.bitmapCheck.get.jmp_bitmap_check else true.B)) 842 843 val hasHptwResp = ParallelOR(state.map(_ === state_hptw_resp)).asBool 844 val hptw_resp_ptr_reg = RegNext(io.hptw.resp.bits.id) 845 val hptw_need_addr_check = RegNext(hasHptwResp && io.hptw.resp.fire && !flush) && state(hptw_resp_ptr_reg) === state_addr_check 846 847 val ptes = io.mem.resp.bits.value.asTypeOf(Vec(blockBits / XLEN, new PteBundle())) 848 val gpaddr = MakeGPAddr(entries(hptw_resp_ptr_reg).ppn, getVpnn(entries(hptw_resp_ptr_reg).req_info.vpn, 0)) 849 val hptw_resp = entries(hptw_resp_ptr_reg).hptw_resp 850 val hpaddr = Cat(hptw_resp.genPPNS2(get_pn(gpaddr)), get_off(gpaddr)) 851 val addr = RegEnable(MakeAddr(io.in.bits.ppn(ppnLen - 1, 0), getVpnn(io.in.bits.req_info.vpn, 0)), io.in.fire) 852 io.pmp.req.valid := need_addr_check || hptw_need_addr_check 853 io.pmp.req.bits.addr := Mux(hptw_need_addr_check, hpaddr, addr) 854 io.pmp.req.bits.cmd := TlbCmd.read 855 io.pmp.req.bits.size := 3.U // TODO: fix it 856 val pmp_resp_valid = io.pmp.req.valid // same cycle 857 when (pmp_resp_valid) { 858 // NOTE: when pmp resp but state is not addr check, then the entry is dup with other entry, the state was changed before 859 // when dup with the req-ing entry, set to mem_waiting (above codes), and the ld must be false, so dontcare 860 val ptr = Mux(hptw_need_addr_check, hptw_resp_ptr_reg, enq_ptr_reg); 861 val accessFault = io.pmp.resp.ld || io.pmp.resp.mmio 862 entries(ptr).af := accessFault 863 state(ptr) := Mux(accessFault, state_mem_out, state_mem_req) 864 } 865 866 when (mem_arb.io.out.fire) { 867 for (i <- state.indices) { 868 when (state(i) =/= state_idle && state(i) =/= state_mem_out && state(i) =/= state_last_hptw_req && state(i) =/= state_last_hptw_resp 869 && (if (HasBitmapCheck) state(i) =/= state_bitmap_check && state(i) =/= state_bitmap_resp else true.B) 870 && entries(i).req_info.s2xlate === mem_arb.io.out.bits.req_info.s2xlate 871 && dup(entries(i).req_info.vpn, mem_arb.io.out.bits.req_info.vpn)) { 872 // NOTE: "dup enq set state to mem_wait" -> "sending req set other dup entries to mem_wait" 873 state(i) := state_mem_waiting 874 entries(i).hptw_resp := entries(mem_arb.io.chosen).hptw_resp 875 entries(i).wait_id := mem_arb.io.chosen 876 } 877 } 878 } 879 when (io.mem.resp.fire) { 880 state.indices.map{i => 881 when (state(i) === state_mem_waiting && io.mem.resp.bits.id === entries(i).wait_id) { 882 val req_paddr = MakeAddr(entries(i).ppn, getVpnn(entries(i).req_info.vpn, 0)) 883 val req_hpaddr = MakeAddr(entries(i).hptw_resp.genPPNS2(get_pn(req_paddr)), getVpnn(entries(i).req_info.vpn, 0)) 884 val index = Mux(entries(i).req_info.s2xlate === allStage, req_hpaddr, req_paddr)(log2Up(l2tlbParams.blockBytes)-1, log2Up(XLEN/8)) 885 val allStageExcp = ptes(index).isPf(0.U, s1Pbmte) || !ptes(index).isLeaf() || ptes(index).isStage1Gpf(io.csr.hgatp.mode) 886 state(i) := Mux((entries(i).req_info.s2xlate === allStage && !allStageExcp), 887 state_last_hptw_req, 888 Mux(bitmap_enable, state_bitmap_check, state_mem_out)) 889 mem_resp_hit(i) := true.B 890 entries(i).ppn := Mux(ptes(index).n === 0.U, ptes(index).getPPN(), Cat(ptes(index).getPPN()(ptePPNLen - 1, pteNapotBits), entries(i).req_info.vpn(pteNapotBits - 1, 0))) // for last stage 2 translation 891 // af will be judged in L2 TLB `contiguous_pte_to_merge_ptwResp` 892 entries(i).hptw_resp.gpf := Mux(entries(i).req_info.s2xlate === allStage, ptes(index).isStage1Gpf(io.csr.hgatp.mode), false.B) 893 } 894 } 895 } 896 897 if (HasBitmapCheck) { 898 for (i <- 0 until l2tlbParams.llptwsize) { 899 way_info.get(i) := DataHoldBypass(io.l0_way_info.get, mem_resp_hit(i)) 900 } 901 } 902 903 when (hyper_arb1.io.out.fire) { 904 for (i <- state.indices) { 905 when (state(i) === state_hptw_req && entries(i).ppn === hyper_arb1.io.out.bits.ppn && entries(i).req_info.s2xlate === allStage && hyper_arb1.io.chosen === i.U) { 906 state(i) := state_hptw_resp 907 entries(i).wait_id := hyper_arb1.io.chosen 908 } 909 } 910 } 911 912 when (hyper_arb2.io.out.fire) { 913 for (i <- state.indices) { 914 when (state(i) === state_last_hptw_req && entries(i).ppn === hyper_arb2.io.out.bits.ppn && entries(i).req_info.s2xlate === allStage && hyper_arb2.io.chosen === i.U) { 915 state(i) := state_last_hptw_resp 916 entries(i).wait_id := hyper_arb2.io.chosen 917 } 918 } 919 } 920 921 if (HasBitmapCheck) { 922 when (bitmap_arb.get.io.out.fire) { 923 for (i <- state.indices) { 924 when (is_bitmap_req(i) && bitmap_arb.get.io.out.bits.bmppn === entries(i).ppn(ppnLen - 1, 0)) { 925 state(i) := state_bitmap_resp 926 entries(i).wait_id := bitmap_arb.get.io.chosen 927 } 928 } 929 } 930 931 when (io.bitmap.get.resp.fire) { 932 for (i <- state.indices) { 933 when (is_bitmap_resp(i) && io.bitmap.get.resp.bits.id === entries(i).wait_id) { 934 entries(i).cfs := io.bitmap.get.resp.bits.cfs 935 entries(i).cf := io.bitmap.get.resp.bits.cf 936 state(i) := state_mem_out 937 } 938 } 939 } 940 } 941 942 when (io.hptw.resp.fire) { 943 for (i <- state.indices) { 944 when (state(i) === state_hptw_resp && io.hptw.resp.bits.id === entries(i).wait_id && io.hptw.resp.bits.h_resp.entry.tag === entries(i).ppn) { 945 val check_g_perm_fail = !io.hptw.resp.bits.h_resp.gaf && (!io.hptw.resp.bits.h_resp.entry.perm.get.r && !(io.csr.priv.mxr && io.hptw.resp.bits.h_resp.entry.perm.get.x)) 946 when (check_g_perm_fail || io.hptw.resp.bits.h_resp.gaf || io.hptw.resp.bits.h_resp.gpf) { 947 state(i) := state_mem_out 948 entries(i).hptw_resp := io.hptw.resp.bits.h_resp 949 entries(i).hptw_resp.gpf := io.hptw.resp.bits.h_resp.gpf || check_g_perm_fail 950 entries(i).first_s2xlate_fault := io.hptw.resp.bits.h_resp.gaf || io.hptw.resp.bits.h_resp.gpf 951 }.otherwise{ // change the entry that is waiting hptw resp 952 val need_to_waiting_vec = state.indices.map(i => state(i) === state_mem_waiting && dup(entries(i).req_info.vpn, entries(io.hptw.resp.bits.id).req_info.vpn)) 953 val waiting_index = ParallelMux(need_to_waiting_vec zip entries.map(_.wait_id)) 954 state(i) := Mux(Cat(need_to_waiting_vec).orR, state_mem_waiting, state_addr_check) 955 entries(i).hptw_resp := io.hptw.resp.bits.h_resp 956 entries(i).wait_id := Mux(Cat(need_to_waiting_vec).orR, waiting_index, entries(i).wait_id) 957 //To do: change the entry that is having the same hptw req 958 } 959 } 960 when (state(i) === state_last_hptw_resp && io.hptw.resp.bits.id === entries(i).wait_id && io.hptw.resp.bits.h_resp.entry.tag === entries(i).ppn) { 961 state(i) := state_mem_out 962 entries(i).hptw_resp := io.hptw.resp.bits.h_resp 963 //To do: change the entry that is having the same hptw req 964 } 965 } 966 } 967 when (io.out.fire) { 968 assert(state(mem_ptr) === state_mem_out) 969 state(mem_ptr) := state_idle 970 } 971 mem_resp_hit.map(a => when (a) { a := false.B } ) 972 973 when (io.cache.fire) { 974 state(cache_ptr) := state_idle 975 } 976 XSError(io.out.fire && io.cache.fire && (mem_ptr === cache_ptr), "mem resp and cache fire at the same time at same entry") 977 978 when (flush) { 979 state.map(_ := state_idle) 980 } 981 982 io.in.ready := !full 983 984 io.out.valid := ParallelOR(is_having).asBool 985 io.out.bits.req_info := entries(mem_ptr).req_info 986 io.out.bits.id := mem_ptr 987 if (HasBitmapCheck) { 988 io.out.bits.af := Mux(bitmap_enable, entries(mem_ptr).af || entries(mem_ptr).cf, entries(mem_ptr).af) 989 io.out.bits.bitmapCheck.get.jmp_bitmap_check := entries(mem_ptr).jmp_bitmap_check 990 io.out.bits.bitmapCheck.get.ptes := entries(mem_ptr).ptes 991 io.out.bits.bitmapCheck.get.cfs := entries(mem_ptr).cfs 992 } else { 993 io.out.bits.af := entries(mem_ptr).af 994 } 995 996 io.out.bits.h_resp := entries(mem_ptr).hptw_resp 997 io.out.bits.first_s2xlate_fault := entries(mem_ptr).first_s2xlate_fault 998 999 val hptw_req_arb = Module(new Arbiter(new Bundle{ 1000 val source = UInt(bSourceWidth.W) 1001 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 1002 val ppn = UInt(ptePPNLen.W) 1003 } , 2)) 1004 // first stage 2 translation 1005 hptw_req_arb.io.in(0).valid := hyper_arb1.io.out.valid 1006 hptw_req_arb.io.in(0).bits.source := hyper_arb1.io.out.bits.req_info.source 1007 hptw_req_arb.io.in(0).bits.ppn := hyper_arb1.io.out.bits.ppn 1008 hptw_req_arb.io.in(0).bits.id := hyper_arb1.io.chosen 1009 hyper_arb1.io.out.ready := hptw_req_arb.io.in(0).ready 1010 // last stage 2 translation 1011 hptw_req_arb.io.in(1).valid := hyper_arb2.io.out.valid 1012 hptw_req_arb.io.in(1).bits.source := hyper_arb2.io.out.bits.req_info.source 1013 hptw_req_arb.io.in(1).bits.ppn := hyper_arb2.io.out.bits.ppn 1014 hptw_req_arb.io.in(1).bits.id := hyper_arb2.io.chosen 1015 hyper_arb2.io.out.ready := hptw_req_arb.io.in(1).ready 1016 hptw_req_arb.io.out.ready := io.hptw.req.ready 1017 io.hptw.req.valid := hptw_req_arb.io.out.fire && !flush 1018 io.hptw.req.bits.gvpn := hptw_req_arb.io.out.bits.ppn 1019 io.hptw.req.bits.id := hptw_req_arb.io.out.bits.id 1020 io.hptw.req.bits.source := hptw_req_arb.io.out.bits.source 1021 1022 io.mem.req.valid := mem_arb.io.out.valid && !flush 1023 val mem_paddr = MakeAddr(mem_arb.io.out.bits.ppn, getVpnn(mem_arb.io.out.bits.req_info.vpn, 0)) 1024 val mem_hpaddr = MakeAddr(mem_arb.io.out.bits.hptw_resp.genPPNS2(get_pn(mem_paddr)), getVpnn(mem_arb.io.out.bits.req_info.vpn, 0)) 1025 io.mem.req.bits.addr := Mux(mem_arb.io.out.bits.req_info.s2xlate === allStage, mem_hpaddr, mem_paddr) 1026 io.mem.req.bits.id := mem_arb.io.chosen 1027 io.mem.req.bits.hptw_bypassed := false.B 1028 mem_arb.io.out.ready := io.mem.req.ready 1029 val mem_refill_id = RegNext(io.mem.resp.bits.id(log2Up(l2tlbParams.llptwsize)-1, 0)) 1030 io.mem.refill := entries(mem_refill_id).req_info 1031 io.mem.refill.s2xlate := entries(mem_refill_id).req_info.s2xlate 1032 io.mem.buffer_it := mem_resp_hit 1033 io.mem.enq_ptr := enq_ptr 1034 1035 io.cache.valid := Cat(is_cache).orR 1036 io.cache.bits := ParallelMux(is_cache, entries.map(_.req_info)) 1037 1038 val has_bitmap_resp = ParallelOR(is_bitmap_resp).asBool 1039 if (HasBitmapCheck) { 1040 io.bitmap.get.req.valid := bitmap_arb.get.io.out.valid && !flush 1041 io.bitmap.get.req.bits.bmppn := bitmap_arb.get.io.out.bits.bmppn 1042 io.bitmap.get.req.bits.id := bitmap_arb.get.io.chosen 1043 io.bitmap.get.req.bits.vpn := bitmap_arb.get.io.out.bits.vpn 1044 io.bitmap.get.req.bits.level := 0.U 1045 io.bitmap.get.req.bits.way_info := bitmap_arb.get.io.out.bits.way_info 1046 io.bitmap.get.req.bits.hptw_bypassed := bitmap_arb.get.io.out.bits.hptw_bypassed 1047 bitmap_arb.get.io.out.ready := io.bitmap.get.req.ready 1048 io.bitmap.get.resp.ready := has_bitmap_resp 1049 } 1050 1051 XSPerfAccumulate("llptw_in_count", io.in.fire) 1052 XSPerfAccumulate("llptw_in_block", io.in.valid && !io.in.ready) 1053 for (i <- 0 until 7) { 1054 XSPerfAccumulate(s"enq_state${i}", io.in.fire && enq_state === i.U) 1055 } 1056 for (i <- 0 until (l2tlbParams.llptwsize + 1)) { 1057 XSPerfAccumulate(s"util${i}", PopCount(is_emptys.map(!_)) === i.U) 1058 XSPerfAccumulate(s"mem_util${i}", PopCount(is_mems) === i.U) 1059 XSPerfAccumulate(s"waiting_util${i}", PopCount(is_waiting) === i.U) 1060 } 1061 XSPerfAccumulate("mem_count", io.mem.req.fire) 1062 XSPerfAccumulate("mem_cycle", PopCount(is_waiting) =/= 0.U) 1063 XSPerfAccumulate("blocked_in", io.in.valid && !io.in.ready) 1064 1065 val perfEvents = Seq( 1066 ("tlbllptw_incount ", io.in.fire ), 1067 ("tlbllptw_inblock ", io.in.valid && !io.in.ready), 1068 ("tlbllptw_memcount ", io.mem.req.fire ), 1069 ("tlbllptw_memcycle ", PopCount(is_waiting) ), 1070 ) 1071 generatePerfEvent() 1072} 1073 1074/*========================= HPTW ==============================*/ 1075 1076/** HPTW : Hypervisor Page Table Walker 1077 * the page walker take the virtual machine's page walk. 1078 * guest physical address translation, guest physical address -> host physical address 1079 **/ 1080class HPTWIO()(implicit p: Parameters) extends MMUIOBaseBundle with HasPtwConst { 1081 val req = Flipped(DecoupledIO(new Bundle { 1082 val source = UInt(bSourceWidth.W) 1083 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 1084 val gvpn = UInt(gvpnLen.W) 1085 val ppn = UInt(ppnLen.W) 1086 val l3Hit = if (EnableSv48) Some(new Bool()) else None 1087 val l2Hit = Bool() 1088 val l1Hit = Bool() 1089 val bypassed = Bool() // if bypass, don't refill 1090 val bitmapCheck = Option.when(HasBitmapCheck)(new Bundle { 1091 val jmp_bitmap_check = Bool() // find pte in l0 or sp, but need bitmap check 1092 val pte = UInt(XLEN.W) // Page Table Entry 1093 val ptes = Vec(tlbcontiguous, UInt(XLEN.W)) // Page Table Entry Vector 1094 val cfs = Vec(tlbcontiguous, Bool()) // Bitmap Check Failed Vector 1095 val hitway = UInt(l2tlbParams.l0nWays.W) 1096 val fromSP = Bool() 1097 val SPlevel = UInt(log2Up(Level).W) 1098 }) 1099 })) 1100 val resp = DecoupledIO(new Bundle { 1101 val source = UInt(bSourceWidth.W) 1102 val resp = Output(new HptwResp()) 1103 val id = Output(UInt(bMemID.W)) 1104 }) 1105 1106 val mem = new Bundle { 1107 val req = DecoupledIO(new L2TlbMemReqBundle()) 1108 val resp = Flipped(ValidIO(UInt(XLEN.W))) 1109 val mask = Input(Bool()) 1110 } 1111 val refill = Output(new Bundle { 1112 val req_info = new L2TlbInnerBundle() 1113 val level = UInt(log2Up(Level + 1).W) 1114 }) 1115 val pmp = new Bundle { 1116 val req = ValidIO(new PMPReqBundle()) 1117 val resp = Flipped(new PMPRespBundle()) 1118 } 1119 val bitmap = Option.when(HasBitmapCheck)(new Bundle { 1120 val req = DecoupledIO(new bitmapReqBundle()) 1121 val resp = Flipped(DecoupledIO(new bitmapRespBundle())) 1122 }) 1123 1124 val l0_way_info = Option.when(HasBitmapCheck)(Input(UInt(l2tlbParams.l0nWays.W))) 1125} 1126 1127class HPTW()(implicit p: Parameters) extends XSModule with HasPtwConst { 1128 val io = IO(new HPTWIO) 1129 val hgatp = io.csr.hgatp 1130 val mpbmte = io.csr.mPBMTE 1131 val sfence = io.sfence 1132 val flush = sfence.valid || hgatp.changed || io.csr.satp.changed || io.csr.vsatp.changed 1133 val mode = hgatp.mode 1134 1135 // mbmc:bitmap csr 1136 val mbmc = io.csr.mbmc 1137 val bitmap_enable = (if (HasBitmapCheck) true.B else false.B) && mbmc.BME === 1.U && mbmc.CMODE === 0.U 1138 1139 val level = RegInit(3.U(log2Up(Level + 1).W)) 1140 val af_level = RegInit(3.U(log2Up(Level + 1).W)) // access fault return this level 1141 val gpaddr = Reg(UInt(GPAddrBits.W)) 1142 val req_ppn = Reg(UInt(ppnLen.W)) 1143 val vpn = gpaddr(GPAddrBits-1, offLen) 1144 val levelNext = level - 1.U 1145 val l3Hit = Reg(Bool()) 1146 val l2Hit = Reg(Bool()) 1147 val l1Hit = Reg(Bool()) 1148 val bypassed = Reg(Bool()) 1149// val pte = io.mem.resp.bits.MergeRespToPte() 1150 val jmp_bitmap_check = if (HasBitmapCheck) RegEnable(io.req.bits.bitmapCheck.get.jmp_bitmap_check, io.req.fire) else false.B 1151 val fromSP = if (HasBitmapCheck) RegEnable(io.req.bits.bitmapCheck.get.fromSP, io.req.fire) else false.B 1152 val cache_pte = Option.when(HasBitmapCheck)(RegEnable(Mux(io.req.bits.bitmapCheck.get.fromSP, io.req.bits.bitmapCheck.get.pte.asTypeOf(new PteBundle().cloneType), io.req.bits.bitmapCheck.get.ptes(io.req.bits.gvpn(sectortlbwidth - 1, 0)).asTypeOf(new PteBundle().cloneType)), io.req.fire)) 1153 val pte = if (HasBitmapCheck) Mux(jmp_bitmap_check, cache_pte.get, io.mem.resp.bits.asTypeOf(new PteBundle().cloneType)) else io.mem.resp.bits.asTypeOf(new PteBundle().cloneType) 1154 val ppn_l3 = Mux(l3Hit, req_ppn, pte.ppn) 1155 val ppn_l2 = Mux(l2Hit, req_ppn, pte.ppn) 1156 val ppn_l1 = Mux(l1Hit, req_ppn, pte.ppn) 1157 val ppn = Wire(UInt(PAddrBits.W)) 1158 val p_pte = MakeAddr(ppn, getVpnn(vpn, level)) 1159 val pg_base = Wire(UInt(PAddrBits.W)) 1160 val mem_addr = Wire(UInt(PAddrBits.W)) 1161 if (EnableSv48) { 1162 when (mode === Sv48) { 1163 ppn := Mux(af_level === 2.U, ppn_l3, Mux(af_level === 1.U, ppn_l2, ppn_l1)) // for l2, l1 and l3 1164 pg_base := MakeGPAddr(hgatp.ppn, getGVpnn(vpn, 3.U, mode = Sv48)) // for l3 1165 mem_addr := Mux(af_level === 3.U, pg_base, p_pte) 1166 } .otherwise { 1167 ppn := Mux(af_level === 1.U, ppn_l2, ppn_l1) //for l1 and l2 1168 pg_base := MakeGPAddr(hgatp.ppn, getGVpnn(vpn, 2.U, mode = Sv39)) 1169 mem_addr := Mux(af_level === 2.U, pg_base, p_pte) 1170 } 1171 } else { 1172 ppn := Mux(af_level === 1.U, ppn_l2, ppn_l1) //for l1 and l2 1173 pg_base := MakeGPAddr(hgatp.ppn, getGVpnn(vpn, 2.U, mode = Sv39)) 1174 mem_addr := Mux(af_level === 2.U, pg_base, p_pte) 1175 } 1176 1177 //s/w register 1178 val s_pmp_check = RegInit(true.B) 1179 val s_mem_req = RegInit(true.B) 1180 val w_mem_resp = RegInit(true.B) 1181 val idle = RegInit(true.B) 1182 val mem_addr_update = RegInit(false.B) 1183 val finish = WireInit(false.B) 1184 val s_bitmap_check = RegInit(true.B) 1185 val w_bitmap_resp = RegInit(true.B) 1186 val whether_need_bitmap_check = RegInit(false.B) 1187 val bitmap_checkfailed = RegInit(false.B) 1188 1189 val sent_to_pmp = !idle && (!s_pmp_check || mem_addr_update) && !finish 1190 val pageFault = pte.isGpf(level, mpbmte) || (!pte.isLeaf() && level === 0.U) 1191 val accessFault = RegEnable(io.pmp.resp.ld || io.pmp.resp.mmio, sent_to_pmp) 1192 1193 // use access fault when bitmap check failed 1194 val ppn_af = if (HasBitmapCheck) { 1195 Mux(bitmap_enable, pte.isAf() || bitmap_checkfailed, pte.isAf()) 1196 } else { 1197 pte.isAf() 1198 } 1199 val find_pte = pte.isLeaf() || ppn_af || pageFault 1200 1201 val resp_valid = !idle && mem_addr_update && ((w_mem_resp && find_pte) || (s_pmp_check && accessFault)) 1202 val id = Reg(UInt(log2Up(l2tlbParams.llptwsize).W)) 1203 val source = RegEnable(io.req.bits.source, io.req.fire) 1204 1205 io.req.ready := idle 1206 val resp = Wire(new HptwResp()) 1207 // accessFault > pageFault > ppn_af 1208 resp.apply( 1209 gpf = pageFault && !accessFault, 1210 gaf = accessFault || (ppn_af && !pageFault), 1211 level = Mux(accessFault, af_level, level), 1212 pte = pte, 1213 vpn = vpn, 1214 vmid = hgatp.vmid 1215 ) 1216 io.resp.valid := resp_valid 1217 io.resp.bits.id := id 1218 io.resp.bits.resp := resp 1219 io.resp.bits.source := source 1220 1221 io.pmp.req.valid := DontCare 1222 io.pmp.req.bits.addr := mem_addr 1223 io.pmp.req.bits.size := 3.U 1224 io.pmp.req.bits.cmd := TlbCmd.read 1225 1226 if (HasBitmapCheck) { 1227 val way_info = DataHoldBypass(io.l0_way_info.get, RegNext(io.mem.resp.fire, init=false.B)) 1228 val cache_hitway = RegEnable(io.req.bits.bitmapCheck.get.hitway, io.req.fire) 1229 val cache_level = RegEnable(io.req.bits.bitmapCheck.get.SPlevel, io.req.fire) 1230 io.bitmap.get.req.valid := !s_bitmap_check 1231 io.bitmap.get.req.bits.bmppn := pte.ppn 1232 io.bitmap.get.req.bits.id := HptwReqId.U(bMemID.W) 1233 io.bitmap.get.req.bits.vpn := vpn 1234 io.bitmap.get.req.bits.level := Mux(jmp_bitmap_check, Mux(fromSP,cache_level,0.U), level) 1235 io.bitmap.get.req.bits.way_info := Mux(jmp_bitmap_check, cache_hitway, way_info) 1236 io.bitmap.get.req.bits.hptw_bypassed := bypassed 1237 io.bitmap.get.resp.ready := !w_bitmap_resp 1238 } 1239 1240 io.mem.req.valid := !s_mem_req && !io.mem.mask && !accessFault && s_pmp_check 1241 io.mem.req.bits.addr := mem_addr 1242 io.mem.req.bits.id := HptwReqId.U(bMemID.W) 1243 io.mem.req.bits.hptw_bypassed := bypassed 1244 1245 io.refill.req_info.vpn := vpn 1246 io.refill.level := level 1247 io.refill.req_info.source := source 1248 io.refill.req_info.s2xlate := onlyStage2 1249 1250 when (idle){ 1251 if (HasBitmapCheck) { 1252 when (io.req.bits.bitmapCheck.get.jmp_bitmap_check && io.req.fire) { 1253 idle := false.B 1254 gpaddr := Cat(io.req.bits.gvpn, 0.U(offLen.W)) 1255 s_bitmap_check := false.B 1256 id := io.req.bits.id 1257 level := Mux(io.req.bits.bitmapCheck.get.fromSP, io.req.bits.bitmapCheck.get.SPlevel, 0.U) 1258 } 1259 } 1260 when (io.req.fire && (if (HasBitmapCheck) !io.req.bits.bitmapCheck.get.jmp_bitmap_check else true.B)) { 1261 bypassed := io.req.bits.bypassed 1262 idle := false.B 1263 gpaddr := Cat(io.req.bits.gvpn, 0.U(offLen.W)) 1264 accessFault := false.B 1265 s_pmp_check := false.B 1266 id := io.req.bits.id 1267 req_ppn := io.req.bits.ppn 1268 if (EnableSv48) { 1269 when (mode === Sv48) { 1270 level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, Mux(io.req.bits.l3Hit.get, 2.U, 3.U))) 1271 af_level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, Mux(io.req.bits.l3Hit.get, 2.U, 3.U))) 1272 l3Hit := io.req.bits.l3Hit.get 1273 } .otherwise { 1274 level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, 2.U)) 1275 af_level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, 2.U)) 1276 l3Hit := false.B 1277 } 1278 } else { 1279 level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, 2.U)) 1280 af_level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, 2.U)) 1281 l3Hit := false.B 1282 } 1283 l2Hit := io.req.bits.l2Hit 1284 l1Hit := io.req.bits.l1Hit 1285 } 1286 } 1287 1288 when(sent_to_pmp && !mem_addr_update){ 1289 s_mem_req := false.B 1290 s_pmp_check := true.B 1291 } 1292 1293 when(accessFault && !idle){ 1294 s_pmp_check := true.B 1295 s_mem_req := true.B 1296 w_mem_resp := true.B 1297 mem_addr_update := true.B 1298 if (HasBitmapCheck) { 1299 s_bitmap_check := true.B 1300 w_bitmap_resp := true.B 1301 whether_need_bitmap_check := false.B 1302 bitmap_checkfailed := false.B 1303 } 1304 } 1305 1306 when(io.mem.req.fire){ 1307 s_mem_req := true.B 1308 w_mem_resp := false.B 1309 } 1310 1311 when(io.mem.resp.fire && !w_mem_resp){ 1312 w_mem_resp := true.B 1313 af_level := af_level - 1.U 1314 if (HasBitmapCheck) { 1315 when (bitmap_enable) { 1316 whether_need_bitmap_check := true.B 1317 } .otherwise { 1318 mem_addr_update := true.B 1319 whether_need_bitmap_check := false.B 1320 } 1321 } else { 1322 mem_addr_update := true.B 1323 } 1324 } 1325 1326 if (HasBitmapCheck) { 1327 when (whether_need_bitmap_check) { 1328 when (bitmap_enable && pte.isLeaf()) { 1329 s_bitmap_check := false.B 1330 whether_need_bitmap_check := false.B 1331 } .otherwise { 1332 mem_addr_update := true.B 1333 whether_need_bitmap_check := false.B 1334 } 1335 } 1336 // bitmapcheck 1337 when (io.bitmap.get.req.fire) { 1338 s_bitmap_check := true.B 1339 w_bitmap_resp := false.B 1340 } 1341 when (io.bitmap.get.resp.fire) { 1342 w_bitmap_resp := true.B 1343 mem_addr_update := true.B 1344 bitmap_checkfailed := io.bitmap.get.resp.bits.cf 1345 } 1346 } 1347 1348 when(mem_addr_update){ 1349 when(!(find_pte || accessFault)){ 1350 level := levelNext 1351 s_mem_req := false.B 1352 mem_addr_update := false.B 1353 }.elsewhen(resp_valid){ 1354 when(io.resp.fire){ 1355 idle := true.B 1356 mem_addr_update := false.B 1357 accessFault := false.B 1358 } 1359 finish := true.B 1360 } 1361 } 1362 when (flush) { 1363 idle := true.B 1364 s_pmp_check := true.B 1365 s_mem_req := true.B 1366 w_mem_resp := true.B 1367 accessFault := false.B 1368 mem_addr_update := false.B 1369 if (HasBitmapCheck) { 1370 s_bitmap_check := true.B 1371 w_bitmap_resp := true.B 1372 whether_need_bitmap_check := false.B 1373 bitmap_checkfailed := false.B 1374 } 1375 } 1376} 1377