1/*************************************************************************************** 2* Copyright (c) 2021-2025 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* Copyright (c) 2024-2025 Institute of Information Engineering, Chinese Academy of Sciences 6* 7* XiangShan is licensed under Mulan PSL v2. 8* You can use this software according to the terms and conditions of the Mulan PSL v2. 9* You may obtain a copy of Mulan PSL v2 at: 10* http://license.coscl.org.cn/MulanPSL2 11* 12* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 13* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 14* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 15* 16* See the Mulan PSL v2 for more details. 17***************************************************************************************/ 18 19package xiangshan.cache.mmu 20 21import org.chipsalliance.cde.config.Parameters 22import chisel3._ 23import chisel3.util._ 24import xiangshan._ 25import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 26import utils._ 27import utility._ 28import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 29import freechips.rocketchip.tilelink._ 30import xiangshan.backend.fu.{PMPReqBundle, PMPRespBundle} 31 32/** Page Table Walk is divided into two parts 33 * One, PTW: page walk for pde, except for leaf entries, one by one 34 * Two, LLPTW: page walk for pte, only the leaf entries(4KB), in parallel 35 */ 36 37 38/** PTW : page table walker 39 * a finite state machine 40 * only take 1GB and 2MB page walks 41 * or in other words, except the last level(leaf) 42 **/ 43class PTWIO()(implicit p: Parameters) extends MMUIOBaseBundle with HasPtwConst { 44 val req = Flipped(DecoupledIO(new Bundle { 45 val req_info = new L2TlbInnerBundle() 46 val l3Hit = if (EnableSv48) Some(new Bool()) else None 47 val l2Hit = Bool() 48 val ppn = UInt(ptePPNLen.W) 49 val stage1Hit = Bool() 50 val stage1 = new PtwMergeResp 51 val bitmapCheck = Option.when(HasBitmapCheck)(new Bundle { 52 val jmp_bitmap_check = Bool() // super page in PtwCache ptw hit, but need bitmap check 53 val pte = UInt(XLEN.W) // Page Table Entry 54 val cfs = Vec(tlbcontiguous, Bool()) // Bitmap Check Failed Vector 55 val SPlevel = UInt(log2Up(Level).W) 56 }) 57 })) 58 val resp = DecoupledIO(new Bundle { 59 val source = UInt(bSourceWidth.W) 60 val s2xlate = UInt(2.W) 61 val resp = new PtwMergeResp 62 val h_resp = new HptwResp 63 }) 64 65 val llptw = DecoupledIO(new LLPTWInBundle()) 66 // NOTE: llptw change from "connect to llptw" to "connect to page cache" 67 // to avoid corner case that caused duplicate entries 68 69 val hptw = new Bundle { 70 val req = DecoupledIO(new Bundle { 71 val source = UInt(bSourceWidth.W) 72 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 73 val gvpn = UInt(ptePPNLen.W) 74 }) 75 val resp = Flipped(Valid(new Bundle { 76 val h_resp = Output(new HptwResp) 77 })) 78 } 79 val mem = new Bundle { 80 val req = DecoupledIO(new L2TlbMemReqBundle()) 81 val resp = Flipped(ValidIO(UInt(XLEN.W))) 82 val mask = Input(Bool()) 83 } 84 val pmp = new Bundle { 85 val req = ValidIO(new PMPReqBundle()) 86 val resp = Flipped(new PMPRespBundle()) 87 } 88 89 val refill = Output(new Bundle { 90 val req_info = new L2TlbInnerBundle() 91 val level = UInt(log2Up(Level + 1).W) 92 }) 93 val bitmap = Option.when(HasBitmapCheck)(new Bundle { 94 val req = DecoupledIO(new bitmapReqBundle()) 95 val resp = Flipped(DecoupledIO(new bitmapRespBundle())) 96 }) 97} 98 99class PTW()(implicit p: Parameters) extends XSModule with HasPtwConst with HasPerfEvents { 100 val io = IO(new PTWIO) 101 val sfence = io.sfence 102 val mem = io.mem 103 val req_s2xlate = Reg(UInt(2.W)) 104 val enableS2xlate = req_s2xlate =/= noS2xlate 105 val onlyS1xlate = req_s2xlate === onlyStage1 106 val onlyS2xlate = req_s2xlate === onlyStage2 107 108 // mbmc:bitmap csr 109 val mbmc = io.csr.mbmc 110 val bitmap_enable = (if (HasBitmapCheck) true.B else false.B) && mbmc.BME === 1.U && mbmc.CMODE === 0.U 111 112 val satp = Wire(new TlbSatpBundle()) 113 when (io.req.fire) { 114 satp := Mux(io.req.bits.req_info.s2xlate =/= noS2xlate, io.csr.vsatp, io.csr.satp) 115 } .otherwise { 116 satp := Mux(enableS2xlate, io.csr.vsatp, io.csr.satp) 117 } 118 val s1Pbmte = Mux(req_s2xlate =/= noS2xlate, io.csr.hPBMTE, io.csr.mPBMTE) 119 120 val mode = satp.mode 121 val hgatp = io.csr.hgatp 122 val flush = io.sfence.valid || io.csr.satp.changed || io.csr.vsatp.changed || io.csr.hgatp.changed 123 val s2xlate = enableS2xlate && !onlyS1xlate 124 val level = RegInit(3.U(log2Up(Level + 1).W)) 125 val af_level = RegInit(3.U(log2Up(Level + 1).W)) // access fault return this level 126 val gpf_level = RegInit(3.U(log2Up(Level + 1).W)) 127 val ppn = Reg(UInt(ptePPNLen.W)) 128 val vpn = Reg(UInt(vpnLen.W)) // vpn or gvpn(onlyS2xlate) 129 val levelNext = level - 1.U 130 val l3Hit = Reg(Bool()) 131 val l2Hit = Reg(Bool()) 132 val jmp_bitmap_check_w = if (HasBitmapCheck) { io.req.bits.bitmapCheck.get.jmp_bitmap_check && io.req.bits.req_info.s2xlate =/= onlyStage2 } else { false.B } 133 val jmp_bitmap_check_r = if (HasBitmapCheck) { RegEnable(jmp_bitmap_check_w, io.req.fire) } else { false.B } 134 val cache_pte = Option.when(HasBitmapCheck)(RegEnable(io.req.bits.bitmapCheck.get.pte.asTypeOf(new PteBundle().cloneType), io.req.fire)) 135 val pte = if (HasBitmapCheck) { Mux(jmp_bitmap_check_r, cache_pte.get, io.mem.resp.bits.asTypeOf(new PteBundle().cloneType)) } else { mem.resp.bits.asTypeOf(new PteBundle()) } 136 137 // s/w register 138 val s_pmp_check = RegInit(true.B) 139 val s_mem_req = RegInit(true.B) 140 val s_llptw_req = RegInit(true.B) 141 val w_mem_resp = RegInit(true.B) 142 val s_hptw_req = RegInit(true.B) 143 val w_hptw_resp = RegInit(true.B) 144 val s_last_hptw_req = RegInit(true.B) 145 val w_last_hptw_resp = RegInit(true.B) 146 // for updating "level" 147 val mem_addr_update = RegInit(false.B) 148 149 val s_bitmap_check = RegInit(true.B) 150 val w_bitmap_resp = RegInit(true.B) 151 val whether_need_bitmap_check = RegInit(false.B) 152 val bitmap_checkfailed = RegInit(false.B) 153 154 val idle = RegInit(true.B) 155 val finish = WireInit(false.B) 156 val sent_to_pmp = idle === false.B && (s_pmp_check === false.B || mem_addr_update) && !finish 157 158 val pageFault = pte.isPf(level, s1Pbmte) 159 val accessFault = RegEnable(io.pmp.resp.ld || io.pmp.resp.mmio, false.B, sent_to_pmp) 160 161 val hptw_pageFault = RegInit(false.B) 162 val hptw_accessFault = RegInit(false.B) 163 val need_last_s2xlate = RegInit(false.B) 164 val stage1Hit = RegEnable(io.req.bits.stage1Hit, io.req.fire) 165 val stage1 = RegEnable(io.req.bits.stage1, io.req.fire) 166 val hptw_resp_stage2 = Reg(Bool()) 167 168 // use accessfault repersent bitmap check failed 169 val pte_isAf = Mux(bitmap_enable, pte.isAf() || bitmap_checkfailed, pte.isAf()) 170 val ppn_af = if (HasBitmapCheck) { 171 Mux(enableS2xlate, Mux(onlyS1xlate, pte_isAf, false.B), pte_isAf) // In two-stage address translation, stage 1 ppn is a vpn for host, so don't need to check ppn_high 172 } else { 173 Mux(enableS2xlate, Mux(onlyS1xlate, pte.isAf(), false.B), pte.isAf()) // In two-stage address translation, stage 1 ppn is a vpn for host, so don't need to check ppn_high 174 } 175 176 val find_pte = pte.isLeaf() || ppn_af || pageFault 177 val to_find_pte = level === 1.U && find_pte === false.B 178 val source = RegEnable(io.req.bits.req_info.source, io.req.fire) 179 180 val l3addr = Wire(UInt(PAddrBits.W)) 181 val l2addr = Wire(UInt(PAddrBits.W)) 182 val l1addr = Wire(UInt(PAddrBits.W)) 183 val mem_addr = Wire(UInt(PAddrBits.W)) 184 185 l3addr := MakeAddr(satp.ppn, getVpnn(vpn, 3)) 186 if (EnableSv48) { 187 when (mode === Sv48) { 188 l2addr := MakeAddr(Mux(l3Hit, ppn, pte.getPPN()), getVpnn(vpn, 2)) 189 } .otherwise { 190 l2addr := MakeAddr(satp.ppn, getVpnn(vpn, 2)) 191 } 192 } else { 193 l2addr := MakeAddr(satp.ppn, getVpnn(vpn, 2)) 194 } 195 l1addr := MakeAddr(Mux(l2Hit, ppn, pte.getPPN()), getVpnn(vpn, 1)) 196 mem_addr := Mux(af_level === 3.U, l3addr, Mux(af_level === 2.U, l2addr, l1addr)) 197 198 val hptw_resp = Reg(new HptwResp) 199 200 val update_full_gvpn_mem_resp = RegInit(false.B) 201 val full_gvpn_reg = Reg(UInt(ptePPNLen.W)) 202 val full_gvpn_wire = pte.getPPN() 203 val full_gvpn = Mux(update_full_gvpn_mem_resp, full_gvpn_wire, full_gvpn_reg) 204 205 val gpaddr = MuxCase(mem_addr, Seq( 206 (stage1Hit || onlyS2xlate) -> Cat(full_gvpn, 0.U(offLen.W)), 207 !s_last_hptw_req -> Cat(MuxLookup(level, pte.getPPN())(Seq( 208 3.U -> Cat(pte.getPPN()(ptePPNLen - 1, vpnnLen * 3), vpn(vpnnLen * 3 - 1, 0)), 209 2.U -> Cat(pte.getPPN()(ptePPNLen - 1, vpnnLen * 2), vpn(vpnnLen * 2 - 1, 0)), 210 1.U -> Cat(pte.getPPN()(ptePPNLen - 1, vpnnLen), vpn(vpnnLen - 1, 0) 211 ))), 212 0.U(offLen.W)) 213 )) 214 val gvpn_gpf = 215 !(hptw_pageFault || hptw_accessFault ) && 216 Mux( 217 s2xlate && io.csr.hgatp.mode === Sv39x4, 218 full_gvpn(ptePPNLen - 1, GPAddrBitsSv39x4 - offLen) =/= 0.U, 219 Mux( 220 s2xlate && io.csr.hgatp.mode === Sv48x4, 221 full_gvpn(ptePPNLen - 1, GPAddrBitsSv48x4 - offLen) =/= 0.U, 222 false.B 223 ) 224 ) 225 226 val guestFault = hptw_pageFault || hptw_accessFault || gvpn_gpf 227 val hpaddr = Cat(hptw_resp.genPPNS2(get_pn(gpaddr)), get_off(gpaddr)) 228 val fake_h_resp = WireInit(0.U.asTypeOf(new HptwResp)) 229 fake_h_resp.entry.tag := get_pn(gpaddr) 230 fake_h_resp.entry.vmid.map(_ := io.csr.hgatp.vmid) 231 fake_h_resp.gpf := true.B 232 233 val pte_valid = RegInit(false.B) // avoid l1tlb pf from stage1 when gpf happens in the first s2xlate in PTW 234 val fake_pte = WireInit(0.U.asTypeOf(new PteBundle())) 235 fake_pte.perm.v := false.B // tell L1TLB this is fake pte 236 fake_pte.ppn := ppn(ppnLen - 1, 0) 237 fake_pte.ppn_high := ppn(ptePPNLen - 1, ppnLen) 238 239 io.req.ready := idle 240 val ptw_resp = Wire(new PtwMergeResp) 241 ptw_resp.apply(Mux(pte_valid, pageFault && !accessFault, false.B), accessFault || (ppn_af && !(pte_valid && (pageFault || guestFault))), Mux(accessFault, af_level, Mux(guestFault, gpf_level, level)), Mux(pte_valid, pte, fake_pte), vpn, satp.asid, hgatp.vmid, vpn(sectortlbwidth - 1, 0), not_super = false, not_merge = false, bitmap_checkfailed.asBool) 242 243 val normal_resp = idle === false.B && mem_addr_update && !need_last_s2xlate && (guestFault || (w_mem_resp && find_pte) || (s_pmp_check && accessFault) || onlyS2xlate ) 244 val stageHit_resp = idle === false.B && hptw_resp_stage2 245 io.resp.valid := Mux(stage1Hit, stageHit_resp, normal_resp) 246 io.resp.bits.source := source 247 io.resp.bits.resp := Mux(stage1Hit || (l3Hit || l2Hit) && guestFault && !pte_valid, stage1, ptw_resp) 248 io.resp.bits.h_resp := Mux(gvpn_gpf, fake_h_resp, hptw_resp) 249 io.resp.bits.s2xlate := req_s2xlate 250 251 io.llptw.valid := s_llptw_req === false.B && to_find_pte && !accessFault && !guestFault 252 io.llptw.bits.req_info.source := source 253 io.llptw.bits.req_info.vpn := vpn 254 io.llptw.bits.req_info.s2xlate := req_s2xlate 255 io.llptw.bits.ppn := DontCare 256 if (HasBitmapCheck) { 257 io.llptw.bits.bitmapCheck.get.jmp_bitmap_check := DontCare 258 io.llptw.bits.bitmapCheck.get.ptes := DontCare 259 io.llptw.bits.bitmapCheck.get.cfs := DontCare 260 io.llptw.bits.bitmapCheck.get.hitway := DontCare 261 } 262 263 io.pmp.req.valid := DontCare // samecycle, do not use valid 264 io.pmp.req.bits.addr := Mux(s2xlate, hpaddr, mem_addr) 265 io.pmp.req.bits.size := 3.U // TODO: fix it 266 io.pmp.req.bits.cmd := TlbCmd.read 267 268 if (HasBitmapCheck) { 269 val cache_level = RegEnable(io.req.bits.bitmapCheck.get.SPlevel, io.req.fire) 270 io.bitmap.get.req.valid := !s_bitmap_check 271 io.bitmap.get.req.bits.bmppn := pte.ppn 272 io.bitmap.get.req.bits.id := FsmReqID.U(bMemID.W) 273 io.bitmap.get.req.bits.vpn := vpn 274 io.bitmap.get.req.bits.level := Mux(jmp_bitmap_check_r, cache_level, level) 275 io.bitmap.get.req.bits.way_info := DontCare 276 io.bitmap.get.req.bits.hptw_bypassed := false.B 277 io.bitmap.get.resp.ready := !w_bitmap_resp 278 } 279 mem.req.valid := s_mem_req === false.B && !mem.mask && !accessFault && s_pmp_check 280 mem.req.bits.addr := Mux(s2xlate, hpaddr, mem_addr) 281 mem.req.bits.id := FsmReqID.U(bMemID.W) 282 mem.req.bits.hptw_bypassed := false.B 283 284 io.refill.req_info.s2xlate := req_s2xlate 285 io.refill.req_info.vpn := vpn 286 io.refill.level := level 287 io.refill.req_info.source := source 288 289 io.hptw.req.valid := !s_hptw_req || !s_last_hptw_req 290 io.hptw.req.bits.id := FsmReqID.U(bMemID.W) 291 io.hptw.req.bits.gvpn := get_pn(gpaddr) 292 io.hptw.req.bits.source := source 293 294 if (HasBitmapCheck) { 295 when (io.req.fire && jmp_bitmap_check_w) { 296 idle := false.B 297 req_s2xlate := io.req.bits.req_info.s2xlate 298 vpn := io.req.bits.req_info.vpn 299 s_bitmap_check := false.B 300 need_last_s2xlate := false.B 301 hptw_pageFault := false.B 302 hptw_accessFault := false.B 303 level := io.req.bits.bitmapCheck.get.SPlevel 304 pte_valid := true.B 305 accessFault := false.B 306 } 307 } 308 309 when (io.req.fire && io.req.bits.stage1Hit && (if (HasBitmapCheck) !jmp_bitmap_check_w else true.B)) { 310 idle := false.B 311 req_s2xlate := io.req.bits.req_info.s2xlate 312 s_last_hptw_req := false.B 313 hptw_resp_stage2 := false.B 314 need_last_s2xlate := false.B 315 hptw_pageFault := false.B 316 hptw_accessFault := false.B 317 full_gvpn_reg := io.req.bits.stage1.genPPN() 318 } 319 320 when (io.resp.fire && stage1Hit){ 321 idle := true.B 322 } 323 324 when (io.req.fire && !io.req.bits.stage1Hit && (if (HasBitmapCheck) !jmp_bitmap_check_w else true.B)) { 325 val req = io.req.bits 326 val gvpn_wire = Wire(UInt(ptePPNLen.W)) 327 if (EnableSv48) { 328 when (mode === Sv48) { 329 level := Mux(req.l2Hit, 1.U, Mux(req.l3Hit.get, 2.U, 3.U)) 330 af_level := Mux(req.l2Hit, 1.U, Mux(req.l3Hit.get, 2.U, 3.U)) 331 gpf_level := Mux(req.l2Hit, 2.U, Mux(req.l3Hit.get, 3.U, 0.U)) 332 ppn := Mux(req.l2Hit || req.l3Hit.get, io.req.bits.ppn, satp.ppn) 333 l3Hit := req.l3Hit.get 334 gvpn_wire := Mux(req.l2Hit || req.l3Hit.get, io.req.bits.ppn, satp.ppn) 335 } .otherwise { 336 level := Mux(req.l2Hit, 1.U, 2.U) 337 af_level := Mux(req.l2Hit, 1.U, 2.U) 338 gpf_level := 0.U 339 ppn := Mux(req.l2Hit, io.req.bits.ppn, satp.ppn) 340 l3Hit := false.B 341 gvpn_wire := Mux(req.l2Hit, io.req.bits.ppn, satp.ppn) 342 } 343 } else { 344 level := Mux(req.l2Hit, 1.U, 2.U) 345 af_level := Mux(req.l2Hit, 1.U, 2.U) 346 gpf_level := 0.U 347 ppn := Mux(req.l2Hit, io.req.bits.ppn, satp.ppn) 348 l3Hit := false.B 349 gvpn_wire := Mux(req.l2Hit, io.req.bits.ppn, satp.ppn) 350 } 351 vpn := io.req.bits.req_info.vpn 352 l2Hit := req.l2Hit 353 accessFault := false.B 354 idle := false.B 355 hptw_pageFault := false.B 356 hptw_accessFault := false.B 357 pte_valid := false.B 358 req_s2xlate := io.req.bits.req_info.s2xlate 359 when(io.req.bits.req_info.s2xlate === onlyStage2){ 360 full_gvpn_reg := io.req.bits.req_info.vpn 361 val onlys2_gpaddr = Cat(io.req.bits.req_info.vpn, 0.U(offLen.W)) // is 50 bits, don't need to check high bits when sv48x4 is enabled 362 val check_gpa_high_fail = Mux(io.req.bits.req_info.s2xlate === onlyStage2 && io.csr.hgatp.mode === Sv39x4, onlys2_gpaddr(onlys2_gpaddr.getWidth - 1, GPAddrBitsSv39x4) =/= 0.U, false.B) 363 need_last_s2xlate := false.B 364 when(check_gpa_high_fail){ 365 mem_addr_update := true.B 366 }.otherwise{ 367 s_last_hptw_req := false.B 368 } 369 }.elsewhen(io.req.bits.req_info.s2xlate === allStage){ 370 full_gvpn_reg := 0.U 371 val allstage_gpaddr = Cat(gvpn_wire, 0.U(offLen.W)) 372 val check_gpa_high_fail = Mux(io.csr.hgatp.mode === Sv39x4, allstage_gpaddr(allstage_gpaddr.getWidth - 1, GPAddrBitsSv39x4) =/= 0.U, Mux(io.csr.hgatp.mode === Sv48x4, allstage_gpaddr(allstage_gpaddr.getWidth - 1, GPAddrBitsSv48x4) =/= 0.U, false.B)) 373 when(check_gpa_high_fail){ 374 mem_addr_update := true.B 375 }.otherwise{ 376 need_last_s2xlate := true.B 377 s_hptw_req := false.B 378 } 379 }.otherwise { 380 full_gvpn_reg := 0.U 381 need_last_s2xlate := false.B 382 s_pmp_check := false.B 383 } 384 } 385 386 when(io.hptw.req.fire && s_hptw_req === false.B){ 387 s_hptw_req := true.B 388 w_hptw_resp := false.B 389 } 390 391 when(io.hptw.resp.fire && w_hptw_resp === false.B) { 392 w_hptw_resp := true.B 393 val g_perm_fail = !io.hptw.resp.bits.h_resp.gaf && (!io.hptw.resp.bits.h_resp.entry.perm.get.r && !(io.csr.priv.mxr && io.hptw.resp.bits.h_resp.entry.perm.get.x)) 394 hptw_pageFault := io.hptw.resp.bits.h_resp.gpf || g_perm_fail 395 hptw_accessFault := io.hptw.resp.bits.h_resp.gaf 396 hptw_resp := io.hptw.resp.bits.h_resp 397 hptw_resp.gpf := io.hptw.resp.bits.h_resp.gpf || g_perm_fail 398 when(!(g_perm_fail || io.hptw.resp.bits.h_resp.gpf || io.hptw.resp.bits.h_resp.gaf)) { 399 s_pmp_check := false.B 400 }.otherwise { 401 mem_addr_update := true.B 402 need_last_s2xlate := false.B 403 } 404 } 405 406 when(io.hptw.req.fire && s_last_hptw_req === false.B) { 407 w_last_hptw_resp := false.B 408 s_last_hptw_req := true.B 409 } 410 411 when (io.hptw.resp.fire && w_last_hptw_resp === false.B && stage1Hit){ 412 w_last_hptw_resp := true.B 413 hptw_resp_stage2 := true.B 414 hptw_resp := io.hptw.resp.bits.h_resp 415 } 416 417 when(io.hptw.resp.fire && w_last_hptw_resp === false.B && !stage1Hit){ 418 hptw_pageFault := io.hptw.resp.bits.h_resp.gpf 419 hptw_accessFault := io.hptw.resp.bits.h_resp.gaf 420 hptw_resp := io.hptw.resp.bits.h_resp 421 w_last_hptw_resp := true.B 422 mem_addr_update := true.B 423 } 424 425 when(sent_to_pmp && mem_addr_update === false.B){ 426 s_mem_req := false.B 427 s_pmp_check := true.B 428 } 429 430 when(accessFault && idle === false.B){ 431 s_pmp_check := true.B 432 s_mem_req := true.B 433 w_mem_resp := true.B 434 s_llptw_req := true.B 435 s_hptw_req := true.B 436 w_hptw_resp := true.B 437 s_last_hptw_req := true.B 438 w_last_hptw_resp := true.B 439 mem_addr_update := true.B 440 need_last_s2xlate := false.B 441 if (HasBitmapCheck) { 442 s_bitmap_check := true.B 443 w_bitmap_resp := true.B 444 whether_need_bitmap_check := false.B 445 bitmap_checkfailed := false.B 446 } 447 } 448 449 when(guestFault && idle === false.B){ 450 s_pmp_check := true.B 451 s_mem_req := true.B 452 w_mem_resp := true.B 453 s_llptw_req := true.B 454 s_hptw_req := true.B 455 w_hptw_resp := true.B 456 s_last_hptw_req := true.B 457 w_last_hptw_resp := true.B 458 mem_addr_update := true.B 459 need_last_s2xlate := false.B 460 if (HasBitmapCheck) { 461 s_bitmap_check := true.B 462 w_bitmap_resp := true.B 463 whether_need_bitmap_check := false.B 464 bitmap_checkfailed := false.B 465 } 466 } 467 468 when (mem.req.fire){ 469 s_mem_req := true.B 470 w_mem_resp := false.B 471 } 472 473 when(mem.resp.fire && w_mem_resp === false.B){ 474 w_mem_resp := true.B 475 af_level := af_level - 1.U 476 gpf_level := Mux(mode === Sv39 && !pte_valid && !(l3Hit || l2Hit), gpf_level - 2.U, gpf_level - 1.U) 477 pte_valid := true.B 478 update_full_gvpn_mem_resp := true.B 479 if (HasBitmapCheck) { 480 when (bitmap_enable) { 481 whether_need_bitmap_check := true.B 482 } .otherwise { 483 s_llptw_req := false.B 484 mem_addr_update := true.B 485 whether_need_bitmap_check := false.B 486 } 487 } else { 488 s_llptw_req := false.B 489 mem_addr_update := true.B 490 } 491 } 492 493 when(update_full_gvpn_mem_resp) { 494 update_full_gvpn_mem_resp := false.B 495 full_gvpn_reg := pte.getPPN() 496 } 497 498 if (HasBitmapCheck) { 499 when (whether_need_bitmap_check) { 500 when (bitmap_enable && (!enableS2xlate || onlyS1xlate) && pte.isLeaf()) { 501 s_bitmap_check := false.B 502 whether_need_bitmap_check := false.B 503 } .otherwise { 504 mem_addr_update := true.B 505 s_llptw_req := false.B 506 whether_need_bitmap_check := false.B 507 } 508 } 509 // bitmapcheck 510 when (io.bitmap.get.req.fire) { 511 s_bitmap_check := true.B 512 w_bitmap_resp := false.B 513 } 514 when (io.bitmap.get.resp.fire) { 515 w_bitmap_resp := true.B 516 mem_addr_update := true.B 517 bitmap_checkfailed := io.bitmap.get.resp.bits.cf 518 } 519 } 520 521 when(mem_addr_update){ 522 when(level >= 2.U && !onlyS2xlate && !(guestFault || find_pte || accessFault)) { 523 level := levelNext 524 when(s2xlate){ 525 s_hptw_req := false.B 526 }.otherwise{ 527 s_mem_req := false.B 528 } 529 s_llptw_req := true.B 530 mem_addr_update := false.B 531 }.elsewhen(io.llptw.valid){ 532 when(io.llptw.fire) { 533 idle := true.B 534 s_llptw_req := true.B 535 mem_addr_update := false.B 536 need_last_s2xlate := false.B 537 } 538 finish := true.B 539 }.elsewhen(s2xlate && need_last_s2xlate === true.B) { 540 need_last_s2xlate := false.B 541 when(!(guestFault || accessFault || pageFault || ppn_af)){ 542 s_last_hptw_req := false.B 543 mem_addr_update := false.B 544 } 545 }.elsewhen(io.resp.valid){ 546 when(io.resp.fire) { 547 idle := true.B 548 s_llptw_req := true.B 549 mem_addr_update := false.B 550 accessFault := false.B 551 } 552 finish := true.B 553 } 554 } 555 556 557 when (flush) { 558 idle := true.B 559 s_pmp_check := true.B 560 s_mem_req := true.B 561 s_llptw_req := true.B 562 w_mem_resp := true.B 563 accessFault := false.B 564 mem_addr_update := false.B 565 s_hptw_req := true.B 566 w_hptw_resp := true.B 567 s_last_hptw_req := true.B 568 w_last_hptw_resp := true.B 569 if (HasBitmapCheck) { 570 s_bitmap_check := true.B 571 w_bitmap_resp := true.B 572 whether_need_bitmap_check := false.B 573 bitmap_checkfailed := false.B 574 } 575 } 576 577 578 XSDebug(p"[ptw] level:${level} notFound:${pageFault}\n") 579 580 // perf 581 XSPerfAccumulate("fsm_count", io.req.fire) 582 for (i <- 0 until PtwWidth) { 583 XSPerfAccumulate(s"fsm_count_source${i}", io.req.fire && io.req.bits.req_info.source === i.U) 584 } 585 XSPerfAccumulate("fsm_busy", !idle) 586 XSPerfAccumulate("fsm_idle", idle) 587 XSPerfAccumulate("resp_blocked", io.resp.valid && !io.resp.ready) 588 XSPerfAccumulate("ptw_ppn_af", io.resp.fire && ppn_af) 589 XSPerfAccumulate("mem_count", mem.req.fire) 590 XSPerfAccumulate("mem_cycle", BoolStopWatch(mem.req.fire, mem.resp.fire, true)) 591 XSPerfAccumulate("mem_blocked", mem.req.valid && !mem.req.ready) 592 593 val perfEvents = Seq( 594 ("fsm_count ", io.req.fire ), 595 ("fsm_busy ", !idle ), 596 ("fsm_idle ", idle ), 597 ("resp_blocked ", io.resp.valid && !io.resp.ready ), 598 ("mem_count ", mem.req.fire ), 599 ("mem_cycle ", BoolStopWatch(mem.req.fire, mem.resp.fire, true)), 600 ("mem_blocked ", mem.req.valid && !mem.req.ready ), 601 ) 602 generatePerfEvent() 603} 604 605/*========================= LLPTW ==============================*/ 606 607/** LLPTW : Last Level Page Table Walker 608 * the page walker that only takes 4KB(last level) page walk. 609 **/ 610 611class LLPTWInBundle(implicit p: Parameters) extends XSBundle with HasPtwConst { 612 val req_info = Output(new L2TlbInnerBundle()) 613 val ppn = Output(UInt(ptePPNLen.W)) 614 val bitmapCheck = Option.when(HasBitmapCheck)(new Bundle { 615 val jmp_bitmap_check = Bool() // find pte in l0 or sp, but need bitmap check 616 val ptes = Vec(tlbcontiguous, UInt(XLEN.W)) // Page Table Entry Vector 617 val cfs = Vec(tlbcontiguous, Bool()) // Bitmap Check Failed Vector 618 val hitway = UInt(l2tlbParams.l0nWays.W) 619 }) 620} 621 622class LLPTWIO(implicit p: Parameters) extends MMUIOBaseBundle with HasPtwConst { 623 val in = Flipped(DecoupledIO(new LLPTWInBundle())) 624 val out = DecoupledIO(new Bundle { 625 val req_info = Output(new L2TlbInnerBundle()) 626 val id = Output(UInt(bMemID.W)) 627 val h_resp = Output(new HptwResp) 628 val first_s2xlate_fault = Output(Bool()) // Whether the first stage 2 translation occurs pf/af 629 val af = Output(Bool()) 630 val bitmapCheck = Option.when(HasBitmapCheck)(new Bundle { 631 val jmp_bitmap_check = Bool() // find pte in l0 or sp, but need bitmap check 632 val ptes = Vec(tlbcontiguous, UInt(XLEN.W)) // Page Table Entry Vector 633 val cfs = Vec(tlbcontiguous, Bool()) // Bitmap Check Failed Vector 634 }) 635 }) 636 val mem = new Bundle { 637 val req = DecoupledIO(new L2TlbMemReqBundle()) 638 val resp = Flipped(Valid(new Bundle { 639 val id = Output(UInt(log2Up(l2tlbParams.llptwsize).W)) 640 val value = Output(UInt(blockBits.W)) 641 })) 642 val enq_ptr = Output(UInt(log2Ceil(l2tlbParams.llptwsize).W)) 643 val buffer_it = Output(Vec(l2tlbParams.llptwsize, Bool())) 644 val refill = Output(new L2TlbInnerBundle()) 645 val req_mask = Input(Vec(l2tlbParams.llptwsize, Bool())) 646 val flush_latch = Input(Vec(l2tlbParams.llptwsize, Bool())) 647 } 648 val cache = DecoupledIO(new L2TlbInnerBundle()) 649 val pmp = new Bundle { 650 val req = Valid(new PMPReqBundle()) 651 val resp = Flipped(new PMPRespBundle()) 652 } 653 val hptw = new Bundle { 654 val req = DecoupledIO(new Bundle{ 655 val source = UInt(bSourceWidth.W) 656 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 657 val gvpn = UInt(ptePPNLen.W) 658 }) 659 val resp = Flipped(Valid(new Bundle { 660 val id = Output(UInt(log2Up(l2tlbParams.llptwsize).W)) 661 val h_resp = Output(new HptwResp) 662 })) 663 } 664 val bitmap = Option.when(HasBitmapCheck)(new Bundle { 665 val req = DecoupledIO(new bitmapReqBundle()) 666 val resp = Flipped(DecoupledIO(new bitmapRespBundle())) 667 }) 668 669 val l0_way_info = Option.when(HasBitmapCheck)(Input(UInt(l2tlbParams.l0nWays.W))) 670} 671 672class LLPTWEntry(implicit p: Parameters) extends XSBundle with HasPtwConst { 673 val req_info = new L2TlbInnerBundle() 674 val ppn = UInt(ptePPNLen.W) 675 val wait_id = UInt(log2Up(l2tlbParams.llptwsize).W) 676 val af = Bool() 677 val hptw_resp = new HptwResp() 678 val first_s2xlate_fault = Output(Bool()) 679 val cf = Bool() 680 val from_l0 = Bool() 681 val way_info = UInt(l2tlbParams.l0nWays.W) 682 val jmp_bitmap_check = Bool() 683 val ptes = Vec(tlbcontiguous, UInt(XLEN.W)) 684 val cfs = Vec(tlbcontiguous, Bool()) 685} 686 687 688class LLPTW(implicit p: Parameters) extends XSModule with HasPtwConst with HasPerfEvents { 689 val io = IO(new LLPTWIO()) 690 val enableS2xlate = io.in.bits.req_info.s2xlate =/= noS2xlate 691 val satp = Mux(enableS2xlate, io.csr.vsatp, io.csr.satp) 692 val s1Pbmte = Mux(enableS2xlate, io.csr.hPBMTE, io.csr.mPBMTE) 693 694 // mbmc:bitmap csr 695 val mbmc = io.csr.mbmc 696 val bitmap_enable = (if (HasBitmapCheck) true.B else false.B) && mbmc.BME === 1.U && mbmc.CMODE === 0.U 697 698 val flush = io.sfence.valid || io.csr.satp.changed || io.csr.vsatp.changed || io.csr.hgatp.changed 699 val entries = RegInit(VecInit(Seq.fill(l2tlbParams.llptwsize)(0.U.asTypeOf(new LLPTWEntry())))) 700 val state_idle :: state_hptw_req :: state_hptw_resp :: state_addr_check :: state_mem_req :: state_mem_waiting :: state_mem_out :: state_last_hptw_req :: state_last_hptw_resp :: state_cache :: state_bitmap_check :: state_bitmap_resp :: Nil = Enum(12) 701 val state = RegInit(VecInit(Seq.fill(l2tlbParams.llptwsize)(state_idle))) 702 703 val is_emptys = state.map(_ === state_idle) 704 val is_mems = state.map(_ === state_mem_req) 705 val is_waiting = state.map(_ === state_mem_waiting) 706 val is_having = state.map(_ === state_mem_out) 707 val is_cache = state.map(_ === state_cache) 708 val is_hptw_req = state.map(_ === state_hptw_req) 709 val is_last_hptw_req = state.map(_ === state_last_hptw_req) 710 val is_hptw_resp = state.map(_ === state_hptw_resp) 711 val is_last_hptw_resp = state.map(_ === state_last_hptw_resp) 712 val is_bitmap_req = state.map(_ === state_bitmap_check) 713 val is_bitmap_resp = state.map(_ === state_bitmap_resp) 714 715 val full = !ParallelOR(is_emptys).asBool 716 val enq_ptr = ParallelPriorityEncoder(is_emptys) 717 718 val mem_ptr = ParallelPriorityEncoder(is_having) // TODO: optimize timing, bad: entries -> ptr -> entry 719 val mem_arb = Module(new RRArbiterInit(new LLPTWEntry(), l2tlbParams.llptwsize)) 720 for (i <- 0 until l2tlbParams.llptwsize) { 721 mem_arb.io.in(i).bits := entries(i) 722 mem_arb.io.in(i).valid := is_mems(i) && !io.mem.req_mask(i) 723 } 724 725 // process hptw requests in serial 726 val hyper_arb1 = Module(new RRArbiterInit(new LLPTWEntry(), l2tlbParams.llptwsize)) 727 for (i <- 0 until l2tlbParams.llptwsize) { 728 hyper_arb1.io.in(i).bits := entries(i) 729 hyper_arb1.io.in(i).valid := is_hptw_req(i) && !(Cat(is_hptw_resp).orR) && !(Cat(is_last_hptw_resp).orR) 730 } 731 val hyper_arb2 = Module(new RRArbiterInit(new LLPTWEntry(), l2tlbParams.llptwsize)) 732 for(i <- 0 until l2tlbParams.llptwsize) { 733 hyper_arb2.io.in(i).bits := entries(i) 734 hyper_arb2.io.in(i).valid := is_last_hptw_req(i) && !(Cat(is_hptw_resp).orR) && !(Cat(is_last_hptw_resp).orR) 735 } 736 737 738 val bitmap_arb = Option.when(HasBitmapCheck)(Module(new RRArbiter(new bitmapReqBundle(), l2tlbParams.llptwsize))) 739 val way_info = Option.when(HasBitmapCheck)(Wire(Vec(l2tlbParams.llptwsize, UInt(l2tlbParams.l0nWays.W)))) 740 if (HasBitmapCheck) { 741 for (i <- 0 until l2tlbParams.llptwsize) { 742 bitmap_arb.get.io.in(i).valid := is_bitmap_req(i) 743 bitmap_arb.get.io.in(i).bits.bmppn := entries(i).ppn 744 bitmap_arb.get.io.in(i).bits.vpn := entries(i).req_info.vpn 745 bitmap_arb.get.io.in(i).bits.id := i.U 746 bitmap_arb.get.io.in(i).bits.level := 0.U // last level 747 bitmap_arb.get.io.in(i).bits.way_info := Mux(entries(i).from_l0, entries(i).way_info, way_info.get(i)) 748 bitmap_arb.get.io.in(i).bits.hptw_bypassed := false.B 749 } 750 } 751 752 val cache_ptr = ParallelMux(is_cache, (0 until l2tlbParams.llptwsize).map(_.U(log2Up(l2tlbParams.llptwsize).W))) 753 754 // duplicate req 755 // to_wait: wait for the last to access mem, set to mem_resp 756 // to_cache: the last is back just right now, set to mem_cache 757 val dup_vec = state.indices.map(i => 758 dup(io.in.bits.req_info.vpn, entries(i).req_info.vpn) && io.in.bits.req_info.s2xlate === entries(i).req_info.s2xlate 759 ) 760 val dup_req_fire = mem_arb.io.out.fire && dup(io.in.bits.req_info.vpn, mem_arb.io.out.bits.req_info.vpn) && io.in.bits.req_info.s2xlate === mem_arb.io.out.bits.req_info.s2xlate // dup with the req fire entry 761 val dup_vec_wait = dup_vec.zip(is_waiting).map{case (d, w) => d && w} // dup with "mem_waiting" entries, sending mem req already 762 val dup_vec_having = dup_vec.zipWithIndex.map{case (d, i) => d && is_having(i)} // dup with the "mem_out" entry recv the data just now 763 val dup_vec_bitmap = dup_vec.zipWithIndex.map{case (d, i) => d && (is_bitmap_req(i) || is_bitmap_resp(i))} 764 val dup_vec_last_hptw = dup_vec.zipWithIndex.map{case (d, i) => d && (is_last_hptw_req(i) || is_last_hptw_resp(i))} 765 val wait_id = Mux(dup_req_fire, mem_arb.io.chosen, ParallelMux(dup_vec_wait zip entries.map(_.wait_id))) 766 val dup_wait_resp = io.mem.resp.fire && VecInit(dup_vec_wait)(io.mem.resp.bits.id) && !io.mem.flush_latch(io.mem.resp.bits.id) // dup with the entry that data coming next cycle 767 val to_wait = Cat(dup_vec_wait).orR || dup_req_fire 768 val to_mem_out = dup_wait_resp && ((entries(io.mem.resp.bits.id).req_info.s2xlate === noS2xlate) || (entries(io.mem.resp.bits.id).req_info.s2xlate === onlyStage1)) && !bitmap_enable 769 val to_bitmap_req = (if (HasBitmapCheck) true.B else false.B) && dup_wait_resp && ((entries(io.mem.resp.bits.id).req_info.s2xlate === noS2xlate) || (entries(io.mem.resp.bits.id).req_info.s2xlate === onlyStage1)) && bitmap_enable 770 val to_cache = if (HasBitmapCheck) Cat(dup_vec_bitmap).orR || Cat(dup_vec_having).orR || Cat(dup_vec_last_hptw).orR 771 else Cat(dup_vec_having).orR || Cat(dup_vec_last_hptw).orR 772 val to_hptw_req = io.in.bits.req_info.s2xlate === allStage 773 val to_last_hptw_req = dup_wait_resp && entries(io.mem.resp.bits.id).req_info.s2xlate === allStage 774 val last_hptw_req_id = io.mem.resp.bits.id 775 val req_paddr = MakeAddr(io.in.bits.ppn(ppnLen-1, 0), getVpnn(io.in.bits.req_info.vpn, 0)) 776 val req_hpaddr = MakeAddr(entries(last_hptw_req_id).hptw_resp.genPPNS2(get_pn(req_paddr)), getVpnn(io.in.bits.req_info.vpn, 0)) 777 val index = Mux(entries(last_hptw_req_id).req_info.s2xlate === allStage, req_hpaddr, req_paddr)(log2Up(l2tlbParams.blockBytes)-1, log2Up(XLEN/8)) 778 val last_hptw_req_ppn = io.mem.resp.bits.value.asTypeOf(Vec(blockBits / XLEN, new PteBundle()))(index).getPPN() 779 XSError(RegNext(dup_req_fire && Cat(dup_vec_wait).orR, init = false.B), "mem req but some entries already waiting, should not happed") 780 781 XSError(io.in.fire && ((to_mem_out && to_cache) || (to_wait && to_cache)), "llptw enq, to cache conflict with to mem") 782 val mem_resp_hit = RegInit(VecInit(Seq.fill(l2tlbParams.llptwsize)(false.B))) 783 val enq_state_normal = MuxCase(state_addr_check, Seq( 784 to_mem_out -> state_mem_out, // same to the blew, but the mem resp now 785 to_bitmap_req -> state_bitmap_check, 786 to_last_hptw_req -> state_last_hptw_req, 787 to_wait -> state_mem_waiting, 788 to_cache -> state_cache, 789 to_hptw_req -> state_hptw_req 790 )) 791 val enq_state = Mux(from_pre(io.in.bits.req_info.source) && enq_state_normal =/= state_addr_check, state_idle, enq_state_normal) 792 when (io.in.fire && (if (HasBitmapCheck) !io.in.bits.bitmapCheck.get.jmp_bitmap_check else true.B)) { 793 // if prefetch req does not need mem access, just give it up. 794 // so there will be at most 1 + FilterSize entries that needs re-access page cache 795 // so 2 + FilterSize is enough to avoid dead-lock 796 state(enq_ptr) := enq_state 797 entries(enq_ptr).req_info := io.in.bits.req_info 798 entries(enq_ptr).ppn := Mux(to_last_hptw_req, last_hptw_req_ppn, io.in.bits.ppn) 799 entries(enq_ptr).wait_id := Mux(to_wait, wait_id, enq_ptr) 800 entries(enq_ptr).af := false.B 801 if (HasBitmapCheck) { 802 entries(enq_ptr).cf := false.B 803 entries(enq_ptr).from_l0 := false.B 804 entries(enq_ptr).way_info := 0.U 805 entries(enq_ptr).jmp_bitmap_check := false.B 806 for (i <- 0 until tlbcontiguous) { 807 entries(enq_ptr).ptes(i) := 0.U 808 } 809 entries(enq_ptr).cfs := io.in.bits.bitmapCheck.get.cfs 810 } 811 entries(enq_ptr).hptw_resp := Mux(to_last_hptw_req, entries(last_hptw_req_id).hptw_resp, Mux(to_wait, entries(wait_id).hptw_resp, entries(enq_ptr).hptw_resp)) 812 entries(enq_ptr).first_s2xlate_fault := false.B 813 mem_resp_hit(enq_ptr) := to_bitmap_req || to_mem_out || to_last_hptw_req 814 } 815 816 if (HasBitmapCheck) { 817 when (io.in.bits.bitmapCheck.get.jmp_bitmap_check && io.in.fire) { 818 state(enq_ptr) := state_bitmap_check 819 entries(enq_ptr).req_info := io.in.bits.req_info 820 entries(enq_ptr).ppn := io.in.bits.bitmapCheck.get.ptes(io.in.bits.req_info.vpn(sectortlbwidth - 1, 0)).asTypeOf(new PteBundle().cloneType).ppn 821 entries(enq_ptr).wait_id := enq_ptr 822 entries(enq_ptr).af := false.B 823 entries(enq_ptr).cf := false.B 824 entries(enq_ptr).from_l0 := true.B 825 entries(enq_ptr).way_info := io.in.bits.bitmapCheck.get.hitway 826 entries(enq_ptr).jmp_bitmap_check := io.in.bits.bitmapCheck.get.jmp_bitmap_check 827 entries(enq_ptr).ptes := io.in.bits.bitmapCheck.get.ptes 828 entries(enq_ptr).cfs := io.in.bits.bitmapCheck.get.cfs 829 mem_resp_hit(enq_ptr) := false.B 830 } 831 } 832 833 val enq_ptr_reg = RegNext(enq_ptr) 834 val need_addr_check = GatedValidRegNext(enq_state === state_addr_check && io.in.fire && !flush && (if (HasBitmapCheck) !io.in.bits.bitmapCheck.get.jmp_bitmap_check else true.B)) 835 836 val hasHptwResp = ParallelOR(state.map(_ === state_hptw_resp)).asBool 837 val hptw_resp_ptr_reg = RegNext(io.hptw.resp.bits.id) 838 val hptw_need_addr_check = RegNext(hasHptwResp && io.hptw.resp.fire && !flush) && state(hptw_resp_ptr_reg) === state_addr_check 839 840 val ptes = io.mem.resp.bits.value.asTypeOf(Vec(blockBits / XLEN, new PteBundle())) 841 val gpaddr = MakeGPAddr(entries(hptw_resp_ptr_reg).ppn, getVpnn(entries(hptw_resp_ptr_reg).req_info.vpn, 0)) 842 val hptw_resp = entries(hptw_resp_ptr_reg).hptw_resp 843 val hpaddr = Cat(hptw_resp.genPPNS2(get_pn(gpaddr)), get_off(gpaddr)) 844 val addr = RegEnable(MakeAddr(io.in.bits.ppn(ppnLen - 1, 0), getVpnn(io.in.bits.req_info.vpn, 0)), io.in.fire) 845 io.pmp.req.valid := need_addr_check || hptw_need_addr_check 846 io.pmp.req.bits.addr := Mux(hptw_need_addr_check, hpaddr, addr) 847 io.pmp.req.bits.cmd := TlbCmd.read 848 io.pmp.req.bits.size := 3.U // TODO: fix it 849 val pmp_resp_valid = io.pmp.req.valid // same cycle 850 when (pmp_resp_valid) { 851 // NOTE: when pmp resp but state is not addr check, then the entry is dup with other entry, the state was changed before 852 // when dup with the req-ing entry, set to mem_waiting (above codes), and the ld must be false, so dontcare 853 val ptr = Mux(hptw_need_addr_check, hptw_resp_ptr_reg, enq_ptr_reg); 854 val accessFault = io.pmp.resp.ld || io.pmp.resp.mmio 855 entries(ptr).af := accessFault 856 state(ptr) := Mux(accessFault, state_mem_out, state_mem_req) 857 } 858 859 when (mem_arb.io.out.fire) { 860 for (i <- state.indices) { 861 when (state(i) =/= state_idle && state(i) =/= state_mem_out && state(i) =/= state_last_hptw_req && state(i) =/= state_last_hptw_resp 862 && (if (HasBitmapCheck) state(i) =/= state_bitmap_check && state(i) =/= state_bitmap_resp else true.B) 863 && entries(i).req_info.s2xlate === mem_arb.io.out.bits.req_info.s2xlate 864 && dup(entries(i).req_info.vpn, mem_arb.io.out.bits.req_info.vpn)) { 865 // NOTE: "dup enq set state to mem_wait" -> "sending req set other dup entries to mem_wait" 866 state(i) := state_mem_waiting 867 entries(i).hptw_resp := entries(mem_arb.io.chosen).hptw_resp 868 entries(i).wait_id := mem_arb.io.chosen 869 } 870 } 871 } 872 when (io.mem.resp.fire) { 873 state.indices.map{i => 874 when (state(i) === state_mem_waiting && io.mem.resp.bits.id === entries(i).wait_id) { 875 val req_paddr = MakeAddr(entries(i).ppn, getVpnn(entries(i).req_info.vpn, 0)) 876 val req_hpaddr = MakeAddr(entries(i).hptw_resp.genPPNS2(get_pn(req_paddr)), getVpnn(entries(i).req_info.vpn, 0)) 877 val index = Mux(entries(i).req_info.s2xlate === allStage, req_hpaddr, req_paddr)(log2Up(l2tlbParams.blockBytes)-1, log2Up(XLEN/8)) 878 state(i) := Mux(entries(i).req_info.s2xlate === allStage && !(ptes(index).isPf(0.U, s1Pbmte) || !ptes(index).isLeaf() || ptes(index).isAf() || ptes(index).isStage1Gpf(io.csr.vsatp.mode)) 879 , state_last_hptw_req, Mux(bitmap_enable, state_bitmap_check, state_mem_out)) 880 mem_resp_hit(i) := true.B 881 entries(i).ppn := ptes(index).getPPN() // for last stage 2 translation 882 entries(i).hptw_resp.gpf := Mux(entries(i).req_info.s2xlate === allStage, ptes(index).isStage1Gpf(io.csr.vsatp.mode), false.B) 883 } 884 } 885 } 886 887 if (HasBitmapCheck) { 888 for (i <- 0 until l2tlbParams.llptwsize) { 889 way_info.get(i) := DataHoldBypass(io.l0_way_info.get, mem_resp_hit(i)) 890 } 891 } 892 893 when (hyper_arb1.io.out.fire) { 894 for (i <- state.indices) { 895 when (state(i) === state_hptw_req && entries(i).ppn === hyper_arb1.io.out.bits.ppn && entries(i).req_info.s2xlate === allStage && hyper_arb1.io.chosen === i.U) { 896 state(i) := state_hptw_resp 897 entries(i).wait_id := hyper_arb1.io.chosen 898 } 899 } 900 } 901 902 when (hyper_arb2.io.out.fire) { 903 for (i <- state.indices) { 904 when (state(i) === state_last_hptw_req && entries(i).ppn === hyper_arb2.io.out.bits.ppn && entries(i).req_info.s2xlate === allStage && hyper_arb2.io.chosen === i.U) { 905 state(i) := state_last_hptw_resp 906 entries(i).wait_id := hyper_arb2.io.chosen 907 } 908 } 909 } 910 911 if (HasBitmapCheck) { 912 when (bitmap_arb.get.io.out.fire) { 913 for (i <- state.indices) { 914 when (is_bitmap_req(i) && bitmap_arb.get.io.out.bits.bmppn === entries(i).ppn(ppnLen - 1, 0)) { 915 state(i) := state_bitmap_resp 916 entries(i).wait_id := bitmap_arb.get.io.chosen 917 } 918 } 919 } 920 921 when (io.bitmap.get.resp.fire) { 922 for (i <- state.indices) { 923 when (is_bitmap_resp(i) && io.bitmap.get.resp.bits.id === entries(i).wait_id) { 924 entries(i).cfs := io.bitmap.get.resp.bits.cfs 925 entries(i).cf := io.bitmap.get.resp.bits.cf 926 state(i) := state_mem_out 927 } 928 } 929 } 930 } 931 932 when (io.hptw.resp.fire) { 933 for (i <- state.indices) { 934 when (state(i) === state_hptw_resp && io.hptw.resp.bits.id === entries(i).wait_id && io.hptw.resp.bits.h_resp.entry.tag === entries(i).ppn) { 935 val check_g_perm_fail = !io.hptw.resp.bits.h_resp.gaf && (!io.hptw.resp.bits.h_resp.entry.perm.get.r && !(io.csr.priv.mxr && io.hptw.resp.bits.h_resp.entry.perm.get.x)) 936 when (check_g_perm_fail || io.hptw.resp.bits.h_resp.gaf || io.hptw.resp.bits.h_resp.gpf) { 937 state(i) := state_mem_out 938 entries(i).hptw_resp := io.hptw.resp.bits.h_resp 939 entries(i).hptw_resp.gpf := io.hptw.resp.bits.h_resp.gpf || check_g_perm_fail 940 entries(i).first_s2xlate_fault := io.hptw.resp.bits.h_resp.gaf || io.hptw.resp.bits.h_resp.gpf 941 }.otherwise{ // change the entry that is waiting hptw resp 942 val need_to_waiting_vec = state.indices.map(i => state(i) === state_mem_waiting && dup(entries(i).req_info.vpn, entries(io.hptw.resp.bits.id).req_info.vpn)) 943 val waiting_index = ParallelMux(need_to_waiting_vec zip entries.map(_.wait_id)) 944 state(i) := Mux(Cat(need_to_waiting_vec).orR, state_mem_waiting, state_addr_check) 945 entries(i).hptw_resp := io.hptw.resp.bits.h_resp 946 entries(i).wait_id := Mux(Cat(need_to_waiting_vec).orR, waiting_index, entries(i).wait_id) 947 //To do: change the entry that is having the same hptw req 948 } 949 } 950 when (state(i) === state_last_hptw_resp && io.hptw.resp.bits.id === entries(i).wait_id && io.hptw.resp.bits.h_resp.entry.tag === entries(i).ppn) { 951 state(i) := state_mem_out 952 entries(i).hptw_resp := io.hptw.resp.bits.h_resp 953 //To do: change the entry that is having the same hptw req 954 } 955 } 956 } 957 when (io.out.fire) { 958 assert(state(mem_ptr) === state_mem_out) 959 state(mem_ptr) := state_idle 960 } 961 mem_resp_hit.map(a => when (a) { a := false.B } ) 962 963 when (io.cache.fire) { 964 state(cache_ptr) := state_idle 965 } 966 XSError(io.out.fire && io.cache.fire && (mem_ptr === cache_ptr), "mem resp and cache fire at the same time at same entry") 967 968 when (flush) { 969 state.map(_ := state_idle) 970 } 971 972 io.in.ready := !full 973 974 io.out.valid := ParallelOR(is_having).asBool 975 io.out.bits.req_info := entries(mem_ptr).req_info 976 io.out.bits.id := mem_ptr 977 if (HasBitmapCheck) { 978 io.out.bits.af := Mux(bitmap_enable, entries(mem_ptr).af || entries(mem_ptr).cf, entries(mem_ptr).af) 979 io.out.bits.bitmapCheck.get.jmp_bitmap_check := entries(mem_ptr).jmp_bitmap_check 980 io.out.bits.bitmapCheck.get.ptes := entries(mem_ptr).ptes 981 io.out.bits.bitmapCheck.get.cfs := entries(mem_ptr).cfs 982 } else { 983 io.out.bits.af := entries(mem_ptr).af 984 } 985 986 io.out.bits.h_resp := entries(mem_ptr).hptw_resp 987 io.out.bits.first_s2xlate_fault := entries(mem_ptr).first_s2xlate_fault 988 989 val hptw_req_arb = Module(new Arbiter(new Bundle{ 990 val source = UInt(bSourceWidth.W) 991 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 992 val ppn = UInt(ptePPNLen.W) 993 } , 2)) 994 // first stage 2 translation 995 hptw_req_arb.io.in(0).valid := hyper_arb1.io.out.valid 996 hptw_req_arb.io.in(0).bits.source := hyper_arb1.io.out.bits.req_info.source 997 hptw_req_arb.io.in(0).bits.ppn := hyper_arb1.io.out.bits.ppn 998 hptw_req_arb.io.in(0).bits.id := hyper_arb1.io.chosen 999 hyper_arb1.io.out.ready := hptw_req_arb.io.in(0).ready 1000 // last stage 2 translation 1001 hptw_req_arb.io.in(1).valid := hyper_arb2.io.out.valid 1002 hptw_req_arb.io.in(1).bits.source := hyper_arb2.io.out.bits.req_info.source 1003 hptw_req_arb.io.in(1).bits.ppn := hyper_arb2.io.out.bits.ppn 1004 hptw_req_arb.io.in(1).bits.id := hyper_arb2.io.chosen 1005 hyper_arb2.io.out.ready := hptw_req_arb.io.in(1).ready 1006 hptw_req_arb.io.out.ready := io.hptw.req.ready 1007 io.hptw.req.valid := hptw_req_arb.io.out.fire && !flush 1008 io.hptw.req.bits.gvpn := hptw_req_arb.io.out.bits.ppn 1009 io.hptw.req.bits.id := hptw_req_arb.io.out.bits.id 1010 io.hptw.req.bits.source := hptw_req_arb.io.out.bits.source 1011 1012 io.mem.req.valid := mem_arb.io.out.valid && !flush 1013 val mem_paddr = MakeAddr(mem_arb.io.out.bits.ppn, getVpnn(mem_arb.io.out.bits.req_info.vpn, 0)) 1014 val mem_hpaddr = MakeAddr(mem_arb.io.out.bits.hptw_resp.genPPNS2(get_pn(mem_paddr)), getVpnn(mem_arb.io.out.bits.req_info.vpn, 0)) 1015 io.mem.req.bits.addr := Mux(mem_arb.io.out.bits.req_info.s2xlate === allStage, mem_hpaddr, mem_paddr) 1016 io.mem.req.bits.id := mem_arb.io.chosen 1017 io.mem.req.bits.hptw_bypassed := false.B 1018 mem_arb.io.out.ready := io.mem.req.ready 1019 val mem_refill_id = RegNext(io.mem.resp.bits.id(log2Up(l2tlbParams.llptwsize)-1, 0)) 1020 io.mem.refill := entries(mem_refill_id).req_info 1021 io.mem.refill.s2xlate := entries(mem_refill_id).req_info.s2xlate 1022 io.mem.buffer_it := mem_resp_hit 1023 io.mem.enq_ptr := enq_ptr 1024 1025 io.cache.valid := Cat(is_cache).orR 1026 io.cache.bits := ParallelMux(is_cache, entries.map(_.req_info)) 1027 1028 val has_bitmap_resp = ParallelOR(is_bitmap_resp).asBool 1029 if (HasBitmapCheck) { 1030 io.bitmap.get.req.valid := bitmap_arb.get.io.out.valid && !flush 1031 io.bitmap.get.req.bits.bmppn := bitmap_arb.get.io.out.bits.bmppn 1032 io.bitmap.get.req.bits.id := bitmap_arb.get.io.chosen 1033 io.bitmap.get.req.bits.vpn := bitmap_arb.get.io.out.bits.vpn 1034 io.bitmap.get.req.bits.level := 0.U 1035 io.bitmap.get.req.bits.way_info := bitmap_arb.get.io.out.bits.way_info 1036 io.bitmap.get.req.bits.hptw_bypassed := bitmap_arb.get.io.out.bits.hptw_bypassed 1037 bitmap_arb.get.io.out.ready := io.bitmap.get.req.ready 1038 io.bitmap.get.resp.ready := has_bitmap_resp 1039 } 1040 1041 XSPerfAccumulate("llptw_in_count", io.in.fire) 1042 XSPerfAccumulate("llptw_in_block", io.in.valid && !io.in.ready) 1043 for (i <- 0 until 7) { 1044 XSPerfAccumulate(s"enq_state${i}", io.in.fire && enq_state === i.U) 1045 } 1046 for (i <- 0 until (l2tlbParams.llptwsize + 1)) { 1047 XSPerfAccumulate(s"util${i}", PopCount(is_emptys.map(!_)) === i.U) 1048 XSPerfAccumulate(s"mem_util${i}", PopCount(is_mems) === i.U) 1049 XSPerfAccumulate(s"waiting_util${i}", PopCount(is_waiting) === i.U) 1050 } 1051 XSPerfAccumulate("mem_count", io.mem.req.fire) 1052 XSPerfAccumulate("mem_cycle", PopCount(is_waiting) =/= 0.U) 1053 XSPerfAccumulate("blocked_in", io.in.valid && !io.in.ready) 1054 1055 val perfEvents = Seq( 1056 ("tlbllptw_incount ", io.in.fire ), 1057 ("tlbllptw_inblock ", io.in.valid && !io.in.ready), 1058 ("tlbllptw_memcount ", io.mem.req.fire ), 1059 ("tlbllptw_memcycle ", PopCount(is_waiting) ), 1060 ) 1061 generatePerfEvent() 1062} 1063 1064/*========================= HPTW ==============================*/ 1065 1066/** HPTW : Hypervisor Page Table Walker 1067 * the page walker take the virtual machine's page walk. 1068 * guest physical address translation, guest physical address -> host physical address 1069 **/ 1070class HPTWIO()(implicit p: Parameters) extends MMUIOBaseBundle with HasPtwConst { 1071 val req = Flipped(DecoupledIO(new Bundle { 1072 val source = UInt(bSourceWidth.W) 1073 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 1074 val gvpn = UInt(gvpnLen.W) 1075 val ppn = UInt(ppnLen.W) 1076 val l3Hit = if (EnableSv48) Some(new Bool()) else None 1077 val l2Hit = Bool() 1078 val l1Hit = Bool() 1079 val bypassed = Bool() // if bypass, don't refill 1080 val bitmapCheck = Option.when(HasBitmapCheck)(new Bundle { 1081 val jmp_bitmap_check = Bool() // find pte in l0 or sp, but need bitmap check 1082 val pte = UInt(XLEN.W) // Page Table Entry 1083 val ptes = Vec(tlbcontiguous, UInt(XLEN.W)) // Page Table Entry Vector 1084 val cfs = Vec(tlbcontiguous, Bool()) // Bitmap Check Failed Vector 1085 val hitway = UInt(l2tlbParams.l0nWays.W) 1086 val fromSP = Bool() 1087 val SPlevel = UInt(log2Up(Level).W) 1088 }) 1089 })) 1090 val resp = DecoupledIO(new Bundle { 1091 val source = UInt(bSourceWidth.W) 1092 val resp = Output(new HptwResp()) 1093 val id = Output(UInt(bMemID.W)) 1094 }) 1095 1096 val mem = new Bundle { 1097 val req = DecoupledIO(new L2TlbMemReqBundle()) 1098 val resp = Flipped(ValidIO(UInt(XLEN.W))) 1099 val mask = Input(Bool()) 1100 } 1101 val refill = Output(new Bundle { 1102 val req_info = new L2TlbInnerBundle() 1103 val level = UInt(log2Up(Level + 1).W) 1104 }) 1105 val pmp = new Bundle { 1106 val req = ValidIO(new PMPReqBundle()) 1107 val resp = Flipped(new PMPRespBundle()) 1108 } 1109 val bitmap = Option.when(HasBitmapCheck)(new Bundle { 1110 val req = DecoupledIO(new bitmapReqBundle()) 1111 val resp = Flipped(DecoupledIO(new bitmapRespBundle())) 1112 }) 1113 1114 val l0_way_info = Option.when(HasBitmapCheck)(Input(UInt(l2tlbParams.l0nWays.W))) 1115} 1116 1117class HPTW()(implicit p: Parameters) extends XSModule with HasPtwConst { 1118 val io = IO(new HPTWIO) 1119 val hgatp = io.csr.hgatp 1120 val mpbmte = io.csr.mPBMTE 1121 val sfence = io.sfence 1122 val flush = sfence.valid || hgatp.changed || io.csr.satp.changed || io.csr.vsatp.changed 1123 val mode = hgatp.mode 1124 1125 // mbmc:bitmap csr 1126 val mbmc = io.csr.mbmc 1127 val bitmap_enable = (if (HasBitmapCheck) true.B else false.B) && mbmc.BME === 1.U && mbmc.CMODE === 0.U 1128 1129 val level = RegInit(3.U(log2Up(Level + 1).W)) 1130 val af_level = RegInit(3.U(log2Up(Level + 1).W)) // access fault return this level 1131 val gpaddr = Reg(UInt(GPAddrBits.W)) 1132 val req_ppn = Reg(UInt(ppnLen.W)) 1133 val vpn = gpaddr(GPAddrBits-1, offLen) 1134 val levelNext = level - 1.U 1135 val l3Hit = Reg(Bool()) 1136 val l2Hit = Reg(Bool()) 1137 val l1Hit = Reg(Bool()) 1138 val bypassed = Reg(Bool()) 1139// val pte = io.mem.resp.bits.MergeRespToPte() 1140 val jmp_bitmap_check = if (HasBitmapCheck) RegEnable(io.req.bits.bitmapCheck.get.jmp_bitmap_check, io.req.fire) else false.B 1141 val fromSP = if (HasBitmapCheck) RegEnable(io.req.bits.bitmapCheck.get.fromSP, io.req.fire) else false.B 1142 val cache_pte = Option.when(HasBitmapCheck)(RegEnable(Mux(io.req.bits.bitmapCheck.get.fromSP, io.req.bits.bitmapCheck.get.pte.asTypeOf(new PteBundle().cloneType), io.req.bits.bitmapCheck.get.ptes(io.req.bits.gvpn(sectortlbwidth - 1, 0)).asTypeOf(new PteBundle().cloneType)), io.req.fire)) 1143 val pte = if (HasBitmapCheck) Mux(jmp_bitmap_check, cache_pte.get, io.mem.resp.bits.asTypeOf(new PteBundle().cloneType)) else io.mem.resp.bits.asTypeOf(new PteBundle().cloneType) 1144 val ppn_l3 = Mux(l3Hit, req_ppn, pte.ppn) 1145 val ppn_l2 = Mux(l2Hit, req_ppn, pte.ppn) 1146 val ppn_l1 = Mux(l1Hit, req_ppn, pte.ppn) 1147 val ppn = Wire(UInt(PAddrBits.W)) 1148 val p_pte = MakeAddr(ppn, getVpnn(vpn, level)) 1149 val pg_base = Wire(UInt(PAddrBits.W)) 1150 val mem_addr = Wire(UInt(PAddrBits.W)) 1151 if (EnableSv48) { 1152 when (mode === Sv48) { 1153 ppn := Mux(af_level === 2.U, ppn_l3, Mux(af_level === 1.U, ppn_l2, ppn_l1)) // for l2, l1 and l3 1154 pg_base := MakeGPAddr(hgatp.ppn, getGVpnn(vpn, 3.U, mode = Sv48)) // for l3 1155 mem_addr := Mux(af_level === 3.U, pg_base, p_pte) 1156 } .otherwise { 1157 ppn := Mux(af_level === 1.U, ppn_l2, ppn_l1) //for l1 and l2 1158 pg_base := MakeGPAddr(hgatp.ppn, getGVpnn(vpn, 2.U, mode = Sv39)) 1159 mem_addr := Mux(af_level === 2.U, pg_base, p_pte) 1160 } 1161 } else { 1162 ppn := Mux(af_level === 1.U, ppn_l2, ppn_l1) //for l1 and l2 1163 pg_base := MakeGPAddr(hgatp.ppn, getGVpnn(vpn, 2.U, mode = Sv39)) 1164 mem_addr := Mux(af_level === 2.U, pg_base, p_pte) 1165 } 1166 1167 //s/w register 1168 val s_pmp_check = RegInit(true.B) 1169 val s_mem_req = RegInit(true.B) 1170 val w_mem_resp = RegInit(true.B) 1171 val idle = RegInit(true.B) 1172 val mem_addr_update = RegInit(false.B) 1173 val finish = WireInit(false.B) 1174 val s_bitmap_check = RegInit(true.B) 1175 val w_bitmap_resp = RegInit(true.B) 1176 val whether_need_bitmap_check = RegInit(false.B) 1177 val bitmap_checkfailed = RegInit(false.B) 1178 1179 val sent_to_pmp = !idle && (!s_pmp_check || mem_addr_update) && !finish 1180 val pageFault = pte.isGpf(level, mpbmte) || (!pte.isLeaf() && level === 0.U) 1181 val accessFault = RegEnable(io.pmp.resp.ld || io.pmp.resp.mmio, sent_to_pmp) 1182 1183 // use access fault when bitmap check failed 1184 val ppn_af = if (HasBitmapCheck) { 1185 Mux(bitmap_enable, pte.isAf() || bitmap_checkfailed, pte.isAf()) 1186 } else { 1187 pte.isAf() 1188 } 1189 val find_pte = pte.isLeaf() || ppn_af || pageFault 1190 1191 val resp_valid = !idle && mem_addr_update && ((w_mem_resp && find_pte) || (s_pmp_check && accessFault)) 1192 val id = Reg(UInt(log2Up(l2tlbParams.llptwsize).W)) 1193 val source = RegEnable(io.req.bits.source, io.req.fire) 1194 1195 io.req.ready := idle 1196 val resp = Wire(new HptwResp()) 1197 // accessFault > pageFault > ppn_af 1198 resp.apply( 1199 gpf = pageFault && !accessFault, 1200 gaf = accessFault || (ppn_af && !pageFault), 1201 level = Mux(accessFault, af_level, level), 1202 pte = pte, 1203 vpn = vpn, 1204 vmid = hgatp.vmid 1205 ) 1206 io.resp.valid := resp_valid 1207 io.resp.bits.id := id 1208 io.resp.bits.resp := resp 1209 io.resp.bits.source := source 1210 1211 io.pmp.req.valid := DontCare 1212 io.pmp.req.bits.addr := mem_addr 1213 io.pmp.req.bits.size := 3.U 1214 io.pmp.req.bits.cmd := TlbCmd.read 1215 1216 if (HasBitmapCheck) { 1217 val way_info = DataHoldBypass(io.l0_way_info.get, RegNext(io.mem.resp.fire, init=false.B)) 1218 val cache_hitway = RegEnable(io.req.bits.bitmapCheck.get.hitway, io.req.fire) 1219 val cache_level = RegEnable(io.req.bits.bitmapCheck.get.SPlevel, io.req.fire) 1220 io.bitmap.get.req.valid := !s_bitmap_check 1221 io.bitmap.get.req.bits.bmppn := pte.ppn 1222 io.bitmap.get.req.bits.id := HptwReqId.U(bMemID.W) 1223 io.bitmap.get.req.bits.vpn := vpn 1224 io.bitmap.get.req.bits.level := Mux(jmp_bitmap_check, Mux(fromSP,cache_level,0.U), level) 1225 io.bitmap.get.req.bits.way_info := Mux(jmp_bitmap_check, cache_hitway, way_info) 1226 io.bitmap.get.req.bits.hptw_bypassed := bypassed 1227 io.bitmap.get.resp.ready := !w_bitmap_resp 1228 } 1229 1230 io.mem.req.valid := !s_mem_req && !io.mem.mask && !accessFault && s_pmp_check 1231 io.mem.req.bits.addr := mem_addr 1232 io.mem.req.bits.id := HptwReqId.U(bMemID.W) 1233 io.mem.req.bits.hptw_bypassed := bypassed 1234 1235 io.refill.req_info.vpn := vpn 1236 io.refill.level := level 1237 io.refill.req_info.source := source 1238 io.refill.req_info.s2xlate := onlyStage2 1239 1240 when (idle){ 1241 if (HasBitmapCheck) { 1242 when (io.req.bits.bitmapCheck.get.jmp_bitmap_check && io.req.fire) { 1243 idle := false.B 1244 gpaddr := Cat(io.req.bits.gvpn, 0.U(offLen.W)) 1245 s_bitmap_check := false.B 1246 id := io.req.bits.id 1247 level := Mux(io.req.bits.bitmapCheck.get.fromSP, io.req.bits.bitmapCheck.get.SPlevel, 0.U) 1248 } 1249 } 1250 when (io.req.fire && (if (HasBitmapCheck) !io.req.bits.bitmapCheck.get.jmp_bitmap_check else true.B)) { 1251 bypassed := io.req.bits.bypassed 1252 idle := false.B 1253 gpaddr := Cat(io.req.bits.gvpn, 0.U(offLen.W)) 1254 accessFault := false.B 1255 s_pmp_check := false.B 1256 id := io.req.bits.id 1257 req_ppn := io.req.bits.ppn 1258 if (EnableSv48) { 1259 when (mode === Sv48) { 1260 level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, Mux(io.req.bits.l3Hit.get, 2.U, 3.U))) 1261 af_level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, Mux(io.req.bits.l3Hit.get, 2.U, 3.U))) 1262 l3Hit := io.req.bits.l3Hit.get 1263 } .otherwise { 1264 level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, 2.U)) 1265 af_level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, 2.U)) 1266 l3Hit := false.B 1267 } 1268 } else { 1269 level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, 2.U)) 1270 af_level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, 2.U)) 1271 l3Hit := false.B 1272 } 1273 l2Hit := io.req.bits.l2Hit 1274 l1Hit := io.req.bits.l1Hit 1275 } 1276 } 1277 1278 when(sent_to_pmp && !mem_addr_update){ 1279 s_mem_req := false.B 1280 s_pmp_check := true.B 1281 } 1282 1283 when(accessFault && !idle){ 1284 s_pmp_check := true.B 1285 s_mem_req := true.B 1286 w_mem_resp := true.B 1287 mem_addr_update := true.B 1288 if (HasBitmapCheck) { 1289 s_bitmap_check := true.B 1290 w_bitmap_resp := true.B 1291 whether_need_bitmap_check := false.B 1292 bitmap_checkfailed := false.B 1293 } 1294 } 1295 1296 when(io.mem.req.fire){ 1297 s_mem_req := true.B 1298 w_mem_resp := false.B 1299 } 1300 1301 when(io.mem.resp.fire && !w_mem_resp){ 1302 w_mem_resp := true.B 1303 af_level := af_level - 1.U 1304 if (HasBitmapCheck) { 1305 when (bitmap_enable) { 1306 whether_need_bitmap_check := true.B 1307 } .otherwise { 1308 mem_addr_update := true.B 1309 whether_need_bitmap_check := false.B 1310 } 1311 } else { 1312 mem_addr_update := true.B 1313 } 1314 } 1315 1316 if (HasBitmapCheck) { 1317 when (whether_need_bitmap_check) { 1318 when (bitmap_enable && pte.isLeaf()) { 1319 s_bitmap_check := false.B 1320 whether_need_bitmap_check := false.B 1321 } .otherwise { 1322 mem_addr_update := true.B 1323 whether_need_bitmap_check := false.B 1324 } 1325 } 1326 // bitmapcheck 1327 when (io.bitmap.get.req.fire) { 1328 s_bitmap_check := true.B 1329 w_bitmap_resp := false.B 1330 } 1331 when (io.bitmap.get.resp.fire) { 1332 w_bitmap_resp := true.B 1333 mem_addr_update := true.B 1334 bitmap_checkfailed := io.bitmap.get.resp.bits.cf 1335 } 1336 } 1337 1338 when(mem_addr_update){ 1339 when(!(find_pte || accessFault)){ 1340 level := levelNext 1341 s_mem_req := false.B 1342 mem_addr_update := false.B 1343 }.elsewhen(resp_valid){ 1344 when(io.resp.fire){ 1345 idle := true.B 1346 mem_addr_update := false.B 1347 accessFault := false.B 1348 } 1349 finish := true.B 1350 } 1351 } 1352 when (flush) { 1353 idle := true.B 1354 s_pmp_check := true.B 1355 s_mem_req := true.B 1356 w_mem_resp := true.B 1357 accessFault := false.B 1358 mem_addr_update := false.B 1359 if (HasBitmapCheck) { 1360 s_bitmap_check := true.B 1361 w_bitmap_resp := true.B 1362 whether_need_bitmap_check := false.B 1363 bitmap_checkfailed := false.B 1364 } 1365 } 1366} 1367