1/*************************************************************************************** 2* Copyright (c) 2021-2025 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* Copyright (c) 2024-2025 Institute of Information Engineering, Chinese Academy of Sciences 6* 7* XiangShan is licensed under Mulan PSL v2. 8* You can use this software according to the terms and conditions of the Mulan PSL v2. 9* You may obtain a copy of Mulan PSL v2 at: 10* http://license.coscl.org.cn/MulanPSL2 11* 12* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 13* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 14* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 15* 16* See the Mulan PSL v2 for more details. 17***************************************************************************************/ 18 19package xiangshan.cache.mmu 20 21import org.chipsalliance.cde.config.Parameters 22import chisel3._ 23import chisel3.util._ 24import xiangshan._ 25import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 26import utils._ 27import utility._ 28import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 29import freechips.rocketchip.tilelink._ 30import xiangshan.backend.fu.{PMPReqBundle, PMPRespBundle} 31 32/** Page Table Walk is divided into two parts 33 * One, PTW: page walk for pde, except for leaf entries, one by one 34 * Two, LLPTW: page walk for pte, only the leaf entries(4KB), in parallel 35 */ 36 37 38/** PTW : page table walker 39 * a finite state machine 40 * only take 1GB and 2MB page walks 41 * or in other words, except the last level(leaf) 42 **/ 43class PTWIO()(implicit p: Parameters) extends MMUIOBaseBundle with HasPtwConst { 44 val req = Flipped(DecoupledIO(new Bundle { 45 val req_info = new L2TlbInnerBundle() 46 val l3Hit = if (EnableSv48) Some(new Bool()) else None 47 val l2Hit = Bool() 48 val ppn = UInt(ptePPNLen.W) 49 val stage1Hit = Bool() 50 val stage1 = new PtwMergeResp 51 val bitmapCheck = Option.when(HasBitmapCheck)(new Bundle { 52 val jmp_bitmap_check = Bool() // super page in PtwCache ptw hit, but need bitmap check 53 val pte = UInt(XLEN.W) // Page Table Entry 54 val cfs = Vec(tlbcontiguous, Bool()) // Bitmap Check Failed Vector 55 val SPlevel = UInt(log2Up(Level).W) 56 }) 57 })) 58 val resp = DecoupledIO(new Bundle { 59 val source = UInt(bSourceWidth.W) 60 val s2xlate = UInt(2.W) 61 val resp = new PtwMergeResp 62 val h_resp = new HptwResp 63 }) 64 65 val llptw = DecoupledIO(new LLPTWInBundle()) 66 // NOTE: llptw change from "connect to llptw" to "connect to page cache" 67 // to avoid corner case that caused duplicate entries 68 69 val hptw = new Bundle { 70 val req = DecoupledIO(new Bundle { 71 val source = UInt(bSourceWidth.W) 72 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 73 val gvpn = UInt(ptePPNLen.W) 74 }) 75 val resp = Flipped(Valid(new Bundle { 76 val h_resp = Output(new HptwResp) 77 })) 78 } 79 val mem = new Bundle { 80 val req = DecoupledIO(new L2TlbMemReqBundle()) 81 val resp = Flipped(ValidIO(UInt(XLEN.W))) 82 val mask = Input(Bool()) 83 } 84 val pmp = new Bundle { 85 val req = ValidIO(new PMPReqBundle()) 86 val resp = Flipped(new PMPRespBundle()) 87 } 88 89 val refill = Output(new Bundle { 90 val req_info = new L2TlbInnerBundle() 91 val level = UInt(log2Up(Level + 1).W) 92 }) 93 val bitmap = Option.when(HasBitmapCheck)(new Bundle { 94 val req = DecoupledIO(new bitmapReqBundle()) 95 val resp = Flipped(DecoupledIO(new bitmapRespBundle())) 96 }) 97} 98 99class PTW()(implicit p: Parameters) extends XSModule with HasPtwConst with HasPerfEvents { 100 val io = IO(new PTWIO) 101 val sfence = io.sfence 102 val mem = io.mem 103 val req_s2xlate = Reg(UInt(2.W)) 104 val enableS2xlate = req_s2xlate =/= noS2xlate 105 val onlyS1xlate = req_s2xlate === onlyStage1 106 val onlyS2xlate = req_s2xlate === onlyStage2 107 108 // mbmc:bitmap csr 109 val mbmc = io.csr.mbmc 110 val bitmap_enable = (if (HasBitmapCheck) true.B else false.B) && mbmc.BME === 1.U && mbmc.CMODE === 0.U 111 112 val satp = Wire(new TlbSatpBundle()) 113 when (io.req.fire) { 114 satp := Mux(io.req.bits.req_info.s2xlate =/= noS2xlate, io.csr.vsatp, io.csr.satp) 115 } .otherwise { 116 satp := Mux(enableS2xlate, io.csr.vsatp, io.csr.satp) 117 } 118 val s1Pbmte = Mux(req_s2xlate =/= noS2xlate, io.csr.hPBMTE, io.csr.mPBMTE) 119 120 val mode = satp.mode 121 val hgatp = io.csr.hgatp 122 val flush = io.sfence.valid || io.csr.satp.changed || io.csr.vsatp.changed || io.csr.hgatp.changed 123 val s2xlate = enableS2xlate && !onlyS1xlate 124 val level = RegInit(3.U(log2Up(Level + 1).W)) 125 val af_level = RegInit(3.U(log2Up(Level + 1).W)) // access fault return this level 126 val gpf_level = RegInit(3.U(log2Up(Level + 1).W)) 127 val ppn = Reg(UInt(ptePPNLen.W)) 128 val vpn = Reg(UInt(vpnLen.W)) // vpn or gvpn(onlyS2xlate) 129 val levelNext = level - 1.U 130 val l3Hit = Reg(Bool()) 131 val l2Hit = Reg(Bool()) 132 val jmp_bitmap_check_w = if (HasBitmapCheck) { io.req.bits.bitmapCheck.get.jmp_bitmap_check && io.req.bits.req_info.s2xlate =/= onlyStage2 } else { false.B } 133 val jmp_bitmap_check_r = if (HasBitmapCheck) { RegEnable(jmp_bitmap_check_w, io.req.fire) } else { false.B } 134 val cache_pte = Option.when(HasBitmapCheck)(RegEnable(io.req.bits.bitmapCheck.get.pte.asTypeOf(new PteBundle().cloneType), io.req.fire)) 135 val pte = if (HasBitmapCheck) { Mux(jmp_bitmap_check_r, cache_pte.get, io.mem.resp.bits.asTypeOf(new PteBundle().cloneType)) } else { mem.resp.bits.asTypeOf(new PteBundle()) } 136 137 // s/w register 138 val s_pmp_check = RegInit(true.B) 139 val s_mem_req = RegInit(true.B) 140 val s_llptw_req = RegInit(true.B) 141 val w_mem_resp = RegInit(true.B) 142 val s_hptw_req = RegInit(true.B) 143 val w_hptw_resp = RegInit(true.B) 144 val s_last_hptw_req = RegInit(true.B) 145 val w_last_hptw_resp = RegInit(true.B) 146 // for updating "level" 147 val mem_addr_update = RegInit(false.B) 148 149 val s_bitmap_check = RegInit(true.B) 150 val w_bitmap_resp = RegInit(true.B) 151 val whether_need_bitmap_check = RegInit(false.B) 152 val bitmap_checkfailed = RegInit(false.B) 153 154 val idle = RegInit(true.B) 155 val finish = WireInit(false.B) 156 dontTouch(finish) 157 val vs_finish = WireInit(false.B) // need to wait for G-stage translate, should not do pmp check 158 dontTouch(vs_finish) 159 160 val hptw_pageFault = RegInit(false.B) 161 val hptw_accessFault = RegInit(false.B) 162 val need_last_s2xlate = RegInit(false.B) 163 val stage1Hit = RegEnable(io.req.bits.stage1Hit, io.req.fire) 164 val stage1 = RegEnable(io.req.bits.stage1, io.req.fire) 165 val hptw_resp_stage2 = Reg(Bool()) 166 val first_gvpn_check_fail = RegInit(false.B) 167 168 // use accessfault repersent bitmap check failed 169 val pte_isAf = Mux(bitmap_enable, pte.isAf() || bitmap_checkfailed, pte.isAf()) 170 val ppn_af = if (HasBitmapCheck) { 171 Mux(enableS2xlate, Mux(onlyS1xlate, pte_isAf, false.B), pte_isAf) // In two-stage address translation, stage 1 ppn is a vpn for host, so don't need to check ppn_high 172 } else { 173 Mux(enableS2xlate, Mux(onlyS1xlate, pte.isAf(), false.B), pte.isAf()) // In two-stage address translation, stage 1 ppn is a vpn for host, so don't need to check ppn_high 174 } 175 val pte_valid = RegInit(false.B) // avoid l1tlb pf from stage1 when gpf happens in the first s2xlate in PTW 176 177 val pageFault = pte.isPf(level, s1Pbmte) 178 val find_pte = pte.isLeaf() || ppn_af || pageFault 179 val to_find_pte = level === 1.U && find_pte === false.B 180 val source = RegEnable(io.req.bits.req_info.source, io.req.fire) 181 182 val sent_to_pmp = idle === false.B && (s_pmp_check === false.B || mem_addr_update) && !finish && !vs_finish && !first_gvpn_check_fail && !(find_pte && pte_valid) 183 val accessFault = RegEnable(io.pmp.resp.ld || io.pmp.resp.mmio, false.B, sent_to_pmp) 184 185 val l3addr = Wire(UInt(ptePaddrLen.W)) 186 val l2addr = Wire(UInt(ptePaddrLen.W)) 187 val l1addr = Wire(UInt(ptePaddrLen.W)) 188 val hptw_addr = Wire(UInt(ptePaddrLen.W)) 189 val mem_addr = Wire(UInt(PAddrBits.W)) 190 191 l3addr := MakeAddr(satp.ppn, getVpnn(vpn, 3)) 192 if (EnableSv48) { 193 when (mode === Sv48) { 194 l2addr := MakeAddr(Mux(l3Hit, ppn, pte.getPPN()), getVpnn(vpn, 2)) 195 } .otherwise { 196 l2addr := MakeAddr(satp.ppn, getVpnn(vpn, 2)) 197 } 198 } else { 199 l2addr := MakeAddr(satp.ppn, getVpnn(vpn, 2)) 200 } 201 l1addr := MakeAddr(Mux(l2Hit, ppn, pte.getPPN()), getVpnn(vpn, 1)) 202 hptw_addr := Mux(af_level === 3.U, l3addr, Mux(af_level === 2.U, l2addr, l1addr)) 203 mem_addr := hptw_addr(PAddrBits - 1, 0) 204 205 val hptw_resp = Reg(new HptwResp) 206 207 val update_full_gvpn_mem_resp = RegInit(false.B) 208 val full_gvpn_reg = Reg(UInt(ptePPNLen.W)) 209 val full_gvpn_wire = pte.getPPN() 210 val full_gvpn = Mux(update_full_gvpn_mem_resp, full_gvpn_wire, full_gvpn_reg) 211 212 val gpaddr = MuxCase(hptw_addr, Seq( 213 (stage1Hit || onlyS2xlate) -> Cat(full_gvpn, 0.U(offLen.W)), 214 !s_last_hptw_req -> Cat(MuxLookup(level, pte.getPPN())(Seq( 215 3.U -> Cat(pte.getPPN()(ptePPNLen - 1, vpnnLen * 3), vpn(vpnnLen * 3 - 1, 0)), 216 2.U -> Cat(pte.getPPN()(ptePPNLen - 1, vpnnLen * 2), vpn(vpnnLen * 2 - 1, 0)), 217 1.U -> Cat(pte.getPPN()(ptePPNLen - 1, vpnnLen), vpn(vpnnLen - 1, 0) 218 ))), 219 0.U(offLen.W)) 220 )) 221 val gvpn_gpf = 222 (!(hptw_pageFault || hptw_accessFault || ((pageFault || ppn_af) && pte_valid)) && 223 Mux( 224 s2xlate && io.csr.hgatp.mode === Sv39x4, 225 full_gvpn(ptePPNLen - 1, GPAddrBitsSv39x4 - offLen) =/= 0.U, 226 Mux( 227 s2xlate && io.csr.hgatp.mode === Sv48x4, 228 full_gvpn(ptePPNLen - 1, GPAddrBitsSv48x4 - offLen) =/= 0.U, 229 false.B 230 ) 231 )) || first_gvpn_check_fail 232 233 val guestFault = hptw_pageFault || hptw_accessFault || gvpn_gpf 234 val hpaddr = Cat(hptw_resp.genPPNS2(get_pn(gpaddr)), get_off(gpaddr)) 235 val fake_h_resp = WireInit(0.U.asTypeOf(new HptwResp)) 236 fake_h_resp.entry.tag := get_pn(gpaddr) 237 fake_h_resp.entry.vmid.map(_ := io.csr.hgatp.vmid) 238 fake_h_resp.gpf := true.B 239 240 val fake_pte = WireInit(0.U.asTypeOf(new PteBundle())) 241 fake_pte.perm.v := false.B // tell L1TLB this is fake pte 242 fake_pte.ppn := ppn(ppnLen - 1, 0) 243 fake_pte.ppn_high := ppn(ptePPNLen - 1, ppnLen) 244 245 io.req.ready := idle 246 val ptw_resp = Wire(new PtwMergeResp) 247 ptw_resp.apply(Mux(pte_valid, pageFault && !accessFault, false.B), (accessFault || ppn_af) && !(pte_valid && (pageFault || guestFault)), Mux(accessFault, af_level, Mux(guestFault, gpf_level, level)), Mux(pte_valid, pte, fake_pte), vpn, satp.asid, hgatp.vmid, vpn(sectortlbwidth - 1, 0), not_super = false, not_merge = false, bitmap_checkfailed.asBool) 248 249 val normal_resp = idle === false.B && mem_addr_update && !need_last_s2xlate && (guestFault || (w_mem_resp && find_pte) || (s_pmp_check && accessFault) || onlyS2xlate ) 250 val stageHit_resp = idle === false.B && hptw_resp_stage2 251 io.resp.valid := Mux(stage1Hit, stageHit_resp, normal_resp) 252 io.resp.bits.source := source 253 io.resp.bits.resp := Mux(stage1Hit || (l3Hit || l2Hit) && guestFault && !pte_valid, stage1, ptw_resp) 254 io.resp.bits.h_resp := Mux(gvpn_gpf, fake_h_resp, hptw_resp) 255 io.resp.bits.s2xlate := req_s2xlate 256 257 io.llptw.valid := s_llptw_req === false.B && to_find_pte && !accessFault && !guestFault 258 io.llptw.bits.req_info.source := source 259 io.llptw.bits.req_info.vpn := vpn 260 io.llptw.bits.req_info.s2xlate := req_s2xlate 261 io.llptw.bits.ppn := DontCare 262 if (HasBitmapCheck) { 263 io.llptw.bits.bitmapCheck.get.jmp_bitmap_check := DontCare 264 io.llptw.bits.bitmapCheck.get.ptes := DontCare 265 io.llptw.bits.bitmapCheck.get.cfs := DontCare 266 io.llptw.bits.bitmapCheck.get.hitway := DontCare 267 } 268 269 io.pmp.req.valid := DontCare // samecycle, do not use valid 270 io.pmp.req.bits.addr := Mux(s2xlate, hpaddr, mem_addr) 271 io.pmp.req.bits.size := 3.U // TODO: fix it 272 io.pmp.req.bits.cmd := TlbCmd.read 273 274 if (HasBitmapCheck) { 275 val cache_level = RegEnable(io.req.bits.bitmapCheck.get.SPlevel, io.req.fire) 276 io.bitmap.get.req.valid := !s_bitmap_check 277 io.bitmap.get.req.bits.bmppn := pte.ppn 278 io.bitmap.get.req.bits.id := FsmReqID.U(bMemID.W) 279 io.bitmap.get.req.bits.vpn := vpn 280 io.bitmap.get.req.bits.level := Mux(jmp_bitmap_check_r, cache_level, level) 281 io.bitmap.get.req.bits.way_info := DontCare 282 io.bitmap.get.req.bits.hptw_bypassed := false.B 283 io.bitmap.get.resp.ready := !w_bitmap_resp 284 } 285 mem.req.valid := s_mem_req === false.B && !mem.mask && !accessFault && s_pmp_check 286 mem.req.bits.addr := Mux(s2xlate, hpaddr, mem_addr) 287 mem.req.bits.id := FsmReqID.U(bMemID.W) 288 mem.req.bits.hptw_bypassed := false.B 289 290 io.refill.req_info.s2xlate := req_s2xlate 291 io.refill.req_info.vpn := vpn 292 io.refill.level := level 293 io.refill.req_info.source := source 294 295 io.hptw.req.valid := !s_hptw_req || !s_last_hptw_req 296 io.hptw.req.bits.id := FsmReqID.U(bMemID.W) 297 io.hptw.req.bits.gvpn := get_pn(gpaddr) 298 io.hptw.req.bits.source := source 299 300 if (HasBitmapCheck) { 301 when (io.req.fire && jmp_bitmap_check_w) { 302 idle := false.B 303 req_s2xlate := io.req.bits.req_info.s2xlate 304 vpn := io.req.bits.req_info.vpn 305 s_bitmap_check := false.B 306 need_last_s2xlate := false.B 307 hptw_pageFault := false.B 308 hptw_accessFault := false.B 309 level := io.req.bits.bitmapCheck.get.SPlevel 310 pte_valid := true.B 311 accessFault := false.B 312 } 313 } 314 315 when (io.req.fire && io.req.bits.stage1Hit && (if (HasBitmapCheck) !jmp_bitmap_check_w else true.B)) { 316 idle := false.B 317 req_s2xlate := io.req.bits.req_info.s2xlate 318 s_last_hptw_req := false.B 319 hptw_resp_stage2 := false.B 320 need_last_s2xlate := false.B 321 hptw_pageFault := false.B 322 hptw_accessFault := false.B 323 full_gvpn_reg := io.req.bits.stage1.genPPN() 324 } 325 326 when (io.resp.fire && stage1Hit){ 327 idle := true.B 328 } 329 330 when (io.req.fire && !io.req.bits.stage1Hit && (if (HasBitmapCheck) !jmp_bitmap_check_w else true.B)) { 331 val req = io.req.bits 332 val gvpn_wire = Wire(UInt(ptePPNLen.W)) 333 if (EnableSv48) { 334 when (mode === Sv48) { 335 level := Mux(req.l2Hit, 1.U, Mux(req.l3Hit.get, 2.U, 3.U)) 336 af_level := Mux(req.l2Hit, 1.U, Mux(req.l3Hit.get, 2.U, 3.U)) 337 gpf_level := Mux(req.l2Hit, 2.U, Mux(req.l3Hit.get, 3.U, 0.U)) 338 ppn := Mux(req.l2Hit || req.l3Hit.get, io.req.bits.ppn, satp.ppn) 339 l3Hit := req.l3Hit.get 340 gvpn_wire := Mux(req.l2Hit || req.l3Hit.get, io.req.bits.ppn, satp.ppn) 341 } .otherwise { 342 level := Mux(req.l2Hit, 1.U, 2.U) 343 af_level := Mux(req.l2Hit, 1.U, 2.U) 344 gpf_level := Mux(req.l2Hit, 2.U, 0.U) 345 ppn := Mux(req.l2Hit, io.req.bits.ppn, satp.ppn) 346 l3Hit := false.B 347 gvpn_wire := Mux(req.l2Hit, io.req.bits.ppn, satp.ppn) 348 } 349 } else { 350 level := Mux(req.l2Hit, 1.U, 2.U) 351 af_level := Mux(req.l2Hit, 1.U, 2.U) 352 gpf_level := Mux(req.l2Hit, 2.U, 0.U) 353 ppn := Mux(req.l2Hit, io.req.bits.ppn, satp.ppn) 354 l3Hit := false.B 355 gvpn_wire := Mux(req.l2Hit, io.req.bits.ppn, satp.ppn) 356 } 357 vpn := io.req.bits.req_info.vpn 358 l2Hit := req.l2Hit 359 accessFault := false.B 360 idle := false.B 361 hptw_pageFault := false.B 362 hptw_accessFault := false.B 363 pte_valid := false.B 364 req_s2xlate := io.req.bits.req_info.s2xlate 365 when(io.req.bits.req_info.s2xlate === onlyStage2){ 366 full_gvpn_reg := io.req.bits.req_info.vpn 367 val onlys2_gpaddr = Cat(io.req.bits.req_info.vpn, 0.U(offLen.W)) // is 50 bits, don't need to check high bits when sv48x4 is enabled 368 val check_gpa_high_fail = Mux(io.req.bits.req_info.s2xlate === onlyStage2 && io.csr.hgatp.mode === Sv39x4, onlys2_gpaddr(onlys2_gpaddr.getWidth - 1, GPAddrBitsSv39x4) =/= 0.U, false.B) 369 need_last_s2xlate := false.B 370 when(check_gpa_high_fail){ 371 mem_addr_update := true.B 372 first_gvpn_check_fail := true.B 373 }.otherwise{ 374 s_last_hptw_req := false.B 375 } 376 }.elsewhen(io.req.bits.req_info.s2xlate === allStage){ 377 full_gvpn_reg := 0.U 378 val allstage_gpaddr = Cat(gvpn_wire, 0.U(offLen.W)) 379 val check_gpa_high_fail = Mux(io.csr.hgatp.mode === Sv39x4, allstage_gpaddr(allstage_gpaddr.getWidth - 1, GPAddrBitsSv39x4) =/= 0.U, Mux(io.csr.hgatp.mode === Sv48x4, allstage_gpaddr(allstage_gpaddr.getWidth - 1, GPAddrBitsSv48x4) =/= 0.U, false.B)) 380 when(check_gpa_high_fail){ 381 mem_addr_update := true.B 382 first_gvpn_check_fail := true.B 383 }.otherwise{ 384 need_last_s2xlate := true.B 385 s_hptw_req := false.B 386 } 387 }.otherwise { 388 full_gvpn_reg := 0.U 389 need_last_s2xlate := false.B 390 s_pmp_check := false.B 391 } 392 } 393 394 when(io.hptw.req.fire && s_hptw_req === false.B){ 395 s_hptw_req := true.B 396 w_hptw_resp := false.B 397 } 398 399 when(io.hptw.resp.fire && w_hptw_resp === false.B) { 400 w_hptw_resp := true.B 401 val g_perm_fail = !io.hptw.resp.bits.h_resp.gaf && (!io.hptw.resp.bits.h_resp.entry.perm.get.r && !(io.csr.priv.mxr && io.hptw.resp.bits.h_resp.entry.perm.get.x)) 402 hptw_pageFault := io.hptw.resp.bits.h_resp.gpf || g_perm_fail 403 hptw_accessFault := io.hptw.resp.bits.h_resp.gaf 404 hptw_resp := io.hptw.resp.bits.h_resp 405 hptw_resp.gpf := io.hptw.resp.bits.h_resp.gpf || g_perm_fail 406 when(!(g_perm_fail || io.hptw.resp.bits.h_resp.gpf || io.hptw.resp.bits.h_resp.gaf)) { 407 s_pmp_check := false.B 408 }.otherwise { 409 mem_addr_update := true.B 410 need_last_s2xlate := false.B 411 } 412 } 413 414 when(io.hptw.req.fire && s_last_hptw_req === false.B) { 415 w_last_hptw_resp := false.B 416 s_last_hptw_req := true.B 417 } 418 419 when (io.hptw.resp.fire && w_last_hptw_resp === false.B && stage1Hit){ 420 w_last_hptw_resp := true.B 421 hptw_resp_stage2 := true.B 422 hptw_resp := io.hptw.resp.bits.h_resp 423 } 424 425 when(io.hptw.resp.fire && w_last_hptw_resp === false.B && !stage1Hit){ 426 hptw_pageFault := io.hptw.resp.bits.h_resp.gpf 427 hptw_accessFault := io.hptw.resp.bits.h_resp.gaf 428 hptw_resp := io.hptw.resp.bits.h_resp 429 w_last_hptw_resp := true.B 430 mem_addr_update := true.B 431 } 432 433 when(sent_to_pmp && mem_addr_update === false.B){ 434 s_mem_req := false.B 435 s_pmp_check := true.B 436 } 437 438 when(accessFault && idle === false.B){ 439 s_pmp_check := true.B 440 s_mem_req := true.B 441 w_mem_resp := true.B 442 s_llptw_req := true.B 443 s_hptw_req := true.B 444 w_hptw_resp := true.B 445 s_last_hptw_req := true.B 446 w_last_hptw_resp := true.B 447 mem_addr_update := true.B 448 need_last_s2xlate := false.B 449 if (HasBitmapCheck) { 450 s_bitmap_check := true.B 451 w_bitmap_resp := true.B 452 whether_need_bitmap_check := false.B 453 bitmap_checkfailed := false.B 454 } 455 } 456 457 when(guestFault && idle === false.B){ 458 s_pmp_check := true.B 459 s_mem_req := true.B 460 w_mem_resp := true.B 461 s_llptw_req := true.B 462 s_hptw_req := true.B 463 w_hptw_resp := true.B 464 s_last_hptw_req := true.B 465 w_last_hptw_resp := true.B 466 mem_addr_update := true.B 467 need_last_s2xlate := false.B 468 if (HasBitmapCheck) { 469 s_bitmap_check := true.B 470 w_bitmap_resp := true.B 471 whether_need_bitmap_check := false.B 472 bitmap_checkfailed := false.B 473 } 474 } 475 476 when (mem.req.fire){ 477 s_mem_req := true.B 478 w_mem_resp := false.B 479 } 480 481 when(mem.resp.fire && w_mem_resp === false.B){ 482 w_mem_resp := true.B 483 af_level := af_level - 1.U 484 gpf_level := Mux(mode === Sv39 && !pte_valid && !l2Hit, gpf_level - 2.U, gpf_level - 1.U) 485 pte_valid := true.B 486 update_full_gvpn_mem_resp := true.B 487 if (HasBitmapCheck) { 488 when (bitmap_enable) { 489 whether_need_bitmap_check := true.B 490 } .otherwise { 491 s_llptw_req := false.B 492 mem_addr_update := true.B 493 whether_need_bitmap_check := false.B 494 } 495 } else { 496 s_llptw_req := false.B 497 mem_addr_update := true.B 498 } 499 } 500 501 when(update_full_gvpn_mem_resp) { 502 update_full_gvpn_mem_resp := false.B 503 full_gvpn_reg := pte.getPPN() 504 } 505 506 if (HasBitmapCheck) { 507 when (whether_need_bitmap_check) { 508 when (bitmap_enable && (!enableS2xlate || onlyS1xlate) && pte.isLeaf()) { 509 s_bitmap_check := false.B 510 whether_need_bitmap_check := false.B 511 } .otherwise { 512 mem_addr_update := true.B 513 s_llptw_req := false.B 514 whether_need_bitmap_check := false.B 515 } 516 } 517 // bitmapcheck 518 when (io.bitmap.get.req.fire) { 519 s_bitmap_check := true.B 520 w_bitmap_resp := false.B 521 } 522 when (io.bitmap.get.resp.fire) { 523 w_bitmap_resp := true.B 524 mem_addr_update := true.B 525 bitmap_checkfailed := io.bitmap.get.resp.bits.cf 526 } 527 } 528 529 when(mem_addr_update){ 530 when(level >= 2.U && !onlyS2xlate && !(guestFault || find_pte || accessFault)) { 531 level := levelNext 532 when(s2xlate){ 533 s_hptw_req := false.B 534 vs_finish := true.B 535 }.otherwise{ 536 s_mem_req := false.B 537 } 538 s_llptw_req := true.B 539 mem_addr_update := false.B 540 }.elsewhen(io.llptw.valid){ 541 when(io.llptw.fire) { 542 idle := true.B 543 s_llptw_req := true.B 544 mem_addr_update := false.B 545 need_last_s2xlate := false.B 546 } 547 finish := true.B 548 }.elsewhen(s2xlate && need_last_s2xlate === true.B) { 549 need_last_s2xlate := false.B 550 when(!(guestFault || accessFault || pageFault || ppn_af)){ 551 s_last_hptw_req := false.B 552 mem_addr_update := false.B 553 } 554 }.elsewhen(io.resp.valid){ 555 when(io.resp.fire) { 556 idle := true.B 557 s_llptw_req := true.B 558 mem_addr_update := false.B 559 accessFault := false.B 560 first_gvpn_check_fail := false.B 561 } 562 finish := true.B 563 } 564 } 565 566 567 when (flush) { 568 idle := true.B 569 s_pmp_check := true.B 570 s_mem_req := true.B 571 s_llptw_req := true.B 572 w_mem_resp := true.B 573 accessFault := false.B 574 mem_addr_update := false.B 575 first_gvpn_check_fail := false.B 576 s_hptw_req := true.B 577 w_hptw_resp := true.B 578 s_last_hptw_req := true.B 579 w_last_hptw_resp := true.B 580 if (HasBitmapCheck) { 581 s_bitmap_check := true.B 582 w_bitmap_resp := true.B 583 whether_need_bitmap_check := false.B 584 bitmap_checkfailed := false.B 585 } 586 } 587 588 589 XSDebug(p"[ptw] level:${level} notFound:${pageFault}\n") 590 591 // perf 592 XSPerfAccumulate("fsm_count", io.req.fire) 593 for (i <- 0 until PtwWidth) { 594 XSPerfAccumulate(s"fsm_count_source${i}", io.req.fire && io.req.bits.req_info.source === i.U) 595 } 596 XSPerfAccumulate("fsm_busy", !idle) 597 XSPerfAccumulate("fsm_idle", idle) 598 XSPerfAccumulate("resp_blocked", io.resp.valid && !io.resp.ready) 599 XSPerfAccumulate("ptw_ppn_af", io.resp.fire && ppn_af) 600 XSPerfAccumulate("mem_count", mem.req.fire) 601 XSPerfAccumulate("mem_cycle", BoolStopWatch(mem.req.fire, mem.resp.fire, true)) 602 XSPerfAccumulate("mem_blocked", mem.req.valid && !mem.req.ready) 603 604 val perfEvents = Seq( 605 ("fsm_count ", io.req.fire ), 606 ("fsm_busy ", !idle ), 607 ("fsm_idle ", idle ), 608 ("resp_blocked ", io.resp.valid && !io.resp.ready ), 609 ("mem_count ", mem.req.fire ), 610 ("mem_cycle ", BoolStopWatch(mem.req.fire, mem.resp.fire, true)), 611 ("mem_blocked ", mem.req.valid && !mem.req.ready ), 612 ) 613 generatePerfEvent() 614} 615 616/*========================= LLPTW ==============================*/ 617 618/** LLPTW : Last Level Page Table Walker 619 * the page walker that only takes 4KB(last level) page walk. 620 **/ 621 622class LLPTWInBundle(implicit p: Parameters) extends XSBundle with HasPtwConst { 623 val req_info = Output(new L2TlbInnerBundle()) 624 val ppn = Output(UInt(ptePPNLen.W)) 625 val bitmapCheck = Option.when(HasBitmapCheck)(new Bundle { 626 val jmp_bitmap_check = Bool() // find pte in l0 or sp, but need bitmap check 627 val ptes = Vec(tlbcontiguous, UInt(XLEN.W)) // Page Table Entry Vector 628 val cfs = Vec(tlbcontiguous, Bool()) // Bitmap Check Failed Vector 629 val hitway = UInt(l2tlbParams.l0nWays.W) 630 }) 631} 632 633class LLPTWIO(implicit p: Parameters) extends MMUIOBaseBundle with HasPtwConst { 634 val in = Flipped(DecoupledIO(new LLPTWInBundle())) 635 val out = DecoupledIO(new Bundle { 636 val req_info = Output(new L2TlbInnerBundle()) 637 val id = Output(UInt(bMemID.W)) 638 val h_resp = Output(new HptwResp) 639 val first_s2xlate_fault = Output(Bool()) // Whether the first stage 2 translation occurs pf/af 640 val af = Output(Bool()) 641 val bitmapCheck = Option.when(HasBitmapCheck)(new Bundle { 642 val jmp_bitmap_check = Bool() // find pte in l0 or sp, but need bitmap check 643 val ptes = Vec(tlbcontiguous, UInt(XLEN.W)) // Page Table Entry Vector 644 val cfs = Vec(tlbcontiguous, Bool()) // Bitmap Check Failed Vector 645 }) 646 }) 647 val mem = new Bundle { 648 val req = DecoupledIO(new L2TlbMemReqBundle()) 649 val resp = Flipped(Valid(new Bundle { 650 val id = Output(UInt(log2Up(l2tlbParams.llptwsize).W)) 651 val value = Output(UInt(blockBits.W)) 652 })) 653 val enq_ptr = Output(UInt(log2Ceil(l2tlbParams.llptwsize).W)) 654 val buffer_it = Output(Vec(l2tlbParams.llptwsize, Bool())) 655 val refill = Output(new L2TlbInnerBundle()) 656 val req_mask = Input(Vec(l2tlbParams.llptwsize, Bool())) 657 val flush_latch = Input(Vec(l2tlbParams.llptwsize, Bool())) 658 } 659 val cache = DecoupledIO(new L2TlbInnerBundle()) 660 val pmp = new Bundle { 661 val req = Valid(new PMPReqBundle()) 662 val resp = Flipped(new PMPRespBundle()) 663 } 664 val hptw = new Bundle { 665 val req = DecoupledIO(new Bundle{ 666 val source = UInt(bSourceWidth.W) 667 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 668 val gvpn = UInt(ptePPNLen.W) 669 }) 670 val resp = Flipped(Valid(new Bundle { 671 val id = Output(UInt(log2Up(l2tlbParams.llptwsize).W)) 672 val h_resp = Output(new HptwResp) 673 })) 674 } 675 val bitmap = Option.when(HasBitmapCheck)(new Bundle { 676 val req = DecoupledIO(new bitmapReqBundle()) 677 val resp = Flipped(DecoupledIO(new bitmapRespBundle())) 678 }) 679 680 val l0_way_info = Option.when(HasBitmapCheck)(Input(UInt(l2tlbParams.l0nWays.W))) 681} 682 683class LLPTWEntry(implicit p: Parameters) extends XSBundle with HasPtwConst { 684 val req_info = new L2TlbInnerBundle() 685 val ppn = UInt(ptePPNLen.W) 686 val wait_id = UInt(log2Up(l2tlbParams.llptwsize).W) 687 val af = Bool() 688 val hptw_resp = new HptwResp() 689 val first_s2xlate_fault = Output(Bool()) 690 val cf = Bool() 691 val from_l0 = Bool() 692 val way_info = UInt(l2tlbParams.l0nWays.W) 693 val jmp_bitmap_check = Bool() 694 val ptes = Vec(tlbcontiguous, UInt(XLEN.W)) 695 val cfs = Vec(tlbcontiguous, Bool()) 696} 697 698 699class LLPTW(implicit p: Parameters) extends XSModule with HasPtwConst with HasPerfEvents { 700 val io = IO(new LLPTWIO()) 701 702 // mbmc:bitmap csr 703 val mbmc = io.csr.mbmc 704 val bitmap_enable = (if (HasBitmapCheck) true.B else false.B) && mbmc.BME === 1.U && mbmc.CMODE === 0.U 705 706 val flush = io.sfence.valid || io.csr.satp.changed || io.csr.vsatp.changed || io.csr.hgatp.changed 707 val entries = RegInit(VecInit(Seq.fill(l2tlbParams.llptwsize)(0.U.asTypeOf(new LLPTWEntry())))) 708 val state_idle :: state_hptw_req :: state_hptw_resp :: state_addr_check :: state_mem_req :: state_mem_waiting :: state_mem_out :: state_last_hptw_req :: state_last_hptw_resp :: state_cache :: state_bitmap_check :: state_bitmap_resp :: Nil = Enum(12) 709 val state = RegInit(VecInit(Seq.fill(l2tlbParams.llptwsize)(state_idle))) 710 711 val is_emptys = state.map(_ === state_idle) 712 val is_mems = state.map(_ === state_mem_req) 713 val is_waiting = state.map(_ === state_mem_waiting) 714 val is_having = state.map(_ === state_mem_out) 715 val is_cache = state.map(_ === state_cache) 716 val is_hptw_req = state.map(_ === state_hptw_req) 717 val is_last_hptw_req = state.map(_ === state_last_hptw_req) 718 val is_hptw_resp = state.map(_ === state_hptw_resp) 719 val is_last_hptw_resp = state.map(_ === state_last_hptw_resp) 720 val is_bitmap_req = state.map(_ === state_bitmap_check) 721 val is_bitmap_resp = state.map(_ === state_bitmap_resp) 722 723 val full = !ParallelOR(is_emptys).asBool 724 val enq_ptr = ParallelPriorityEncoder(is_emptys) 725 726 val mem_ptr = ParallelPriorityEncoder(is_having) // TODO: optimize timing, bad: entries -> ptr -> entry 727 val mem_arb = Module(new RRArbiterInit(new LLPTWEntry(), l2tlbParams.llptwsize)) 728 for (i <- 0 until l2tlbParams.llptwsize) { 729 mem_arb.io.in(i).bits := entries(i) 730 mem_arb.io.in(i).valid := is_mems(i) && !io.mem.req_mask(i) 731 } 732 733 // process hptw requests in serial 734 val hyper_arb1 = Module(new RRArbiterInit(new LLPTWEntry(), l2tlbParams.llptwsize)) 735 for (i <- 0 until l2tlbParams.llptwsize) { 736 hyper_arb1.io.in(i).bits := entries(i) 737 hyper_arb1.io.in(i).valid := is_hptw_req(i) && !(Cat(is_hptw_resp).orR) && !(Cat(is_last_hptw_resp).orR) 738 } 739 val hyper_arb2 = Module(new RRArbiterInit(new LLPTWEntry(), l2tlbParams.llptwsize)) 740 for(i <- 0 until l2tlbParams.llptwsize) { 741 hyper_arb2.io.in(i).bits := entries(i) 742 hyper_arb2.io.in(i).valid := is_last_hptw_req(i) && !(Cat(is_hptw_resp).orR) && !(Cat(is_last_hptw_resp).orR) 743 } 744 745 746 val bitmap_arb = Option.when(HasBitmapCheck)(Module(new RRArbiter(new bitmapReqBundle(), l2tlbParams.llptwsize))) 747 val way_info = Option.when(HasBitmapCheck)(Wire(Vec(l2tlbParams.llptwsize, UInt(l2tlbParams.l0nWays.W)))) 748 if (HasBitmapCheck) { 749 for (i <- 0 until l2tlbParams.llptwsize) { 750 bitmap_arb.get.io.in(i).valid := is_bitmap_req(i) 751 bitmap_arb.get.io.in(i).bits.bmppn := entries(i).ppn 752 bitmap_arb.get.io.in(i).bits.vpn := entries(i).req_info.vpn 753 bitmap_arb.get.io.in(i).bits.id := i.U 754 bitmap_arb.get.io.in(i).bits.level := 0.U // last level 755 bitmap_arb.get.io.in(i).bits.way_info := Mux(entries(i).from_l0, entries(i).way_info, way_info.get(i)) 756 bitmap_arb.get.io.in(i).bits.hptw_bypassed := false.B 757 } 758 } 759 760 val cache_ptr = ParallelMux(is_cache, (0 until l2tlbParams.llptwsize).map(_.U(log2Up(l2tlbParams.llptwsize).W))) 761 762 // duplicate req 763 // to_wait: wait for the last to access mem, set to mem_resp 764 // to_cache: the last is back just right now, set to mem_cache 765 val dup_vec = state.indices.map(i => 766 dup(io.in.bits.req_info.vpn, entries(i).req_info.vpn) && io.in.bits.req_info.s2xlate === entries(i).req_info.s2xlate 767 ) 768 val dup_req_fire = mem_arb.io.out.fire && dup(io.in.bits.req_info.vpn, mem_arb.io.out.bits.req_info.vpn) && io.in.bits.req_info.s2xlate === mem_arb.io.out.bits.req_info.s2xlate // dup with the req fire entry 769 val dup_vec_wait = dup_vec.zip(is_waiting).map{case (d, w) => d && w} // dup with "mem_waiting" entries, sending mem req already 770 val dup_vec_having = dup_vec.zipWithIndex.map{case (d, i) => d && is_having(i)} // dup with the "mem_out" entry recv the data just now 771 val dup_vec_bitmap = dup_vec.zipWithIndex.map{case (d, i) => d && (is_bitmap_req(i) || is_bitmap_resp(i))} 772 val dup_vec_last_hptw = dup_vec.zipWithIndex.map{case (d, i) => d && (is_last_hptw_req(i) || is_last_hptw_resp(i))} 773 val wait_id = Mux(dup_req_fire, mem_arb.io.chosen, ParallelMux(dup_vec_wait zip entries.map(_.wait_id))) 774 val dup_wait_resp = io.mem.resp.fire && VecInit(dup_vec_wait)(io.mem.resp.bits.id) && !io.mem.flush_latch(io.mem.resp.bits.id) // dup with the entry that data coming next cycle 775 val to_wait = Cat(dup_vec_wait).orR || dup_req_fire 776 val to_mem_out = dup_wait_resp && ((entries(io.mem.resp.bits.id).req_info.s2xlate === noS2xlate) || (entries(io.mem.resp.bits.id).req_info.s2xlate === onlyStage1)) && !bitmap_enable 777 val to_bitmap_req = (if (HasBitmapCheck) true.B else false.B) && dup_wait_resp && ((entries(io.mem.resp.bits.id).req_info.s2xlate === noS2xlate) || (entries(io.mem.resp.bits.id).req_info.s2xlate === onlyStage1)) && bitmap_enable 778 val to_cache = if (HasBitmapCheck) Cat(dup_vec_bitmap).orR || Cat(dup_vec_having).orR || Cat(dup_vec_last_hptw).orR 779 else Cat(dup_vec_having).orR || Cat(dup_vec_last_hptw).orR 780 val to_hptw_req = io.in.bits.req_info.s2xlate === allStage 781 val to_last_hptw_req = dup_wait_resp && entries(io.mem.resp.bits.id).req_info.s2xlate === allStage 782 val last_hptw_req_id = io.mem.resp.bits.id 783 val req_paddr = MakeAddr(io.in.bits.ppn(ppnLen-1, 0), getVpnn(io.in.bits.req_info.vpn, 0)) 784 val req_hpaddr = MakeAddr(entries(last_hptw_req_id).hptw_resp.genPPNS2(get_pn(req_paddr)), getVpnn(io.in.bits.req_info.vpn, 0)) 785 val index = Mux(entries(last_hptw_req_id).req_info.s2xlate === allStage, req_hpaddr, req_paddr)(log2Up(l2tlbParams.blockBytes)-1, log2Up(XLEN/8)) 786 val last_hptw_req_ppn = io.mem.resp.bits.value.asTypeOf(Vec(blockBits / XLEN, new PteBundle()))(index).getPPN() 787 XSError(RegNext(dup_req_fire && Cat(dup_vec_wait).orR, init = false.B), "mem req but some entries already waiting, should not happed") 788 789 XSError(io.in.fire && ((to_mem_out && to_cache) || (to_wait && to_cache)), "llptw enq, to cache conflict with to mem") 790 val mem_resp_hit = RegInit(VecInit(Seq.fill(l2tlbParams.llptwsize)(false.B))) 791 val enq_state_normal = MuxCase(state_addr_check, Seq( 792 to_mem_out -> state_mem_out, // same to the blew, but the mem resp now 793 to_bitmap_req -> state_bitmap_check, 794 to_last_hptw_req -> state_last_hptw_req, 795 to_wait -> state_mem_waiting, 796 to_cache -> state_cache, 797 to_hptw_req -> state_hptw_req 798 )) 799 val enq_state = Mux(from_pre(io.in.bits.req_info.source) && enq_state_normal =/= state_addr_check, state_idle, enq_state_normal) 800 when (io.in.fire && (if (HasBitmapCheck) !io.in.bits.bitmapCheck.get.jmp_bitmap_check else true.B)) { 801 // if prefetch req does not need mem access, just give it up. 802 // so there will be at most 1 + FilterSize entries that needs re-access page cache 803 // so 2 + FilterSize is enough to avoid dead-lock 804 state(enq_ptr) := enq_state 805 entries(enq_ptr).req_info := io.in.bits.req_info 806 entries(enq_ptr).ppn := Mux(to_last_hptw_req, last_hptw_req_ppn, io.in.bits.ppn) 807 entries(enq_ptr).wait_id := Mux(to_wait, wait_id, enq_ptr) 808 entries(enq_ptr).af := false.B 809 if (HasBitmapCheck) { 810 entries(enq_ptr).cf := false.B 811 entries(enq_ptr).from_l0 := false.B 812 entries(enq_ptr).way_info := 0.U 813 entries(enq_ptr).jmp_bitmap_check := false.B 814 for (i <- 0 until tlbcontiguous) { 815 entries(enq_ptr).ptes(i) := 0.U 816 } 817 entries(enq_ptr).cfs := io.in.bits.bitmapCheck.get.cfs 818 } 819 entries(enq_ptr).hptw_resp := Mux(to_last_hptw_req, entries(last_hptw_req_id).hptw_resp, Mux(to_wait, entries(wait_id).hptw_resp, entries(enq_ptr).hptw_resp)) 820 entries(enq_ptr).first_s2xlate_fault := false.B 821 mem_resp_hit(enq_ptr) := to_bitmap_req || to_mem_out || to_last_hptw_req 822 } 823 824 if (HasBitmapCheck) { 825 when (io.in.bits.bitmapCheck.get.jmp_bitmap_check && io.in.fire) { 826 state(enq_ptr) := state_bitmap_check 827 entries(enq_ptr).req_info := io.in.bits.req_info 828 entries(enq_ptr).ppn := io.in.bits.bitmapCheck.get.ptes(io.in.bits.req_info.vpn(sectortlbwidth - 1, 0)).asTypeOf(new PteBundle().cloneType).ppn 829 entries(enq_ptr).wait_id := enq_ptr 830 entries(enq_ptr).af := false.B 831 entries(enq_ptr).cf := false.B 832 entries(enq_ptr).from_l0 := true.B 833 entries(enq_ptr).way_info := io.in.bits.bitmapCheck.get.hitway 834 entries(enq_ptr).jmp_bitmap_check := io.in.bits.bitmapCheck.get.jmp_bitmap_check 835 entries(enq_ptr).ptes := io.in.bits.bitmapCheck.get.ptes 836 entries(enq_ptr).cfs := io.in.bits.bitmapCheck.get.cfs 837 mem_resp_hit(enq_ptr) := false.B 838 } 839 } 840 841 val enq_ptr_reg = RegNext(enq_ptr) 842 val need_addr_check = GatedValidRegNext(enq_state === state_addr_check && io.in.fire && !flush && (if (HasBitmapCheck) !io.in.bits.bitmapCheck.get.jmp_bitmap_check else true.B)) 843 844 val hasHptwResp = ParallelOR(state.map(_ === state_hptw_resp)).asBool 845 val hptw_resp_ptr_reg = RegNext(io.hptw.resp.bits.id) 846 val hptw_need_addr_check = RegNext(hasHptwResp && io.hptw.resp.fire && !flush) && state(hptw_resp_ptr_reg) === state_addr_check 847 848 val ptes = io.mem.resp.bits.value.asTypeOf(Vec(blockBits / XLEN, new PteBundle())) 849 val gpaddr = MakeGPAddr(entries(hptw_resp_ptr_reg).ppn, getVpnn(entries(hptw_resp_ptr_reg).req_info.vpn, 0)) 850 val hptw_resp = entries(hptw_resp_ptr_reg).hptw_resp 851 val hpaddr = Cat(hptw_resp.genPPNS2(get_pn(gpaddr)), get_off(gpaddr)) 852 val addr = RegEnable(MakeAddr(io.in.bits.ppn(ppnLen - 1, 0), getVpnn(io.in.bits.req_info.vpn, 0)), io.in.fire) 853 io.pmp.req.valid := need_addr_check || hptw_need_addr_check 854 io.pmp.req.bits.addr := Mux(hptw_need_addr_check, hpaddr, addr) 855 io.pmp.req.bits.cmd := TlbCmd.read 856 io.pmp.req.bits.size := 3.U // TODO: fix it 857 val pmp_resp_valid = io.pmp.req.valid // same cycle 858 when (pmp_resp_valid) { 859 // NOTE: when pmp resp but state is not addr check, then the entry is dup with other entry, the state was changed before 860 // when dup with the req-ing entry, set to mem_waiting (above codes), and the ld must be false, so dontcare 861 val ptr = Mux(hptw_need_addr_check, hptw_resp_ptr_reg, enq_ptr_reg); 862 val accessFault = io.pmp.resp.ld || io.pmp.resp.mmio 863 entries(ptr).af := accessFault 864 state(ptr) := Mux(accessFault, state_mem_out, state_mem_req) 865 } 866 867 when (mem_arb.io.out.fire) { 868 for (i <- state.indices) { 869 when (state(i) =/= state_idle && state(i) =/= state_mem_out && state(i) =/= state_last_hptw_req && state(i) =/= state_last_hptw_resp 870 && (if (HasBitmapCheck) state(i) =/= state_bitmap_check && state(i) =/= state_bitmap_resp else true.B) 871 && entries(i).req_info.s2xlate === mem_arb.io.out.bits.req_info.s2xlate 872 && dup(entries(i).req_info.vpn, mem_arb.io.out.bits.req_info.vpn)) { 873 // NOTE: "dup enq set state to mem_wait" -> "sending req set other dup entries to mem_wait" 874 state(i) := state_mem_waiting 875 entries(i).hptw_resp := entries(mem_arb.io.chosen).hptw_resp 876 entries(i).wait_id := mem_arb.io.chosen 877 } 878 } 879 } 880 when (io.mem.resp.fire) { 881 state.indices.map{i => 882 when (state(i) === state_mem_waiting && io.mem.resp.bits.id === entries(i).wait_id) { 883 val req_paddr = MakeAddr(entries(i).ppn, getVpnn(entries(i).req_info.vpn, 0)) 884 val req_hpaddr = MakeAddr(entries(i).hptw_resp.genPPNS2(get_pn(req_paddr)), getVpnn(entries(i).req_info.vpn, 0)) 885 val index = Mux(entries(i).req_info.s2xlate === allStage, req_hpaddr, req_paddr)(log2Up(l2tlbParams.blockBytes)-1, log2Up(XLEN/8)) 886 val enableS2xlate = entries(i).req_info.s2xlate =/= noS2xlate 887 val s1Pbmte = Mux(enableS2xlate, io.csr.hPBMTE, io.csr.mPBMTE) 888 val vsStagePf = ptes(index).isPf(0.U, s1Pbmte) || !ptes(index).isLeaf() // Pagefault in vs-Stage 889 // Pagefault in g-Stage; when vsStagePf valid, should not check gStagepf 890 val gStagePf = ptes(index).isStage1Gpf(io.csr.hgatp.mode) && !vsStagePf 891 state(i) := Mux(entries(i).req_info.s2xlate === allStage && !(vsStagePf || gStagePf), 892 state_last_hptw_req, 893 Mux(bitmap_enable, state_bitmap_check, state_mem_out)) 894 mem_resp_hit(i) := true.B 895 entries(i).ppn := Mux(ptes(index).n === 0.U, ptes(index).getPPN(), Cat(ptes(index).getPPN()(ptePPNLen - 1, pteNapotBits), entries(i).req_info.vpn(pteNapotBits - 1, 0))) // for last stage 2 translation 896 // af will be judged in L2 TLB `contiguous_pte_to_merge_ptwResp` 897 entries(i).hptw_resp.gpf := Mux(entries(i).req_info.s2xlate === allStage, gStagePf, false.B) 898 } 899 } 900 } 901 902 if (HasBitmapCheck) { 903 for (i <- 0 until l2tlbParams.llptwsize) { 904 way_info.get(i) := DataHoldBypass(io.l0_way_info.get, mem_resp_hit(i)) 905 } 906 } 907 908 when (hyper_arb1.io.out.fire) { 909 for (i <- state.indices) { 910 when (state(i) === state_hptw_req && entries(i).ppn === hyper_arb1.io.out.bits.ppn && entries(i).req_info.s2xlate === allStage && hyper_arb1.io.chosen === i.U) { 911 state(i) := state_hptw_resp 912 entries(i).wait_id := hyper_arb1.io.chosen 913 } 914 } 915 } 916 917 when (hyper_arb2.io.out.fire) { 918 for (i <- state.indices) { 919 when (state(i) === state_last_hptw_req && entries(i).ppn === hyper_arb2.io.out.bits.ppn && entries(i).req_info.s2xlate === allStage && hyper_arb2.io.chosen === i.U) { 920 state(i) := state_last_hptw_resp 921 entries(i).wait_id := hyper_arb2.io.chosen 922 } 923 } 924 } 925 926 if (HasBitmapCheck) { 927 when (bitmap_arb.get.io.out.fire) { 928 for (i <- state.indices) { 929 when (is_bitmap_req(i) && bitmap_arb.get.io.out.bits.bmppn === entries(i).ppn(ppnLen - 1, 0)) { 930 state(i) := state_bitmap_resp 931 entries(i).wait_id := bitmap_arb.get.io.chosen 932 } 933 } 934 } 935 936 when (io.bitmap.get.resp.fire) { 937 for (i <- state.indices) { 938 when (is_bitmap_resp(i) && io.bitmap.get.resp.bits.id === entries(i).wait_id) { 939 entries(i).cfs := io.bitmap.get.resp.bits.cfs 940 entries(i).cf := io.bitmap.get.resp.bits.cf 941 state(i) := state_mem_out 942 } 943 } 944 } 945 } 946 947 when (io.hptw.resp.fire) { 948 for (i <- state.indices) { 949 when (state(i) === state_hptw_resp && io.hptw.resp.bits.id === entries(i).wait_id && io.hptw.resp.bits.h_resp.entry.tag === entries(i).ppn) { 950 val check_g_perm_fail = !io.hptw.resp.bits.h_resp.gaf && (!io.hptw.resp.bits.h_resp.entry.perm.get.r && !(io.csr.priv.mxr && io.hptw.resp.bits.h_resp.entry.perm.get.x)) 951 when (check_g_perm_fail || io.hptw.resp.bits.h_resp.gaf || io.hptw.resp.bits.h_resp.gpf) { 952 state(i) := state_mem_out 953 entries(i).hptw_resp := io.hptw.resp.bits.h_resp 954 entries(i).hptw_resp.gpf := io.hptw.resp.bits.h_resp.gpf || check_g_perm_fail 955 entries(i).first_s2xlate_fault := io.hptw.resp.bits.h_resp.gaf || io.hptw.resp.bits.h_resp.gpf 956 }.otherwise{ // change the entry that is waiting hptw resp 957 val need_to_waiting_vec = state.indices.map(i => state(i) === state_mem_waiting && dup(entries(i).req_info.vpn, entries(io.hptw.resp.bits.id).req_info.vpn)) 958 val waiting_index = ParallelMux(need_to_waiting_vec zip entries.map(_.wait_id)) 959 state(i) := Mux(Cat(need_to_waiting_vec).orR, state_mem_waiting, state_addr_check) 960 entries(i).hptw_resp := io.hptw.resp.bits.h_resp 961 entries(i).wait_id := Mux(Cat(need_to_waiting_vec).orR, waiting_index, entries(i).wait_id) 962 //To do: change the entry that is having the same hptw req 963 } 964 } 965 when (state(i) === state_last_hptw_resp && io.hptw.resp.bits.id === entries(i).wait_id && io.hptw.resp.bits.h_resp.entry.tag === entries(i).ppn) { 966 state(i) := state_mem_out 967 entries(i).hptw_resp := io.hptw.resp.bits.h_resp 968 //To do: change the entry that is having the same hptw req 969 } 970 } 971 } 972 when (io.out.fire) { 973 assert(state(mem_ptr) === state_mem_out) 974 state(mem_ptr) := state_idle 975 } 976 mem_resp_hit.map(a => when (a) { a := false.B } ) 977 978 when (io.cache.fire) { 979 state(cache_ptr) := state_idle 980 } 981 XSError(io.out.fire && io.cache.fire && (mem_ptr === cache_ptr), "mem resp and cache fire at the same time at same entry") 982 983 when (flush) { 984 state.map(_ := state_idle) 985 } 986 987 io.in.ready := !full 988 989 io.out.valid := ParallelOR(is_having).asBool 990 io.out.bits.req_info := entries(mem_ptr).req_info 991 io.out.bits.id := mem_ptr 992 if (HasBitmapCheck) { 993 io.out.bits.af := Mux(bitmap_enable, entries(mem_ptr).af || entries(mem_ptr).cf, entries(mem_ptr).af) 994 io.out.bits.bitmapCheck.get.jmp_bitmap_check := entries(mem_ptr).jmp_bitmap_check 995 io.out.bits.bitmapCheck.get.ptes := entries(mem_ptr).ptes 996 io.out.bits.bitmapCheck.get.cfs := entries(mem_ptr).cfs 997 } else { 998 io.out.bits.af := entries(mem_ptr).af 999 } 1000 1001 io.out.bits.h_resp := entries(mem_ptr).hptw_resp 1002 io.out.bits.first_s2xlate_fault := entries(mem_ptr).first_s2xlate_fault 1003 1004 val hptw_req_arb = Module(new Arbiter(new Bundle{ 1005 val source = UInt(bSourceWidth.W) 1006 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 1007 val ppn = UInt(ptePPNLen.W) 1008 } , 2)) 1009 // first stage 2 translation 1010 hptw_req_arb.io.in(0).valid := hyper_arb1.io.out.valid 1011 hptw_req_arb.io.in(0).bits.source := hyper_arb1.io.out.bits.req_info.source 1012 hptw_req_arb.io.in(0).bits.ppn := hyper_arb1.io.out.bits.ppn 1013 hptw_req_arb.io.in(0).bits.id := hyper_arb1.io.chosen 1014 hyper_arb1.io.out.ready := hptw_req_arb.io.in(0).ready 1015 // last stage 2 translation 1016 hptw_req_arb.io.in(1).valid := hyper_arb2.io.out.valid 1017 hptw_req_arb.io.in(1).bits.source := hyper_arb2.io.out.bits.req_info.source 1018 hptw_req_arb.io.in(1).bits.ppn := hyper_arb2.io.out.bits.ppn 1019 hptw_req_arb.io.in(1).bits.id := hyper_arb2.io.chosen 1020 hyper_arb2.io.out.ready := hptw_req_arb.io.in(1).ready 1021 hptw_req_arb.io.out.ready := io.hptw.req.ready 1022 io.hptw.req.valid := hptw_req_arb.io.out.fire && !flush 1023 io.hptw.req.bits.gvpn := hptw_req_arb.io.out.bits.ppn 1024 io.hptw.req.bits.id := hptw_req_arb.io.out.bits.id 1025 io.hptw.req.bits.source := hptw_req_arb.io.out.bits.source 1026 1027 io.mem.req.valid := mem_arb.io.out.valid && !flush 1028 val mem_paddr = MakeAddr(mem_arb.io.out.bits.ppn, getVpnn(mem_arb.io.out.bits.req_info.vpn, 0)) 1029 val mem_hpaddr = MakeAddr(mem_arb.io.out.bits.hptw_resp.genPPNS2(get_pn(mem_paddr)), getVpnn(mem_arb.io.out.bits.req_info.vpn, 0)) 1030 io.mem.req.bits.addr := Mux(mem_arb.io.out.bits.req_info.s2xlate === allStage, mem_hpaddr, mem_paddr) 1031 io.mem.req.bits.id := mem_arb.io.chosen 1032 io.mem.req.bits.hptw_bypassed := false.B 1033 mem_arb.io.out.ready := io.mem.req.ready 1034 val mem_refill_id = RegNext(io.mem.resp.bits.id(log2Up(l2tlbParams.llptwsize)-1, 0)) 1035 io.mem.refill := entries(mem_refill_id).req_info 1036 io.mem.refill.s2xlate := entries(mem_refill_id).req_info.s2xlate 1037 io.mem.buffer_it := mem_resp_hit 1038 io.mem.enq_ptr := enq_ptr 1039 1040 io.cache.valid := Cat(is_cache).orR 1041 io.cache.bits := ParallelMux(is_cache, entries.map(_.req_info)) 1042 1043 val has_bitmap_resp = ParallelOR(is_bitmap_resp).asBool 1044 if (HasBitmapCheck) { 1045 io.bitmap.get.req.valid := bitmap_arb.get.io.out.valid && !flush 1046 io.bitmap.get.req.bits.bmppn := bitmap_arb.get.io.out.bits.bmppn 1047 io.bitmap.get.req.bits.id := bitmap_arb.get.io.chosen 1048 io.bitmap.get.req.bits.vpn := bitmap_arb.get.io.out.bits.vpn 1049 io.bitmap.get.req.bits.level := 0.U 1050 io.bitmap.get.req.bits.way_info := bitmap_arb.get.io.out.bits.way_info 1051 io.bitmap.get.req.bits.hptw_bypassed := bitmap_arb.get.io.out.bits.hptw_bypassed 1052 bitmap_arb.get.io.out.ready := io.bitmap.get.req.ready 1053 io.bitmap.get.resp.ready := has_bitmap_resp 1054 } 1055 1056 XSPerfAccumulate("llptw_in_count", io.in.fire) 1057 XSPerfAccumulate("llptw_in_block", io.in.valid && !io.in.ready) 1058 for (i <- 0 until 7) { 1059 XSPerfAccumulate(s"enq_state${i}", io.in.fire && enq_state === i.U) 1060 } 1061 for (i <- 0 until (l2tlbParams.llptwsize + 1)) { 1062 XSPerfAccumulate(s"util${i}", PopCount(is_emptys.map(!_)) === i.U) 1063 XSPerfAccumulate(s"mem_util${i}", PopCount(is_mems) === i.U) 1064 XSPerfAccumulate(s"waiting_util${i}", PopCount(is_waiting) === i.U) 1065 } 1066 XSPerfAccumulate("mem_count", io.mem.req.fire) 1067 XSPerfAccumulate("mem_cycle", PopCount(is_waiting) =/= 0.U) 1068 XSPerfAccumulate("blocked_in", io.in.valid && !io.in.ready) 1069 1070 val perfEvents = Seq( 1071 ("tlbllptw_incount ", io.in.fire ), 1072 ("tlbllptw_inblock ", io.in.valid && !io.in.ready), 1073 ("tlbllptw_memcount ", io.mem.req.fire ), 1074 ("tlbllptw_memcycle ", PopCount(is_waiting) ), 1075 ) 1076 generatePerfEvent() 1077} 1078 1079/*========================= HPTW ==============================*/ 1080 1081/** HPTW : Hypervisor Page Table Walker 1082 * the page walker take the virtual machine's page walk. 1083 * guest physical address translation, guest physical address -> host physical address 1084 **/ 1085class HPTWIO()(implicit p: Parameters) extends MMUIOBaseBundle with HasPtwConst { 1086 val req = Flipped(DecoupledIO(new Bundle { 1087 val source = UInt(bSourceWidth.W) 1088 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 1089 val gvpn = UInt(gvpnLen.W) 1090 val ppn = UInt(ppnLen.W) 1091 val l3Hit = if (EnableSv48) Some(new Bool()) else None 1092 val l2Hit = Bool() 1093 val l1Hit = Bool() 1094 val bypassed = Bool() // if bypass, don't refill 1095 val bitmapCheck = Option.when(HasBitmapCheck)(new Bundle { 1096 val jmp_bitmap_check = Bool() // find pte in l0 or sp, but need bitmap check 1097 val pte = UInt(XLEN.W) // Page Table Entry 1098 val ptes = Vec(tlbcontiguous, UInt(XLEN.W)) // Page Table Entry Vector 1099 val cfs = Vec(tlbcontiguous, Bool()) // Bitmap Check Failed Vector 1100 val hitway = UInt(l2tlbParams.l0nWays.W) 1101 val fromSP = Bool() 1102 val SPlevel = UInt(log2Up(Level).W) 1103 }) 1104 })) 1105 val resp = DecoupledIO(new Bundle { 1106 val source = UInt(bSourceWidth.W) 1107 val resp = Output(new HptwResp()) 1108 val id = Output(UInt(bMemID.W)) 1109 }) 1110 1111 val mem = new Bundle { 1112 val req = DecoupledIO(new L2TlbMemReqBundle()) 1113 val resp = Flipped(ValidIO(UInt(XLEN.W))) 1114 val mask = Input(Bool()) 1115 } 1116 val refill = Output(new Bundle { 1117 val req_info = new L2TlbInnerBundle() 1118 val level = UInt(log2Up(Level + 1).W) 1119 }) 1120 val pmp = new Bundle { 1121 val req = ValidIO(new PMPReqBundle()) 1122 val resp = Flipped(new PMPRespBundle()) 1123 } 1124 val bitmap = Option.when(HasBitmapCheck)(new Bundle { 1125 val req = DecoupledIO(new bitmapReqBundle()) 1126 val resp = Flipped(DecoupledIO(new bitmapRespBundle())) 1127 }) 1128 1129 val l0_way_info = Option.when(HasBitmapCheck)(Input(UInt(l2tlbParams.l0nWays.W))) 1130} 1131 1132class HPTW()(implicit p: Parameters) extends XSModule with HasPtwConst { 1133 val io = IO(new HPTWIO) 1134 val hgatp = io.csr.hgatp 1135 val mpbmte = io.csr.mPBMTE 1136 val sfence = io.sfence 1137 val flush = sfence.valid || hgatp.changed || io.csr.satp.changed || io.csr.vsatp.changed 1138 val mode = hgatp.mode 1139 1140 // mbmc:bitmap csr 1141 val mbmc = io.csr.mbmc 1142 val bitmap_enable = (if (HasBitmapCheck) true.B else false.B) && mbmc.BME === 1.U && mbmc.CMODE === 0.U 1143 1144 val level = RegInit(3.U(log2Up(Level + 1).W)) 1145 val af_level = RegInit(3.U(log2Up(Level + 1).W)) // access fault return this level 1146 val gpaddr = Reg(UInt(GPAddrBits.W)) 1147 val req_ppn = Reg(UInt(ppnLen.W)) 1148 val vpn = gpaddr(GPAddrBits-1, offLen) 1149 val levelNext = level - 1.U 1150 val l3Hit = Reg(Bool()) 1151 val l2Hit = Reg(Bool()) 1152 val l1Hit = Reg(Bool()) 1153 val bypassed = Reg(Bool()) 1154// val pte = io.mem.resp.bits.MergeRespToPte() 1155 val jmp_bitmap_check = if (HasBitmapCheck) RegEnable(io.req.bits.bitmapCheck.get.jmp_bitmap_check, io.req.fire) else false.B 1156 val fromSP = if (HasBitmapCheck) RegEnable(io.req.bits.bitmapCheck.get.fromSP, io.req.fire) else false.B 1157 val cache_pte = Option.when(HasBitmapCheck)(RegEnable(Mux(io.req.bits.bitmapCheck.get.fromSP, io.req.bits.bitmapCheck.get.pte.asTypeOf(new PteBundle().cloneType), io.req.bits.bitmapCheck.get.ptes(io.req.bits.gvpn(sectortlbwidth - 1, 0)).asTypeOf(new PteBundle().cloneType)), io.req.fire)) 1158 val pte = if (HasBitmapCheck) Mux(jmp_bitmap_check, cache_pte.get, io.mem.resp.bits.asTypeOf(new PteBundle().cloneType)) else io.mem.resp.bits.asTypeOf(new PteBundle().cloneType) 1159 val ppn_l3 = Mux(l3Hit, req_ppn, pte.ppn) 1160 val ppn_l2 = Mux(l2Hit, req_ppn, pte.ppn) 1161 val ppn_l1 = Mux(l1Hit, req_ppn, pte.ppn) 1162 val ppn = Wire(UInt(PAddrBits.W)) 1163 val p_pte = MakeAddr(ppn, getVpnn(vpn, level)) 1164 val pg_base = Wire(UInt(PAddrBits.W)) 1165 val mem_addr = Wire(UInt(PAddrBits.W)) 1166 if (EnableSv48) { 1167 when (mode === Sv48) { 1168 ppn := Mux(af_level === 2.U, ppn_l3, Mux(af_level === 1.U, ppn_l2, ppn_l1)) // for l2, l1 and l3 1169 pg_base := MakeGPAddr(hgatp.ppn, getGVpnn(vpn, 3.U, mode = Sv48)) // for l3 1170 mem_addr := Mux(af_level === 3.U, pg_base, p_pte) 1171 } .otherwise { 1172 ppn := Mux(af_level === 1.U, ppn_l2, ppn_l1) //for l1 and l2 1173 pg_base := MakeGPAddr(hgatp.ppn, getGVpnn(vpn, 2.U, mode = Sv39)) 1174 mem_addr := Mux(af_level === 2.U, pg_base, p_pte) 1175 } 1176 } else { 1177 ppn := Mux(af_level === 1.U, ppn_l2, ppn_l1) //for l1 and l2 1178 pg_base := MakeGPAddr(hgatp.ppn, getGVpnn(vpn, 2.U, mode = Sv39)) 1179 mem_addr := Mux(af_level === 2.U, pg_base, p_pte) 1180 } 1181 1182 //s/w register 1183 val s_pmp_check = RegInit(true.B) 1184 val s_mem_req = RegInit(true.B) 1185 val w_mem_resp = RegInit(true.B) 1186 val idle = RegInit(true.B) 1187 val mem_addr_update = RegInit(false.B) 1188 val finish = WireInit(false.B) 1189 val s_bitmap_check = RegInit(true.B) 1190 val w_bitmap_resp = RegInit(true.B) 1191 val whether_need_bitmap_check = RegInit(false.B) 1192 val bitmap_checkfailed = RegInit(false.B) 1193 1194 val sent_to_pmp = !idle && (!s_pmp_check || mem_addr_update) && !finish 1195 val pageFault = pte.isGpf(level, mpbmte) || (!pte.isLeaf() && level === 0.U) 1196 val accessFault = RegEnable(io.pmp.resp.ld || io.pmp.resp.mmio, sent_to_pmp) 1197 1198 // use access fault when bitmap check failed 1199 val ppn_af = if (HasBitmapCheck) { 1200 Mux(bitmap_enable, pte.isAf() || bitmap_checkfailed, pte.isAf()) 1201 } else { 1202 pte.isAf() 1203 } 1204 val find_pte = pte.isLeaf() || ppn_af || pageFault 1205 1206 val resp_valid = !idle && mem_addr_update && ((w_mem_resp && find_pte) || (s_pmp_check && accessFault)) 1207 val id = Reg(UInt(log2Up(l2tlbParams.llptwsize).W)) 1208 val source = RegEnable(io.req.bits.source, io.req.fire) 1209 1210 io.req.ready := idle 1211 val resp = Wire(new HptwResp()) 1212 // accessFault > pageFault > ppn_af 1213 resp.apply( 1214 gpf = pageFault && !accessFault, 1215 gaf = accessFault || (ppn_af && !pageFault), 1216 level = Mux(accessFault, af_level, level), 1217 pte = pte, 1218 vpn = vpn, 1219 vmid = hgatp.vmid 1220 ) 1221 io.resp.valid := resp_valid 1222 io.resp.bits.id := id 1223 io.resp.bits.resp := resp 1224 io.resp.bits.source := source 1225 1226 io.pmp.req.valid := DontCare 1227 io.pmp.req.bits.addr := mem_addr 1228 io.pmp.req.bits.size := 3.U 1229 io.pmp.req.bits.cmd := TlbCmd.read 1230 1231 if (HasBitmapCheck) { 1232 val way_info = DataHoldBypass(io.l0_way_info.get, RegNext(io.mem.resp.fire, init=false.B)) 1233 val cache_hitway = RegEnable(io.req.bits.bitmapCheck.get.hitway, io.req.fire) 1234 val cache_level = RegEnable(io.req.bits.bitmapCheck.get.SPlevel, io.req.fire) 1235 io.bitmap.get.req.valid := !s_bitmap_check 1236 io.bitmap.get.req.bits.bmppn := pte.ppn 1237 io.bitmap.get.req.bits.id := HptwReqId.U(bMemID.W) 1238 io.bitmap.get.req.bits.vpn := vpn 1239 io.bitmap.get.req.bits.level := Mux(jmp_bitmap_check, Mux(fromSP,cache_level,0.U), level) 1240 io.bitmap.get.req.bits.way_info := Mux(jmp_bitmap_check, cache_hitway, way_info) 1241 io.bitmap.get.req.bits.hptw_bypassed := bypassed 1242 io.bitmap.get.resp.ready := !w_bitmap_resp 1243 } 1244 1245 io.mem.req.valid := !s_mem_req && !io.mem.mask && !accessFault && s_pmp_check 1246 io.mem.req.bits.addr := mem_addr 1247 io.mem.req.bits.id := HptwReqId.U(bMemID.W) 1248 io.mem.req.bits.hptw_bypassed := bypassed 1249 1250 io.refill.req_info.vpn := vpn 1251 io.refill.level := level 1252 io.refill.req_info.source := source 1253 io.refill.req_info.s2xlate := onlyStage2 1254 1255 when (idle){ 1256 if (HasBitmapCheck) { 1257 when (io.req.bits.bitmapCheck.get.jmp_bitmap_check && io.req.fire) { 1258 idle := false.B 1259 gpaddr := Cat(io.req.bits.gvpn, 0.U(offLen.W)) 1260 s_bitmap_check := false.B 1261 id := io.req.bits.id 1262 level := Mux(io.req.bits.bitmapCheck.get.fromSP, io.req.bits.bitmapCheck.get.SPlevel, 0.U) 1263 } 1264 } 1265 when (io.req.fire && (if (HasBitmapCheck) !io.req.bits.bitmapCheck.get.jmp_bitmap_check else true.B)) { 1266 bypassed := io.req.bits.bypassed 1267 idle := false.B 1268 gpaddr := Cat(io.req.bits.gvpn, 0.U(offLen.W)) 1269 accessFault := false.B 1270 s_pmp_check := false.B 1271 id := io.req.bits.id 1272 req_ppn := io.req.bits.ppn 1273 if (EnableSv48) { 1274 when (mode === Sv48) { 1275 level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, Mux(io.req.bits.l3Hit.get, 2.U, 3.U))) 1276 af_level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, Mux(io.req.bits.l3Hit.get, 2.U, 3.U))) 1277 l3Hit := io.req.bits.l3Hit.get 1278 } .otherwise { 1279 level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, 2.U)) 1280 af_level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, 2.U)) 1281 l3Hit := false.B 1282 } 1283 } else { 1284 level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, 2.U)) 1285 af_level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, 2.U)) 1286 l3Hit := false.B 1287 } 1288 l2Hit := io.req.bits.l2Hit 1289 l1Hit := io.req.bits.l1Hit 1290 } 1291 } 1292 1293 when(sent_to_pmp && !mem_addr_update){ 1294 s_mem_req := false.B 1295 s_pmp_check := true.B 1296 } 1297 1298 when(accessFault && !idle){ 1299 s_pmp_check := true.B 1300 s_mem_req := true.B 1301 w_mem_resp := true.B 1302 mem_addr_update := true.B 1303 if (HasBitmapCheck) { 1304 s_bitmap_check := true.B 1305 w_bitmap_resp := true.B 1306 whether_need_bitmap_check := false.B 1307 bitmap_checkfailed := false.B 1308 } 1309 } 1310 1311 when(io.mem.req.fire){ 1312 s_mem_req := true.B 1313 w_mem_resp := false.B 1314 } 1315 1316 when(io.mem.resp.fire && !w_mem_resp){ 1317 w_mem_resp := true.B 1318 af_level := af_level - 1.U 1319 if (HasBitmapCheck) { 1320 when (bitmap_enable) { 1321 whether_need_bitmap_check := true.B 1322 } .otherwise { 1323 mem_addr_update := true.B 1324 whether_need_bitmap_check := false.B 1325 } 1326 } else { 1327 mem_addr_update := true.B 1328 } 1329 } 1330 1331 if (HasBitmapCheck) { 1332 when (whether_need_bitmap_check) { 1333 when (bitmap_enable && pte.isLeaf()) { 1334 s_bitmap_check := false.B 1335 whether_need_bitmap_check := false.B 1336 } .otherwise { 1337 mem_addr_update := true.B 1338 whether_need_bitmap_check := false.B 1339 } 1340 } 1341 // bitmapcheck 1342 when (io.bitmap.get.req.fire) { 1343 s_bitmap_check := true.B 1344 w_bitmap_resp := false.B 1345 } 1346 when (io.bitmap.get.resp.fire) { 1347 w_bitmap_resp := true.B 1348 mem_addr_update := true.B 1349 bitmap_checkfailed := io.bitmap.get.resp.bits.cf 1350 } 1351 } 1352 1353 when(mem_addr_update){ 1354 when(!(find_pte || accessFault)){ 1355 level := levelNext 1356 s_mem_req := false.B 1357 mem_addr_update := false.B 1358 }.elsewhen(resp_valid){ 1359 when(io.resp.fire){ 1360 idle := true.B 1361 mem_addr_update := false.B 1362 accessFault := false.B 1363 } 1364 finish := true.B 1365 } 1366 } 1367 when (flush) { 1368 idle := true.B 1369 s_pmp_check := true.B 1370 s_mem_req := true.B 1371 w_mem_resp := true.B 1372 accessFault := false.B 1373 mem_addr_update := false.B 1374 if (HasBitmapCheck) { 1375 s_bitmap_check := true.B 1376 w_bitmap_resp := true.B 1377 whether_need_bitmap_check := false.B 1378 bitmap_checkfailed := false.B 1379 } 1380 } 1381} 1382