1/*************************************************************************************** 2* Copyright (c) 2021-2025 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* Copyright (c) 2024-2025 Institute of Information Engineering, Chinese Academy of Sciences 6* 7* XiangShan is licensed under Mulan PSL v2. 8* You can use this software according to the terms and conditions of the Mulan PSL v2. 9* You may obtain a copy of Mulan PSL v2 at: 10* http://license.coscl.org.cn/MulanPSL2 11* 12* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 13* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 14* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 15* 16* See the Mulan PSL v2 for more details. 17***************************************************************************************/ 18 19package xiangshan.cache.mmu 20 21import org.chipsalliance.cde.config.Parameters 22import chisel3._ 23import chisel3.util._ 24import xiangshan._ 25import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 26import utils._ 27import utility._ 28import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 29import freechips.rocketchip.tilelink._ 30import xiangshan.backend.fu.{PMPReqBundle, PMPRespBundle} 31 32/** Page Table Walk is divided into two parts 33 * One, PTW: page walk for pde, except for leaf entries, one by one 34 * Two, LLPTW: page walk for pte, only the leaf entries(4KB), in parallel 35 */ 36 37 38/** PTW : page table walker 39 * a finite state machine 40 * only take 1GB and 2MB page walks 41 * or in other words, except the last level(leaf) 42 **/ 43class PTWIO()(implicit p: Parameters) extends MMUIOBaseBundle with HasPtwConst { 44 val req = Flipped(DecoupledIO(new Bundle { 45 val req_info = new L2TlbInnerBundle() 46 val l3Hit = if (EnableSv48) Some(new Bool()) else None 47 val l2Hit = Bool() 48 val ppn = UInt(ptePPNLen.W) 49 val stage1Hit = Bool() 50 val stage1 = new PtwMergeResp 51 val bitmapCheck = Option.when(HasBitmapCheck)(new Bundle { 52 val jmp_bitmap_check = Bool() // super page in PtwCache ptw hit, but need bitmap check 53 val pte = UInt(XLEN.W) // Page Table Entry 54 val cfs = Vec(tlbcontiguous, Bool()) // Bitmap Check Failed Vector 55 val SPlevel = UInt(log2Up(Level).W) 56 }) 57 })) 58 val resp = DecoupledIO(new Bundle { 59 val source = UInt(bSourceWidth.W) 60 val s2xlate = UInt(2.W) 61 val resp = new PtwMergeResp 62 val h_resp = new HptwResp 63 }) 64 65 val llptw = DecoupledIO(new LLPTWInBundle()) 66 // NOTE: llptw change from "connect to llptw" to "connect to page cache" 67 // to avoid corner case that caused duplicate entries 68 69 val hptw = new Bundle { 70 val req = DecoupledIO(new Bundle { 71 val source = UInt(bSourceWidth.W) 72 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 73 val gvpn = UInt(ptePPNLen.W) 74 }) 75 val resp = Flipped(Valid(new Bundle { 76 val h_resp = Output(new HptwResp) 77 })) 78 } 79 val mem = new Bundle { 80 val req = DecoupledIO(new L2TlbMemReqBundle()) 81 val resp = Flipped(ValidIO(UInt(XLEN.W))) 82 val mask = Input(Bool()) 83 } 84 val pmp = new Bundle { 85 val req = ValidIO(new PMPReqBundle()) 86 val resp = Flipped(new PMPRespBundle()) 87 } 88 89 val refill = Output(new Bundle { 90 val req_info = new L2TlbInnerBundle() 91 val level = UInt(log2Up(Level + 1).W) 92 }) 93 val bitmap = Option.when(HasBitmapCheck)(new Bundle { 94 val req = DecoupledIO(new bitmapReqBundle()) 95 val resp = Flipped(DecoupledIO(new bitmapRespBundle())) 96 }) 97} 98 99class PTW()(implicit p: Parameters) extends XSModule with HasPtwConst with HasPerfEvents { 100 val io = IO(new PTWIO) 101 val sfence = io.sfence 102 val mem = io.mem 103 val req_s2xlate = Reg(UInt(2.W)) 104 val enableS2xlate = req_s2xlate =/= noS2xlate 105 val onlyS1xlate = req_s2xlate === onlyStage1 106 val onlyS2xlate = req_s2xlate === onlyStage2 107 108 // mbmc:bitmap csr 109 val mbmc = io.csr.mbmc 110 val bitmap_enable = (if (HasBitmapCheck) true.B else false.B) && mbmc.BME === 1.U && mbmc.CMODE === 0.U 111 112 val satp = Wire(new TlbSatpBundle()) 113 when (io.req.fire) { 114 satp := Mux(io.req.bits.req_info.s2xlate =/= noS2xlate, io.csr.vsatp, io.csr.satp) 115 } .otherwise { 116 satp := Mux(enableS2xlate, io.csr.vsatp, io.csr.satp) 117 } 118 val s1Pbmte = Mux(req_s2xlate =/= noS2xlate, io.csr.hPBMTE, io.csr.mPBMTE) 119 120 val mode = satp.mode 121 val hgatp = io.csr.hgatp 122 val flush = io.sfence.valid || io.csr.satp.changed || io.csr.vsatp.changed || io.csr.hgatp.changed 123 val s2xlate = enableS2xlate && !onlyS1xlate 124 val level = RegInit(3.U(log2Up(Level + 1).W)) 125 val af_level = RegInit(3.U(log2Up(Level + 1).W)) // access fault return this level 126 val gpf_level = RegInit(3.U(log2Up(Level + 1).W)) 127 val ppn = Reg(UInt(ptePPNLen.W)) 128 val vpn = Reg(UInt(vpnLen.W)) // vpn or gvpn(onlyS2xlate) 129 val levelNext = level - 1.U 130 val l3Hit = Reg(Bool()) 131 val l2Hit = Reg(Bool()) 132 val jmp_bitmap_check_w = if (HasBitmapCheck) { io.req.bits.bitmapCheck.get.jmp_bitmap_check && io.req.bits.req_info.s2xlate =/= onlyStage2 } else { false.B } 133 val jmp_bitmap_check_r = if (HasBitmapCheck) { RegEnable(jmp_bitmap_check_w, io.req.fire) } else { false.B } 134 val cache_pte = Option.when(HasBitmapCheck)(RegEnable(io.req.bits.bitmapCheck.get.pte.asTypeOf(new PteBundle().cloneType), io.req.fire)) 135 val pte = if (HasBitmapCheck) { Mux(jmp_bitmap_check_r, cache_pte.get, io.mem.resp.bits.asTypeOf(new PteBundle().cloneType)) } else { mem.resp.bits.asTypeOf(new PteBundle()) } 136 137 // s/w register 138 val s_pmp_check = RegInit(true.B) 139 val s_mem_req = RegInit(true.B) 140 val s_llptw_req = RegInit(true.B) 141 val w_mem_resp = RegInit(true.B) 142 val s_hptw_req = RegInit(true.B) 143 val w_hptw_resp = RegInit(true.B) 144 val s_last_hptw_req = RegInit(true.B) 145 val w_last_hptw_resp = RegInit(true.B) 146 // for updating "level" 147 val mem_addr_update = RegInit(false.B) 148 149 val s_bitmap_check = RegInit(true.B) 150 val w_bitmap_resp = RegInit(true.B) 151 val whether_need_bitmap_check = RegInit(false.B) 152 val bitmap_checkfailed = RegInit(false.B) 153 154 val idle = RegInit(true.B) 155 val finish = WireInit(false.B) 156 val sent_to_pmp = idle === false.B && (s_pmp_check === false.B || mem_addr_update) && !finish 157 158 val pageFault = pte.isPf(level, s1Pbmte) 159 val accessFault = RegEnable(io.pmp.resp.ld || io.pmp.resp.mmio, false.B, sent_to_pmp) 160 161 val hptw_pageFault = RegInit(false.B) 162 val hptw_accessFault = RegInit(false.B) 163 val need_last_s2xlate = RegInit(false.B) 164 val stage1Hit = RegEnable(io.req.bits.stage1Hit, io.req.fire) 165 val stage1 = RegEnable(io.req.bits.stage1, io.req.fire) 166 val hptw_resp_stage2 = Reg(Bool()) 167 168 // use accessfault repersent bitmap check failed 169 val pte_isAf = Mux(bitmap_enable, pte.isAf() || bitmap_checkfailed, pte.isAf()) 170 val ppn_af = if (HasBitmapCheck) { 171 Mux(enableS2xlate, Mux(onlyS1xlate, pte_isAf, false.B), pte_isAf) // In two-stage address translation, stage 1 ppn is a vpn for host, so don't need to check ppn_high 172 } else { 173 Mux(enableS2xlate, Mux(onlyS1xlate, pte.isAf(), false.B), pte.isAf()) // In two-stage address translation, stage 1 ppn is a vpn for host, so don't need to check ppn_high 174 } 175 176 val find_pte = pte.isLeaf() || ppn_af || pageFault 177 val to_find_pte = level === 1.U && find_pte === false.B 178 val source = RegEnable(io.req.bits.req_info.source, io.req.fire) 179 180 val l3addr = Wire(UInt(ptePaddrLen.W)) 181 val l2addr = Wire(UInt(ptePaddrLen.W)) 182 val l1addr = Wire(UInt(ptePaddrLen.W)) 183 val hptw_addr = Wire(UInt(ptePaddrLen.W)) 184 val mem_addr = Wire(UInt(PAddrBits.W)) 185 186 l3addr := MakeAddr(satp.ppn, getVpnn(vpn, 3)) 187 if (EnableSv48) { 188 when (mode === Sv48) { 189 l2addr := MakeAddr(Mux(l3Hit, ppn, pte.getPPN()), getVpnn(vpn, 2)) 190 } .otherwise { 191 l2addr := MakeAddr(satp.ppn, getVpnn(vpn, 2)) 192 } 193 } else { 194 l2addr := MakeAddr(satp.ppn, getVpnn(vpn, 2)) 195 } 196 l1addr := MakeAddr(Mux(l2Hit, ppn, pte.getPPN()), getVpnn(vpn, 1)) 197 hptw_addr := Mux(af_level === 3.U, l3addr, Mux(af_level === 2.U, l2addr, l1addr)) 198 mem_addr := hptw_addr(PAddrBits - 1, 0) 199 200 val hptw_resp = Reg(new HptwResp) 201 202 val update_full_gvpn_mem_resp = RegInit(false.B) 203 val full_gvpn_reg = Reg(UInt(ptePPNLen.W)) 204 val full_gvpn_wire = pte.getPPN() 205 val full_gvpn = Mux(update_full_gvpn_mem_resp, full_gvpn_wire, full_gvpn_reg) 206 207 val gpaddr = MuxCase(hptw_addr, Seq( 208 (stage1Hit || onlyS2xlate) -> Cat(full_gvpn, 0.U(offLen.W)), 209 !s_last_hptw_req -> Cat(MuxLookup(level, pte.getPPN())(Seq( 210 3.U -> Cat(pte.getPPN()(ptePPNLen - 1, vpnnLen * 3), vpn(vpnnLen * 3 - 1, 0)), 211 2.U -> Cat(pte.getPPN()(ptePPNLen - 1, vpnnLen * 2), vpn(vpnnLen * 2 - 1, 0)), 212 1.U -> Cat(pte.getPPN()(ptePPNLen - 1, vpnnLen), vpn(vpnnLen - 1, 0) 213 ))), 214 0.U(offLen.W)) 215 )) 216 val gvpn_gpf = 217 !(hptw_pageFault || hptw_accessFault ) && 218 Mux( 219 s2xlate && io.csr.hgatp.mode === Sv39x4, 220 full_gvpn(ptePPNLen - 1, GPAddrBitsSv39x4 - offLen) =/= 0.U, 221 Mux( 222 s2xlate && io.csr.hgatp.mode === Sv48x4, 223 full_gvpn(ptePPNLen - 1, GPAddrBitsSv48x4 - offLen) =/= 0.U, 224 false.B 225 ) 226 ) 227 228 val guestFault = hptw_pageFault || hptw_accessFault || gvpn_gpf 229 val hpaddr = Cat(hptw_resp.genPPNS2(get_pn(gpaddr)), get_off(gpaddr)) 230 val fake_h_resp = WireInit(0.U.asTypeOf(new HptwResp)) 231 fake_h_resp.entry.tag := get_pn(gpaddr) 232 fake_h_resp.entry.vmid.map(_ := io.csr.hgatp.vmid) 233 fake_h_resp.gpf := true.B 234 235 val pte_valid = RegInit(false.B) // avoid l1tlb pf from stage1 when gpf happens in the first s2xlate in PTW 236 val fake_pte = WireInit(0.U.asTypeOf(new PteBundle())) 237 fake_pte.perm.v := false.B // tell L1TLB this is fake pte 238 fake_pte.ppn := ppn(ppnLen - 1, 0) 239 fake_pte.ppn_high := ppn(ptePPNLen - 1, ppnLen) 240 241 io.req.ready := idle 242 val ptw_resp = Wire(new PtwMergeResp) 243 ptw_resp.apply(Mux(pte_valid, pageFault && !accessFault, false.B), accessFault || (ppn_af && !(pte_valid && (pageFault || guestFault))), Mux(accessFault, af_level, Mux(guestFault, gpf_level, level)), Mux(pte_valid, pte, fake_pte), vpn, satp.asid, hgatp.vmid, vpn(sectortlbwidth - 1, 0), not_super = false, not_merge = false, bitmap_checkfailed.asBool) 244 245 val normal_resp = idle === false.B && mem_addr_update && !need_last_s2xlate && (guestFault || (w_mem_resp && find_pte) || (s_pmp_check && accessFault) || onlyS2xlate ) 246 val stageHit_resp = idle === false.B && hptw_resp_stage2 247 io.resp.valid := Mux(stage1Hit, stageHit_resp, normal_resp) 248 io.resp.bits.source := source 249 io.resp.bits.resp := Mux(stage1Hit || (l3Hit || l2Hit) && guestFault && !pte_valid, stage1, ptw_resp) 250 io.resp.bits.h_resp := Mux(gvpn_gpf, fake_h_resp, hptw_resp) 251 io.resp.bits.s2xlate := req_s2xlate 252 253 io.llptw.valid := s_llptw_req === false.B && to_find_pte && !accessFault && !guestFault 254 io.llptw.bits.req_info.source := source 255 io.llptw.bits.req_info.vpn := vpn 256 io.llptw.bits.req_info.s2xlate := req_s2xlate 257 io.llptw.bits.ppn := DontCare 258 if (HasBitmapCheck) { 259 io.llptw.bits.bitmapCheck.get.jmp_bitmap_check := DontCare 260 io.llptw.bits.bitmapCheck.get.ptes := DontCare 261 io.llptw.bits.bitmapCheck.get.cfs := DontCare 262 io.llptw.bits.bitmapCheck.get.hitway := DontCare 263 } 264 265 io.pmp.req.valid := DontCare // samecycle, do not use valid 266 io.pmp.req.bits.addr := Mux(s2xlate, hpaddr, mem_addr) 267 io.pmp.req.bits.size := 3.U // TODO: fix it 268 io.pmp.req.bits.cmd := TlbCmd.read 269 270 if (HasBitmapCheck) { 271 val cache_level = RegEnable(io.req.bits.bitmapCheck.get.SPlevel, io.req.fire) 272 io.bitmap.get.req.valid := !s_bitmap_check 273 io.bitmap.get.req.bits.bmppn := pte.ppn 274 io.bitmap.get.req.bits.id := FsmReqID.U(bMemID.W) 275 io.bitmap.get.req.bits.vpn := vpn 276 io.bitmap.get.req.bits.level := Mux(jmp_bitmap_check_r, cache_level, level) 277 io.bitmap.get.req.bits.way_info := DontCare 278 io.bitmap.get.req.bits.hptw_bypassed := false.B 279 io.bitmap.get.resp.ready := !w_bitmap_resp 280 } 281 mem.req.valid := s_mem_req === false.B && !mem.mask && !accessFault && s_pmp_check 282 mem.req.bits.addr := Mux(s2xlate, hpaddr, mem_addr) 283 mem.req.bits.id := FsmReqID.U(bMemID.W) 284 mem.req.bits.hptw_bypassed := false.B 285 286 io.refill.req_info.s2xlate := req_s2xlate 287 io.refill.req_info.vpn := vpn 288 io.refill.level := level 289 io.refill.req_info.source := source 290 291 io.hptw.req.valid := !s_hptw_req || !s_last_hptw_req 292 io.hptw.req.bits.id := FsmReqID.U(bMemID.W) 293 io.hptw.req.bits.gvpn := get_pn(gpaddr) 294 io.hptw.req.bits.source := source 295 296 if (HasBitmapCheck) { 297 when (io.req.fire && jmp_bitmap_check_w) { 298 idle := false.B 299 req_s2xlate := io.req.bits.req_info.s2xlate 300 vpn := io.req.bits.req_info.vpn 301 s_bitmap_check := false.B 302 need_last_s2xlate := false.B 303 hptw_pageFault := false.B 304 hptw_accessFault := false.B 305 level := io.req.bits.bitmapCheck.get.SPlevel 306 pte_valid := true.B 307 accessFault := false.B 308 } 309 } 310 311 when (io.req.fire && io.req.bits.stage1Hit && (if (HasBitmapCheck) !jmp_bitmap_check_w else true.B)) { 312 idle := false.B 313 req_s2xlate := io.req.bits.req_info.s2xlate 314 s_last_hptw_req := false.B 315 hptw_resp_stage2 := false.B 316 need_last_s2xlate := false.B 317 hptw_pageFault := false.B 318 hptw_accessFault := false.B 319 full_gvpn_reg := io.req.bits.stage1.genPPN() 320 } 321 322 when (io.resp.fire && stage1Hit){ 323 idle := true.B 324 } 325 326 when (io.req.fire && !io.req.bits.stage1Hit && (if (HasBitmapCheck) !jmp_bitmap_check_w else true.B)) { 327 val req = io.req.bits 328 val gvpn_wire = Wire(UInt(ptePPNLen.W)) 329 if (EnableSv48) { 330 when (mode === Sv48) { 331 level := Mux(req.l2Hit, 1.U, Mux(req.l3Hit.get, 2.U, 3.U)) 332 af_level := Mux(req.l2Hit, 1.U, Mux(req.l3Hit.get, 2.U, 3.U)) 333 gpf_level := Mux(req.l2Hit, 2.U, Mux(req.l3Hit.get, 3.U, 0.U)) 334 ppn := Mux(req.l2Hit || req.l3Hit.get, io.req.bits.ppn, satp.ppn) 335 l3Hit := req.l3Hit.get 336 gvpn_wire := Mux(req.l2Hit || req.l3Hit.get, io.req.bits.ppn, satp.ppn) 337 } .otherwise { 338 level := Mux(req.l2Hit, 1.U, 2.U) 339 af_level := Mux(req.l2Hit, 1.U, 2.U) 340 gpf_level := 0.U 341 ppn := Mux(req.l2Hit, io.req.bits.ppn, satp.ppn) 342 l3Hit := false.B 343 gvpn_wire := Mux(req.l2Hit, io.req.bits.ppn, satp.ppn) 344 } 345 } else { 346 level := Mux(req.l2Hit, 1.U, 2.U) 347 af_level := Mux(req.l2Hit, 1.U, 2.U) 348 gpf_level := 0.U 349 ppn := Mux(req.l2Hit, io.req.bits.ppn, satp.ppn) 350 l3Hit := false.B 351 gvpn_wire := Mux(req.l2Hit, io.req.bits.ppn, satp.ppn) 352 } 353 vpn := io.req.bits.req_info.vpn 354 l2Hit := req.l2Hit 355 accessFault := false.B 356 idle := false.B 357 hptw_pageFault := false.B 358 hptw_accessFault := false.B 359 pte_valid := false.B 360 req_s2xlate := io.req.bits.req_info.s2xlate 361 when(io.req.bits.req_info.s2xlate === onlyStage2){ 362 full_gvpn_reg := io.req.bits.req_info.vpn 363 val onlys2_gpaddr = Cat(io.req.bits.req_info.vpn, 0.U(offLen.W)) // is 50 bits, don't need to check high bits when sv48x4 is enabled 364 val check_gpa_high_fail = Mux(io.req.bits.req_info.s2xlate === onlyStage2 && io.csr.hgatp.mode === Sv39x4, onlys2_gpaddr(onlys2_gpaddr.getWidth - 1, GPAddrBitsSv39x4) =/= 0.U, false.B) 365 need_last_s2xlate := false.B 366 when(check_gpa_high_fail){ 367 mem_addr_update := true.B 368 }.otherwise{ 369 s_last_hptw_req := false.B 370 } 371 }.elsewhen(io.req.bits.req_info.s2xlate === allStage){ 372 full_gvpn_reg := 0.U 373 val allstage_gpaddr = Cat(gvpn_wire, 0.U(offLen.W)) 374 val check_gpa_high_fail = Mux(io.csr.hgatp.mode === Sv39x4, allstage_gpaddr(allstage_gpaddr.getWidth - 1, GPAddrBitsSv39x4) =/= 0.U, Mux(io.csr.hgatp.mode === Sv48x4, allstage_gpaddr(allstage_gpaddr.getWidth - 1, GPAddrBitsSv48x4) =/= 0.U, false.B)) 375 when(check_gpa_high_fail){ 376 mem_addr_update := true.B 377 }.otherwise{ 378 need_last_s2xlate := true.B 379 s_hptw_req := false.B 380 } 381 }.otherwise { 382 full_gvpn_reg := 0.U 383 need_last_s2xlate := false.B 384 s_pmp_check := false.B 385 } 386 } 387 388 when(io.hptw.req.fire && s_hptw_req === false.B){ 389 s_hptw_req := true.B 390 w_hptw_resp := false.B 391 } 392 393 when(io.hptw.resp.fire && w_hptw_resp === false.B) { 394 w_hptw_resp := true.B 395 val g_perm_fail = !io.hptw.resp.bits.h_resp.gaf && (!io.hptw.resp.bits.h_resp.entry.perm.get.r && !(io.csr.priv.mxr && io.hptw.resp.bits.h_resp.entry.perm.get.x)) 396 hptw_pageFault := io.hptw.resp.bits.h_resp.gpf || g_perm_fail 397 hptw_accessFault := io.hptw.resp.bits.h_resp.gaf 398 hptw_resp := io.hptw.resp.bits.h_resp 399 hptw_resp.gpf := io.hptw.resp.bits.h_resp.gpf || g_perm_fail 400 when(!(g_perm_fail || io.hptw.resp.bits.h_resp.gpf || io.hptw.resp.bits.h_resp.gaf)) { 401 s_pmp_check := false.B 402 }.otherwise { 403 mem_addr_update := true.B 404 need_last_s2xlate := false.B 405 } 406 } 407 408 when(io.hptw.req.fire && s_last_hptw_req === false.B) { 409 w_last_hptw_resp := false.B 410 s_last_hptw_req := true.B 411 } 412 413 when (io.hptw.resp.fire && w_last_hptw_resp === false.B && stage1Hit){ 414 w_last_hptw_resp := true.B 415 hptw_resp_stage2 := true.B 416 hptw_resp := io.hptw.resp.bits.h_resp 417 } 418 419 when(io.hptw.resp.fire && w_last_hptw_resp === false.B && !stage1Hit){ 420 hptw_pageFault := io.hptw.resp.bits.h_resp.gpf 421 hptw_accessFault := io.hptw.resp.bits.h_resp.gaf 422 hptw_resp := io.hptw.resp.bits.h_resp 423 w_last_hptw_resp := true.B 424 mem_addr_update := true.B 425 } 426 427 when(sent_to_pmp && mem_addr_update === false.B){ 428 s_mem_req := false.B 429 s_pmp_check := true.B 430 } 431 432 when(accessFault && idle === false.B){ 433 s_pmp_check := true.B 434 s_mem_req := true.B 435 w_mem_resp := true.B 436 s_llptw_req := true.B 437 s_hptw_req := true.B 438 w_hptw_resp := true.B 439 s_last_hptw_req := true.B 440 w_last_hptw_resp := true.B 441 mem_addr_update := true.B 442 need_last_s2xlate := false.B 443 if (HasBitmapCheck) { 444 s_bitmap_check := true.B 445 w_bitmap_resp := true.B 446 whether_need_bitmap_check := false.B 447 bitmap_checkfailed := false.B 448 } 449 } 450 451 when(guestFault && idle === false.B){ 452 s_pmp_check := true.B 453 s_mem_req := true.B 454 w_mem_resp := true.B 455 s_llptw_req := true.B 456 s_hptw_req := true.B 457 w_hptw_resp := true.B 458 s_last_hptw_req := true.B 459 w_last_hptw_resp := true.B 460 mem_addr_update := true.B 461 need_last_s2xlate := false.B 462 if (HasBitmapCheck) { 463 s_bitmap_check := true.B 464 w_bitmap_resp := true.B 465 whether_need_bitmap_check := false.B 466 bitmap_checkfailed := false.B 467 } 468 } 469 470 when (mem.req.fire){ 471 s_mem_req := true.B 472 w_mem_resp := false.B 473 } 474 475 when(mem.resp.fire && w_mem_resp === false.B){ 476 w_mem_resp := true.B 477 af_level := af_level - 1.U 478 gpf_level := Mux(mode === Sv39 && !pte_valid && !(l3Hit || l2Hit), gpf_level - 2.U, gpf_level - 1.U) 479 pte_valid := true.B 480 update_full_gvpn_mem_resp := true.B 481 if (HasBitmapCheck) { 482 when (bitmap_enable) { 483 whether_need_bitmap_check := true.B 484 } .otherwise { 485 s_llptw_req := false.B 486 mem_addr_update := true.B 487 whether_need_bitmap_check := false.B 488 } 489 } else { 490 s_llptw_req := false.B 491 mem_addr_update := true.B 492 } 493 } 494 495 when(update_full_gvpn_mem_resp) { 496 update_full_gvpn_mem_resp := false.B 497 full_gvpn_reg := pte.getPPN() 498 } 499 500 if (HasBitmapCheck) { 501 when (whether_need_bitmap_check) { 502 when (bitmap_enable && (!enableS2xlate || onlyS1xlate) && pte.isLeaf()) { 503 s_bitmap_check := false.B 504 whether_need_bitmap_check := false.B 505 } .otherwise { 506 mem_addr_update := true.B 507 s_llptw_req := false.B 508 whether_need_bitmap_check := false.B 509 } 510 } 511 // bitmapcheck 512 when (io.bitmap.get.req.fire) { 513 s_bitmap_check := true.B 514 w_bitmap_resp := false.B 515 } 516 when (io.bitmap.get.resp.fire) { 517 w_bitmap_resp := true.B 518 mem_addr_update := true.B 519 bitmap_checkfailed := io.bitmap.get.resp.bits.cf 520 } 521 } 522 523 when(mem_addr_update){ 524 when(level >= 2.U && !onlyS2xlate && !(guestFault || find_pte || accessFault)) { 525 level := levelNext 526 when(s2xlate){ 527 s_hptw_req := false.B 528 }.otherwise{ 529 s_mem_req := false.B 530 } 531 s_llptw_req := true.B 532 mem_addr_update := false.B 533 }.elsewhen(io.llptw.valid){ 534 when(io.llptw.fire) { 535 idle := true.B 536 s_llptw_req := true.B 537 mem_addr_update := false.B 538 need_last_s2xlate := false.B 539 } 540 finish := true.B 541 }.elsewhen(s2xlate && need_last_s2xlate === true.B) { 542 need_last_s2xlate := false.B 543 when(!(guestFault || accessFault || pageFault || ppn_af)){ 544 s_last_hptw_req := false.B 545 mem_addr_update := false.B 546 } 547 }.elsewhen(io.resp.valid){ 548 when(io.resp.fire) { 549 idle := true.B 550 s_llptw_req := true.B 551 mem_addr_update := false.B 552 accessFault := false.B 553 } 554 finish := true.B 555 } 556 } 557 558 559 when (flush) { 560 idle := true.B 561 s_pmp_check := true.B 562 s_mem_req := true.B 563 s_llptw_req := true.B 564 w_mem_resp := true.B 565 accessFault := false.B 566 mem_addr_update := false.B 567 s_hptw_req := true.B 568 w_hptw_resp := true.B 569 s_last_hptw_req := true.B 570 w_last_hptw_resp := true.B 571 if (HasBitmapCheck) { 572 s_bitmap_check := true.B 573 w_bitmap_resp := true.B 574 whether_need_bitmap_check := false.B 575 bitmap_checkfailed := false.B 576 } 577 } 578 579 580 XSDebug(p"[ptw] level:${level} notFound:${pageFault}\n") 581 582 // perf 583 XSPerfAccumulate("fsm_count", io.req.fire) 584 for (i <- 0 until PtwWidth) { 585 XSPerfAccumulate(s"fsm_count_source${i}", io.req.fire && io.req.bits.req_info.source === i.U) 586 } 587 XSPerfAccumulate("fsm_busy", !idle) 588 XSPerfAccumulate("fsm_idle", idle) 589 XSPerfAccumulate("resp_blocked", io.resp.valid && !io.resp.ready) 590 XSPerfAccumulate("ptw_ppn_af", io.resp.fire && ppn_af) 591 XSPerfAccumulate("mem_count", mem.req.fire) 592 XSPerfAccumulate("mem_cycle", BoolStopWatch(mem.req.fire, mem.resp.fire, true)) 593 XSPerfAccumulate("mem_blocked", mem.req.valid && !mem.req.ready) 594 595 val perfEvents = Seq( 596 ("fsm_count ", io.req.fire ), 597 ("fsm_busy ", !idle ), 598 ("fsm_idle ", idle ), 599 ("resp_blocked ", io.resp.valid && !io.resp.ready ), 600 ("mem_count ", mem.req.fire ), 601 ("mem_cycle ", BoolStopWatch(mem.req.fire, mem.resp.fire, true)), 602 ("mem_blocked ", mem.req.valid && !mem.req.ready ), 603 ) 604 generatePerfEvent() 605} 606 607/*========================= LLPTW ==============================*/ 608 609/** LLPTW : Last Level Page Table Walker 610 * the page walker that only takes 4KB(last level) page walk. 611 **/ 612 613class LLPTWInBundle(implicit p: Parameters) extends XSBundle with HasPtwConst { 614 val req_info = Output(new L2TlbInnerBundle()) 615 val ppn = Output(UInt(ptePPNLen.W)) 616 val bitmapCheck = Option.when(HasBitmapCheck)(new Bundle { 617 val jmp_bitmap_check = Bool() // find pte in l0 or sp, but need bitmap check 618 val ptes = Vec(tlbcontiguous, UInt(XLEN.W)) // Page Table Entry Vector 619 val cfs = Vec(tlbcontiguous, Bool()) // Bitmap Check Failed Vector 620 val hitway = UInt(l2tlbParams.l0nWays.W) 621 }) 622} 623 624class LLPTWIO(implicit p: Parameters) extends MMUIOBaseBundle with HasPtwConst { 625 val in = Flipped(DecoupledIO(new LLPTWInBundle())) 626 val out = DecoupledIO(new Bundle { 627 val req_info = Output(new L2TlbInnerBundle()) 628 val id = Output(UInt(bMemID.W)) 629 val h_resp = Output(new HptwResp) 630 val first_s2xlate_fault = Output(Bool()) // Whether the first stage 2 translation occurs pf/af 631 val af = Output(Bool()) 632 val bitmapCheck = Option.when(HasBitmapCheck)(new Bundle { 633 val jmp_bitmap_check = Bool() // find pte in l0 or sp, but need bitmap check 634 val ptes = Vec(tlbcontiguous, UInt(XLEN.W)) // Page Table Entry Vector 635 val cfs = Vec(tlbcontiguous, Bool()) // Bitmap Check Failed Vector 636 }) 637 }) 638 val mem = new Bundle { 639 val req = DecoupledIO(new L2TlbMemReqBundle()) 640 val resp = Flipped(Valid(new Bundle { 641 val id = Output(UInt(log2Up(l2tlbParams.llptwsize).W)) 642 val value = Output(UInt(blockBits.W)) 643 })) 644 val enq_ptr = Output(UInt(log2Ceil(l2tlbParams.llptwsize).W)) 645 val buffer_it = Output(Vec(l2tlbParams.llptwsize, Bool())) 646 val refill = Output(new L2TlbInnerBundle()) 647 val req_mask = Input(Vec(l2tlbParams.llptwsize, Bool())) 648 val flush_latch = Input(Vec(l2tlbParams.llptwsize, Bool())) 649 } 650 val cache = DecoupledIO(new L2TlbInnerBundle()) 651 val pmp = new Bundle { 652 val req = Valid(new PMPReqBundle()) 653 val resp = Flipped(new PMPRespBundle()) 654 } 655 val hptw = new Bundle { 656 val req = DecoupledIO(new Bundle{ 657 val source = UInt(bSourceWidth.W) 658 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 659 val gvpn = UInt(ptePPNLen.W) 660 }) 661 val resp = Flipped(Valid(new Bundle { 662 val id = Output(UInt(log2Up(l2tlbParams.llptwsize).W)) 663 val h_resp = Output(new HptwResp) 664 })) 665 } 666 val bitmap = Option.when(HasBitmapCheck)(new Bundle { 667 val req = DecoupledIO(new bitmapReqBundle()) 668 val resp = Flipped(DecoupledIO(new bitmapRespBundle())) 669 }) 670 671 val l0_way_info = Option.when(HasBitmapCheck)(Input(UInt(l2tlbParams.l0nWays.W))) 672} 673 674class LLPTWEntry(implicit p: Parameters) extends XSBundle with HasPtwConst { 675 val req_info = new L2TlbInnerBundle() 676 val ppn = UInt(ptePPNLen.W) 677 val wait_id = UInt(log2Up(l2tlbParams.llptwsize).W) 678 val af = Bool() 679 val hptw_resp = new HptwResp() 680 val first_s2xlate_fault = Output(Bool()) 681 val cf = Bool() 682 val from_l0 = Bool() 683 val way_info = UInt(l2tlbParams.l0nWays.W) 684 val jmp_bitmap_check = Bool() 685 val ptes = Vec(tlbcontiguous, UInt(XLEN.W)) 686 val cfs = Vec(tlbcontiguous, Bool()) 687} 688 689 690class LLPTW(implicit p: Parameters) extends XSModule with HasPtwConst with HasPerfEvents { 691 val io = IO(new LLPTWIO()) 692 val enableS2xlate = io.in.bits.req_info.s2xlate =/= noS2xlate 693 val satp = Mux(enableS2xlate, io.csr.vsatp, io.csr.satp) 694 val s1Pbmte = Mux(enableS2xlate, io.csr.hPBMTE, io.csr.mPBMTE) 695 696 // mbmc:bitmap csr 697 val mbmc = io.csr.mbmc 698 val bitmap_enable = (if (HasBitmapCheck) true.B else false.B) && mbmc.BME === 1.U && mbmc.CMODE === 0.U 699 700 val flush = io.sfence.valid || io.csr.satp.changed || io.csr.vsatp.changed || io.csr.hgatp.changed 701 val entries = RegInit(VecInit(Seq.fill(l2tlbParams.llptwsize)(0.U.asTypeOf(new LLPTWEntry())))) 702 val state_idle :: state_hptw_req :: state_hptw_resp :: state_addr_check :: state_mem_req :: state_mem_waiting :: state_mem_out :: state_last_hptw_req :: state_last_hptw_resp :: state_cache :: state_bitmap_check :: state_bitmap_resp :: Nil = Enum(12) 703 val state = RegInit(VecInit(Seq.fill(l2tlbParams.llptwsize)(state_idle))) 704 705 val is_emptys = state.map(_ === state_idle) 706 val is_mems = state.map(_ === state_mem_req) 707 val is_waiting = state.map(_ === state_mem_waiting) 708 val is_having = state.map(_ === state_mem_out) 709 val is_cache = state.map(_ === state_cache) 710 val is_hptw_req = state.map(_ === state_hptw_req) 711 val is_last_hptw_req = state.map(_ === state_last_hptw_req) 712 val is_hptw_resp = state.map(_ === state_hptw_resp) 713 val is_last_hptw_resp = state.map(_ === state_last_hptw_resp) 714 val is_bitmap_req = state.map(_ === state_bitmap_check) 715 val is_bitmap_resp = state.map(_ === state_bitmap_resp) 716 717 val full = !ParallelOR(is_emptys).asBool 718 val enq_ptr = ParallelPriorityEncoder(is_emptys) 719 720 val mem_ptr = ParallelPriorityEncoder(is_having) // TODO: optimize timing, bad: entries -> ptr -> entry 721 val mem_arb = Module(new RRArbiterInit(new LLPTWEntry(), l2tlbParams.llptwsize)) 722 for (i <- 0 until l2tlbParams.llptwsize) { 723 mem_arb.io.in(i).bits := entries(i) 724 mem_arb.io.in(i).valid := is_mems(i) && !io.mem.req_mask(i) 725 } 726 727 // process hptw requests in serial 728 val hyper_arb1 = Module(new RRArbiterInit(new LLPTWEntry(), l2tlbParams.llptwsize)) 729 for (i <- 0 until l2tlbParams.llptwsize) { 730 hyper_arb1.io.in(i).bits := entries(i) 731 hyper_arb1.io.in(i).valid := is_hptw_req(i) && !(Cat(is_hptw_resp).orR) && !(Cat(is_last_hptw_resp).orR) 732 } 733 val hyper_arb2 = Module(new RRArbiterInit(new LLPTWEntry(), l2tlbParams.llptwsize)) 734 for(i <- 0 until l2tlbParams.llptwsize) { 735 hyper_arb2.io.in(i).bits := entries(i) 736 hyper_arb2.io.in(i).valid := is_last_hptw_req(i) && !(Cat(is_hptw_resp).orR) && !(Cat(is_last_hptw_resp).orR) 737 } 738 739 740 val bitmap_arb = Option.when(HasBitmapCheck)(Module(new RRArbiter(new bitmapReqBundle(), l2tlbParams.llptwsize))) 741 val way_info = Option.when(HasBitmapCheck)(Wire(Vec(l2tlbParams.llptwsize, UInt(l2tlbParams.l0nWays.W)))) 742 if (HasBitmapCheck) { 743 for (i <- 0 until l2tlbParams.llptwsize) { 744 bitmap_arb.get.io.in(i).valid := is_bitmap_req(i) 745 bitmap_arb.get.io.in(i).bits.bmppn := entries(i).ppn 746 bitmap_arb.get.io.in(i).bits.vpn := entries(i).req_info.vpn 747 bitmap_arb.get.io.in(i).bits.id := i.U 748 bitmap_arb.get.io.in(i).bits.level := 0.U // last level 749 bitmap_arb.get.io.in(i).bits.way_info := Mux(entries(i).from_l0, entries(i).way_info, way_info.get(i)) 750 bitmap_arb.get.io.in(i).bits.hptw_bypassed := false.B 751 } 752 } 753 754 val cache_ptr = ParallelMux(is_cache, (0 until l2tlbParams.llptwsize).map(_.U(log2Up(l2tlbParams.llptwsize).W))) 755 756 // duplicate req 757 // to_wait: wait for the last to access mem, set to mem_resp 758 // to_cache: the last is back just right now, set to mem_cache 759 val dup_vec = state.indices.map(i => 760 dup(io.in.bits.req_info.vpn, entries(i).req_info.vpn) && io.in.bits.req_info.s2xlate === entries(i).req_info.s2xlate 761 ) 762 val dup_req_fire = mem_arb.io.out.fire && dup(io.in.bits.req_info.vpn, mem_arb.io.out.bits.req_info.vpn) && io.in.bits.req_info.s2xlate === mem_arb.io.out.bits.req_info.s2xlate // dup with the req fire entry 763 val dup_vec_wait = dup_vec.zip(is_waiting).map{case (d, w) => d && w} // dup with "mem_waiting" entries, sending mem req already 764 val dup_vec_having = dup_vec.zipWithIndex.map{case (d, i) => d && is_having(i)} // dup with the "mem_out" entry recv the data just now 765 val dup_vec_bitmap = dup_vec.zipWithIndex.map{case (d, i) => d && (is_bitmap_req(i) || is_bitmap_resp(i))} 766 val dup_vec_last_hptw = dup_vec.zipWithIndex.map{case (d, i) => d && (is_last_hptw_req(i) || is_last_hptw_resp(i))} 767 val wait_id = Mux(dup_req_fire, mem_arb.io.chosen, ParallelMux(dup_vec_wait zip entries.map(_.wait_id))) 768 val dup_wait_resp = io.mem.resp.fire && VecInit(dup_vec_wait)(io.mem.resp.bits.id) && !io.mem.flush_latch(io.mem.resp.bits.id) // dup with the entry that data coming next cycle 769 val to_wait = Cat(dup_vec_wait).orR || dup_req_fire 770 val to_mem_out = dup_wait_resp && ((entries(io.mem.resp.bits.id).req_info.s2xlate === noS2xlate) || (entries(io.mem.resp.bits.id).req_info.s2xlate === onlyStage1)) && !bitmap_enable 771 val to_bitmap_req = (if (HasBitmapCheck) true.B else false.B) && dup_wait_resp && ((entries(io.mem.resp.bits.id).req_info.s2xlate === noS2xlate) || (entries(io.mem.resp.bits.id).req_info.s2xlate === onlyStage1)) && bitmap_enable 772 val to_cache = if (HasBitmapCheck) Cat(dup_vec_bitmap).orR || Cat(dup_vec_having).orR || Cat(dup_vec_last_hptw).orR 773 else Cat(dup_vec_having).orR || Cat(dup_vec_last_hptw).orR 774 val to_hptw_req = io.in.bits.req_info.s2xlate === allStage 775 val to_last_hptw_req = dup_wait_resp && entries(io.mem.resp.bits.id).req_info.s2xlate === allStage 776 val last_hptw_req_id = io.mem.resp.bits.id 777 val req_paddr = MakeAddr(io.in.bits.ppn(ppnLen-1, 0), getVpnn(io.in.bits.req_info.vpn, 0)) 778 val req_hpaddr = MakeAddr(entries(last_hptw_req_id).hptw_resp.genPPNS2(get_pn(req_paddr)), getVpnn(io.in.bits.req_info.vpn, 0)) 779 val index = Mux(entries(last_hptw_req_id).req_info.s2xlate === allStage, req_hpaddr, req_paddr)(log2Up(l2tlbParams.blockBytes)-1, log2Up(XLEN/8)) 780 val last_hptw_req_ppn = io.mem.resp.bits.value.asTypeOf(Vec(blockBits / XLEN, new PteBundle()))(index).getPPN() 781 XSError(RegNext(dup_req_fire && Cat(dup_vec_wait).orR, init = false.B), "mem req but some entries already waiting, should not happed") 782 783 XSError(io.in.fire && ((to_mem_out && to_cache) || (to_wait && to_cache)), "llptw enq, to cache conflict with to mem") 784 val mem_resp_hit = RegInit(VecInit(Seq.fill(l2tlbParams.llptwsize)(false.B))) 785 val enq_state_normal = MuxCase(state_addr_check, Seq( 786 to_mem_out -> state_mem_out, // same to the blew, but the mem resp now 787 to_bitmap_req -> state_bitmap_check, 788 to_last_hptw_req -> state_last_hptw_req, 789 to_wait -> state_mem_waiting, 790 to_cache -> state_cache, 791 to_hptw_req -> state_hptw_req 792 )) 793 val enq_state = Mux(from_pre(io.in.bits.req_info.source) && enq_state_normal =/= state_addr_check, state_idle, enq_state_normal) 794 when (io.in.fire && (if (HasBitmapCheck) !io.in.bits.bitmapCheck.get.jmp_bitmap_check else true.B)) { 795 // if prefetch req does not need mem access, just give it up. 796 // so there will be at most 1 + FilterSize entries that needs re-access page cache 797 // so 2 + FilterSize is enough to avoid dead-lock 798 state(enq_ptr) := enq_state 799 entries(enq_ptr).req_info := io.in.bits.req_info 800 entries(enq_ptr).ppn := Mux(to_last_hptw_req, last_hptw_req_ppn, io.in.bits.ppn) 801 entries(enq_ptr).wait_id := Mux(to_wait, wait_id, enq_ptr) 802 entries(enq_ptr).af := false.B 803 if (HasBitmapCheck) { 804 entries(enq_ptr).cf := false.B 805 entries(enq_ptr).from_l0 := false.B 806 entries(enq_ptr).way_info := 0.U 807 entries(enq_ptr).jmp_bitmap_check := false.B 808 for (i <- 0 until tlbcontiguous) { 809 entries(enq_ptr).ptes(i) := 0.U 810 } 811 entries(enq_ptr).cfs := io.in.bits.bitmapCheck.get.cfs 812 } 813 entries(enq_ptr).hptw_resp := Mux(to_last_hptw_req, entries(last_hptw_req_id).hptw_resp, Mux(to_wait, entries(wait_id).hptw_resp, entries(enq_ptr).hptw_resp)) 814 entries(enq_ptr).first_s2xlate_fault := false.B 815 mem_resp_hit(enq_ptr) := to_bitmap_req || to_mem_out || to_last_hptw_req 816 } 817 818 if (HasBitmapCheck) { 819 when (io.in.bits.bitmapCheck.get.jmp_bitmap_check && io.in.fire) { 820 state(enq_ptr) := state_bitmap_check 821 entries(enq_ptr).req_info := io.in.bits.req_info 822 entries(enq_ptr).ppn := io.in.bits.bitmapCheck.get.ptes(io.in.bits.req_info.vpn(sectortlbwidth - 1, 0)).asTypeOf(new PteBundle().cloneType).ppn 823 entries(enq_ptr).wait_id := enq_ptr 824 entries(enq_ptr).af := false.B 825 entries(enq_ptr).cf := false.B 826 entries(enq_ptr).from_l0 := true.B 827 entries(enq_ptr).way_info := io.in.bits.bitmapCheck.get.hitway 828 entries(enq_ptr).jmp_bitmap_check := io.in.bits.bitmapCheck.get.jmp_bitmap_check 829 entries(enq_ptr).ptes := io.in.bits.bitmapCheck.get.ptes 830 entries(enq_ptr).cfs := io.in.bits.bitmapCheck.get.cfs 831 mem_resp_hit(enq_ptr) := false.B 832 } 833 } 834 835 val enq_ptr_reg = RegNext(enq_ptr) 836 val need_addr_check = GatedValidRegNext(enq_state === state_addr_check && io.in.fire && !flush && (if (HasBitmapCheck) !io.in.bits.bitmapCheck.get.jmp_bitmap_check else true.B)) 837 838 val hasHptwResp = ParallelOR(state.map(_ === state_hptw_resp)).asBool 839 val hptw_resp_ptr_reg = RegNext(io.hptw.resp.bits.id) 840 val hptw_need_addr_check = RegNext(hasHptwResp && io.hptw.resp.fire && !flush) && state(hptw_resp_ptr_reg) === state_addr_check 841 842 val ptes = io.mem.resp.bits.value.asTypeOf(Vec(blockBits / XLEN, new PteBundle())) 843 val gpaddr = MakeGPAddr(entries(hptw_resp_ptr_reg).ppn, getVpnn(entries(hptw_resp_ptr_reg).req_info.vpn, 0)) 844 val hptw_resp = entries(hptw_resp_ptr_reg).hptw_resp 845 val hpaddr = Cat(hptw_resp.genPPNS2(get_pn(gpaddr)), get_off(gpaddr)) 846 val addr = RegEnable(MakeAddr(io.in.bits.ppn(ppnLen - 1, 0), getVpnn(io.in.bits.req_info.vpn, 0)), io.in.fire) 847 io.pmp.req.valid := need_addr_check || hptw_need_addr_check 848 io.pmp.req.bits.addr := Mux(hptw_need_addr_check, hpaddr, addr) 849 io.pmp.req.bits.cmd := TlbCmd.read 850 io.pmp.req.bits.size := 3.U // TODO: fix it 851 val pmp_resp_valid = io.pmp.req.valid // same cycle 852 when (pmp_resp_valid) { 853 // NOTE: when pmp resp but state is not addr check, then the entry is dup with other entry, the state was changed before 854 // when dup with the req-ing entry, set to mem_waiting (above codes), and the ld must be false, so dontcare 855 val ptr = Mux(hptw_need_addr_check, hptw_resp_ptr_reg, enq_ptr_reg); 856 val accessFault = io.pmp.resp.ld || io.pmp.resp.mmio 857 entries(ptr).af := accessFault 858 state(ptr) := Mux(accessFault, state_mem_out, state_mem_req) 859 } 860 861 when (mem_arb.io.out.fire) { 862 for (i <- state.indices) { 863 when (state(i) =/= state_idle && state(i) =/= state_mem_out && state(i) =/= state_last_hptw_req && state(i) =/= state_last_hptw_resp 864 && (if (HasBitmapCheck) state(i) =/= state_bitmap_check && state(i) =/= state_bitmap_resp else true.B) 865 && entries(i).req_info.s2xlate === mem_arb.io.out.bits.req_info.s2xlate 866 && dup(entries(i).req_info.vpn, mem_arb.io.out.bits.req_info.vpn)) { 867 // NOTE: "dup enq set state to mem_wait" -> "sending req set other dup entries to mem_wait" 868 state(i) := state_mem_waiting 869 entries(i).hptw_resp := entries(mem_arb.io.chosen).hptw_resp 870 entries(i).wait_id := mem_arb.io.chosen 871 } 872 } 873 } 874 when (io.mem.resp.fire) { 875 state.indices.map{i => 876 when (state(i) === state_mem_waiting && io.mem.resp.bits.id === entries(i).wait_id) { 877 val req_paddr = MakeAddr(entries(i).ppn, getVpnn(entries(i).req_info.vpn, 0)) 878 val req_hpaddr = MakeAddr(entries(i).hptw_resp.genPPNS2(get_pn(req_paddr)), getVpnn(entries(i).req_info.vpn, 0)) 879 val index = Mux(entries(i).req_info.s2xlate === allStage, req_hpaddr, req_paddr)(log2Up(l2tlbParams.blockBytes)-1, log2Up(XLEN/8)) 880 val allStageExcp = ptes(index).isPf(0.U, s1Pbmte) || !ptes(index).isLeaf() || ptes(index).isStage1Gpf(io.csr.vsatp.mode) 881 state(i) := Mux((entries(i).req_info.s2xlate === allStage && !allStageExcp), 882 state_last_hptw_req, 883 Mux(bitmap_enable, state_bitmap_check, state_mem_out)) 884 mem_resp_hit(i) := true.B 885 entries(i).ppn := ptes(index).getPPN() // for last stage 2 translation 886 // af will be judged in L2 TLB `contiguous_pte_to_merge_ptwResp` 887 entries(i).hptw_resp.gpf := Mux(entries(i).req_info.s2xlate === allStage, ptes(index).isStage1Gpf(io.csr.vsatp.mode), false.B) 888 } 889 } 890 } 891 892 if (HasBitmapCheck) { 893 for (i <- 0 until l2tlbParams.llptwsize) { 894 way_info.get(i) := DataHoldBypass(io.l0_way_info.get, mem_resp_hit(i)) 895 } 896 } 897 898 when (hyper_arb1.io.out.fire) { 899 for (i <- state.indices) { 900 when (state(i) === state_hptw_req && entries(i).ppn === hyper_arb1.io.out.bits.ppn && entries(i).req_info.s2xlate === allStage && hyper_arb1.io.chosen === i.U) { 901 state(i) := state_hptw_resp 902 entries(i).wait_id := hyper_arb1.io.chosen 903 } 904 } 905 } 906 907 when (hyper_arb2.io.out.fire) { 908 for (i <- state.indices) { 909 when (state(i) === state_last_hptw_req && entries(i).ppn === hyper_arb2.io.out.bits.ppn && entries(i).req_info.s2xlate === allStage && hyper_arb2.io.chosen === i.U) { 910 state(i) := state_last_hptw_resp 911 entries(i).wait_id := hyper_arb2.io.chosen 912 } 913 } 914 } 915 916 if (HasBitmapCheck) { 917 when (bitmap_arb.get.io.out.fire) { 918 for (i <- state.indices) { 919 when (is_bitmap_req(i) && bitmap_arb.get.io.out.bits.bmppn === entries(i).ppn(ppnLen - 1, 0)) { 920 state(i) := state_bitmap_resp 921 entries(i).wait_id := bitmap_arb.get.io.chosen 922 } 923 } 924 } 925 926 when (io.bitmap.get.resp.fire) { 927 for (i <- state.indices) { 928 when (is_bitmap_resp(i) && io.bitmap.get.resp.bits.id === entries(i).wait_id) { 929 entries(i).cfs := io.bitmap.get.resp.bits.cfs 930 entries(i).cf := io.bitmap.get.resp.bits.cf 931 state(i) := state_mem_out 932 } 933 } 934 } 935 } 936 937 when (io.hptw.resp.fire) { 938 for (i <- state.indices) { 939 when (state(i) === state_hptw_resp && io.hptw.resp.bits.id === entries(i).wait_id && io.hptw.resp.bits.h_resp.entry.tag === entries(i).ppn) { 940 val check_g_perm_fail = !io.hptw.resp.bits.h_resp.gaf && (!io.hptw.resp.bits.h_resp.entry.perm.get.r && !(io.csr.priv.mxr && io.hptw.resp.bits.h_resp.entry.perm.get.x)) 941 when (check_g_perm_fail || io.hptw.resp.bits.h_resp.gaf || io.hptw.resp.bits.h_resp.gpf) { 942 state(i) := state_mem_out 943 entries(i).hptw_resp := io.hptw.resp.bits.h_resp 944 entries(i).hptw_resp.gpf := io.hptw.resp.bits.h_resp.gpf || check_g_perm_fail 945 entries(i).first_s2xlate_fault := io.hptw.resp.bits.h_resp.gaf || io.hptw.resp.bits.h_resp.gpf 946 }.otherwise{ // change the entry that is waiting hptw resp 947 val need_to_waiting_vec = state.indices.map(i => state(i) === state_mem_waiting && dup(entries(i).req_info.vpn, entries(io.hptw.resp.bits.id).req_info.vpn)) 948 val waiting_index = ParallelMux(need_to_waiting_vec zip entries.map(_.wait_id)) 949 state(i) := Mux(Cat(need_to_waiting_vec).orR, state_mem_waiting, state_addr_check) 950 entries(i).hptw_resp := io.hptw.resp.bits.h_resp 951 entries(i).wait_id := Mux(Cat(need_to_waiting_vec).orR, waiting_index, entries(i).wait_id) 952 //To do: change the entry that is having the same hptw req 953 } 954 } 955 when (state(i) === state_last_hptw_resp && io.hptw.resp.bits.id === entries(i).wait_id && io.hptw.resp.bits.h_resp.entry.tag === entries(i).ppn) { 956 state(i) := state_mem_out 957 entries(i).hptw_resp := io.hptw.resp.bits.h_resp 958 //To do: change the entry that is having the same hptw req 959 } 960 } 961 } 962 when (io.out.fire) { 963 assert(state(mem_ptr) === state_mem_out) 964 state(mem_ptr) := state_idle 965 } 966 mem_resp_hit.map(a => when (a) { a := false.B } ) 967 968 when (io.cache.fire) { 969 state(cache_ptr) := state_idle 970 } 971 XSError(io.out.fire && io.cache.fire && (mem_ptr === cache_ptr), "mem resp and cache fire at the same time at same entry") 972 973 when (flush) { 974 state.map(_ := state_idle) 975 } 976 977 io.in.ready := !full 978 979 io.out.valid := ParallelOR(is_having).asBool 980 io.out.bits.req_info := entries(mem_ptr).req_info 981 io.out.bits.id := mem_ptr 982 if (HasBitmapCheck) { 983 io.out.bits.af := Mux(bitmap_enable, entries(mem_ptr).af || entries(mem_ptr).cf, entries(mem_ptr).af) 984 io.out.bits.bitmapCheck.get.jmp_bitmap_check := entries(mem_ptr).jmp_bitmap_check 985 io.out.bits.bitmapCheck.get.ptes := entries(mem_ptr).ptes 986 io.out.bits.bitmapCheck.get.cfs := entries(mem_ptr).cfs 987 } else { 988 io.out.bits.af := entries(mem_ptr).af 989 } 990 991 io.out.bits.h_resp := entries(mem_ptr).hptw_resp 992 io.out.bits.first_s2xlate_fault := entries(mem_ptr).first_s2xlate_fault 993 994 val hptw_req_arb = Module(new Arbiter(new Bundle{ 995 val source = UInt(bSourceWidth.W) 996 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 997 val ppn = UInt(ptePPNLen.W) 998 } , 2)) 999 // first stage 2 translation 1000 hptw_req_arb.io.in(0).valid := hyper_arb1.io.out.valid 1001 hptw_req_arb.io.in(0).bits.source := hyper_arb1.io.out.bits.req_info.source 1002 hptw_req_arb.io.in(0).bits.ppn := hyper_arb1.io.out.bits.ppn 1003 hptw_req_arb.io.in(0).bits.id := hyper_arb1.io.chosen 1004 hyper_arb1.io.out.ready := hptw_req_arb.io.in(0).ready 1005 // last stage 2 translation 1006 hptw_req_arb.io.in(1).valid := hyper_arb2.io.out.valid 1007 hptw_req_arb.io.in(1).bits.source := hyper_arb2.io.out.bits.req_info.source 1008 hptw_req_arb.io.in(1).bits.ppn := hyper_arb2.io.out.bits.ppn 1009 hptw_req_arb.io.in(1).bits.id := hyper_arb2.io.chosen 1010 hyper_arb2.io.out.ready := hptw_req_arb.io.in(1).ready 1011 hptw_req_arb.io.out.ready := io.hptw.req.ready 1012 io.hptw.req.valid := hptw_req_arb.io.out.fire && !flush 1013 io.hptw.req.bits.gvpn := hptw_req_arb.io.out.bits.ppn 1014 io.hptw.req.bits.id := hptw_req_arb.io.out.bits.id 1015 io.hptw.req.bits.source := hptw_req_arb.io.out.bits.source 1016 1017 io.mem.req.valid := mem_arb.io.out.valid && !flush 1018 val mem_paddr = MakeAddr(mem_arb.io.out.bits.ppn, getVpnn(mem_arb.io.out.bits.req_info.vpn, 0)) 1019 val mem_hpaddr = MakeAddr(mem_arb.io.out.bits.hptw_resp.genPPNS2(get_pn(mem_paddr)), getVpnn(mem_arb.io.out.bits.req_info.vpn, 0)) 1020 io.mem.req.bits.addr := Mux(mem_arb.io.out.bits.req_info.s2xlate === allStage, mem_hpaddr, mem_paddr) 1021 io.mem.req.bits.id := mem_arb.io.chosen 1022 io.mem.req.bits.hptw_bypassed := false.B 1023 mem_arb.io.out.ready := io.mem.req.ready 1024 val mem_refill_id = RegNext(io.mem.resp.bits.id(log2Up(l2tlbParams.llptwsize)-1, 0)) 1025 io.mem.refill := entries(mem_refill_id).req_info 1026 io.mem.refill.s2xlate := entries(mem_refill_id).req_info.s2xlate 1027 io.mem.buffer_it := mem_resp_hit 1028 io.mem.enq_ptr := enq_ptr 1029 1030 io.cache.valid := Cat(is_cache).orR 1031 io.cache.bits := ParallelMux(is_cache, entries.map(_.req_info)) 1032 1033 val has_bitmap_resp = ParallelOR(is_bitmap_resp).asBool 1034 if (HasBitmapCheck) { 1035 io.bitmap.get.req.valid := bitmap_arb.get.io.out.valid && !flush 1036 io.bitmap.get.req.bits.bmppn := bitmap_arb.get.io.out.bits.bmppn 1037 io.bitmap.get.req.bits.id := bitmap_arb.get.io.chosen 1038 io.bitmap.get.req.bits.vpn := bitmap_arb.get.io.out.bits.vpn 1039 io.bitmap.get.req.bits.level := 0.U 1040 io.bitmap.get.req.bits.way_info := bitmap_arb.get.io.out.bits.way_info 1041 io.bitmap.get.req.bits.hptw_bypassed := bitmap_arb.get.io.out.bits.hptw_bypassed 1042 bitmap_arb.get.io.out.ready := io.bitmap.get.req.ready 1043 io.bitmap.get.resp.ready := has_bitmap_resp 1044 } 1045 1046 XSPerfAccumulate("llptw_in_count", io.in.fire) 1047 XSPerfAccumulate("llptw_in_block", io.in.valid && !io.in.ready) 1048 for (i <- 0 until 7) { 1049 XSPerfAccumulate(s"enq_state${i}", io.in.fire && enq_state === i.U) 1050 } 1051 for (i <- 0 until (l2tlbParams.llptwsize + 1)) { 1052 XSPerfAccumulate(s"util${i}", PopCount(is_emptys.map(!_)) === i.U) 1053 XSPerfAccumulate(s"mem_util${i}", PopCount(is_mems) === i.U) 1054 XSPerfAccumulate(s"waiting_util${i}", PopCount(is_waiting) === i.U) 1055 } 1056 XSPerfAccumulate("mem_count", io.mem.req.fire) 1057 XSPerfAccumulate("mem_cycle", PopCount(is_waiting) =/= 0.U) 1058 XSPerfAccumulate("blocked_in", io.in.valid && !io.in.ready) 1059 1060 val perfEvents = Seq( 1061 ("tlbllptw_incount ", io.in.fire ), 1062 ("tlbllptw_inblock ", io.in.valid && !io.in.ready), 1063 ("tlbllptw_memcount ", io.mem.req.fire ), 1064 ("tlbllptw_memcycle ", PopCount(is_waiting) ), 1065 ) 1066 generatePerfEvent() 1067} 1068 1069/*========================= HPTW ==============================*/ 1070 1071/** HPTW : Hypervisor Page Table Walker 1072 * the page walker take the virtual machine's page walk. 1073 * guest physical address translation, guest physical address -> host physical address 1074 **/ 1075class HPTWIO()(implicit p: Parameters) extends MMUIOBaseBundle with HasPtwConst { 1076 val req = Flipped(DecoupledIO(new Bundle { 1077 val source = UInt(bSourceWidth.W) 1078 val id = UInt(log2Up(l2tlbParams.llptwsize).W) 1079 val gvpn = UInt(gvpnLen.W) 1080 val ppn = UInt(ppnLen.W) 1081 val l3Hit = if (EnableSv48) Some(new Bool()) else None 1082 val l2Hit = Bool() 1083 val l1Hit = Bool() 1084 val bypassed = Bool() // if bypass, don't refill 1085 val bitmapCheck = Option.when(HasBitmapCheck)(new Bundle { 1086 val jmp_bitmap_check = Bool() // find pte in l0 or sp, but need bitmap check 1087 val pte = UInt(XLEN.W) // Page Table Entry 1088 val ptes = Vec(tlbcontiguous, UInt(XLEN.W)) // Page Table Entry Vector 1089 val cfs = Vec(tlbcontiguous, Bool()) // Bitmap Check Failed Vector 1090 val hitway = UInt(l2tlbParams.l0nWays.W) 1091 val fromSP = Bool() 1092 val SPlevel = UInt(log2Up(Level).W) 1093 }) 1094 })) 1095 val resp = DecoupledIO(new Bundle { 1096 val source = UInt(bSourceWidth.W) 1097 val resp = Output(new HptwResp()) 1098 val id = Output(UInt(bMemID.W)) 1099 }) 1100 1101 val mem = new Bundle { 1102 val req = DecoupledIO(new L2TlbMemReqBundle()) 1103 val resp = Flipped(ValidIO(UInt(XLEN.W))) 1104 val mask = Input(Bool()) 1105 } 1106 val refill = Output(new Bundle { 1107 val req_info = new L2TlbInnerBundle() 1108 val level = UInt(log2Up(Level + 1).W) 1109 }) 1110 val pmp = new Bundle { 1111 val req = ValidIO(new PMPReqBundle()) 1112 val resp = Flipped(new PMPRespBundle()) 1113 } 1114 val bitmap = Option.when(HasBitmapCheck)(new Bundle { 1115 val req = DecoupledIO(new bitmapReqBundle()) 1116 val resp = Flipped(DecoupledIO(new bitmapRespBundle())) 1117 }) 1118 1119 val l0_way_info = Option.when(HasBitmapCheck)(Input(UInt(l2tlbParams.l0nWays.W))) 1120} 1121 1122class HPTW()(implicit p: Parameters) extends XSModule with HasPtwConst { 1123 val io = IO(new HPTWIO) 1124 val hgatp = io.csr.hgatp 1125 val mpbmte = io.csr.mPBMTE 1126 val sfence = io.sfence 1127 val flush = sfence.valid || hgatp.changed || io.csr.satp.changed || io.csr.vsatp.changed 1128 val mode = hgatp.mode 1129 1130 // mbmc:bitmap csr 1131 val mbmc = io.csr.mbmc 1132 val bitmap_enable = (if (HasBitmapCheck) true.B else false.B) && mbmc.BME === 1.U && mbmc.CMODE === 0.U 1133 1134 val level = RegInit(3.U(log2Up(Level + 1).W)) 1135 val af_level = RegInit(3.U(log2Up(Level + 1).W)) // access fault return this level 1136 val gpaddr = Reg(UInt(GPAddrBits.W)) 1137 val req_ppn = Reg(UInt(ppnLen.W)) 1138 val vpn = gpaddr(GPAddrBits-1, offLen) 1139 val levelNext = level - 1.U 1140 val l3Hit = Reg(Bool()) 1141 val l2Hit = Reg(Bool()) 1142 val l1Hit = Reg(Bool()) 1143 val bypassed = Reg(Bool()) 1144// val pte = io.mem.resp.bits.MergeRespToPte() 1145 val jmp_bitmap_check = if (HasBitmapCheck) RegEnable(io.req.bits.bitmapCheck.get.jmp_bitmap_check, io.req.fire) else false.B 1146 val fromSP = if (HasBitmapCheck) RegEnable(io.req.bits.bitmapCheck.get.fromSP, io.req.fire) else false.B 1147 val cache_pte = Option.when(HasBitmapCheck)(RegEnable(Mux(io.req.bits.bitmapCheck.get.fromSP, io.req.bits.bitmapCheck.get.pte.asTypeOf(new PteBundle().cloneType), io.req.bits.bitmapCheck.get.ptes(io.req.bits.gvpn(sectortlbwidth - 1, 0)).asTypeOf(new PteBundle().cloneType)), io.req.fire)) 1148 val pte = if (HasBitmapCheck) Mux(jmp_bitmap_check, cache_pte.get, io.mem.resp.bits.asTypeOf(new PteBundle().cloneType)) else io.mem.resp.bits.asTypeOf(new PteBundle().cloneType) 1149 val ppn_l3 = Mux(l3Hit, req_ppn, pte.ppn) 1150 val ppn_l2 = Mux(l2Hit, req_ppn, pte.ppn) 1151 val ppn_l1 = Mux(l1Hit, req_ppn, pte.ppn) 1152 val ppn = Wire(UInt(PAddrBits.W)) 1153 val p_pte = MakeAddr(ppn, getVpnn(vpn, level)) 1154 val pg_base = Wire(UInt(PAddrBits.W)) 1155 val mem_addr = Wire(UInt(PAddrBits.W)) 1156 if (EnableSv48) { 1157 when (mode === Sv48) { 1158 ppn := Mux(af_level === 2.U, ppn_l3, Mux(af_level === 1.U, ppn_l2, ppn_l1)) // for l2, l1 and l3 1159 pg_base := MakeGPAddr(hgatp.ppn, getGVpnn(vpn, 3.U, mode = Sv48)) // for l3 1160 mem_addr := Mux(af_level === 3.U, pg_base, p_pte) 1161 } .otherwise { 1162 ppn := Mux(af_level === 1.U, ppn_l2, ppn_l1) //for l1 and l2 1163 pg_base := MakeGPAddr(hgatp.ppn, getGVpnn(vpn, 2.U, mode = Sv39)) 1164 mem_addr := Mux(af_level === 2.U, pg_base, p_pte) 1165 } 1166 } else { 1167 ppn := Mux(af_level === 1.U, ppn_l2, ppn_l1) //for l1 and l2 1168 pg_base := MakeGPAddr(hgatp.ppn, getGVpnn(vpn, 2.U, mode = Sv39)) 1169 mem_addr := Mux(af_level === 2.U, pg_base, p_pte) 1170 } 1171 1172 //s/w register 1173 val s_pmp_check = RegInit(true.B) 1174 val s_mem_req = RegInit(true.B) 1175 val w_mem_resp = RegInit(true.B) 1176 val idle = RegInit(true.B) 1177 val mem_addr_update = RegInit(false.B) 1178 val finish = WireInit(false.B) 1179 val s_bitmap_check = RegInit(true.B) 1180 val w_bitmap_resp = RegInit(true.B) 1181 val whether_need_bitmap_check = RegInit(false.B) 1182 val bitmap_checkfailed = RegInit(false.B) 1183 1184 val sent_to_pmp = !idle && (!s_pmp_check || mem_addr_update) && !finish 1185 val pageFault = pte.isGpf(level, mpbmte) || (!pte.isLeaf() && level === 0.U) 1186 val accessFault = RegEnable(io.pmp.resp.ld || io.pmp.resp.mmio, sent_to_pmp) 1187 1188 // use access fault when bitmap check failed 1189 val ppn_af = if (HasBitmapCheck) { 1190 Mux(bitmap_enable, pte.isAf() || bitmap_checkfailed, pte.isAf()) 1191 } else { 1192 pte.isAf() 1193 } 1194 val find_pte = pte.isLeaf() || ppn_af || pageFault 1195 1196 val resp_valid = !idle && mem_addr_update && ((w_mem_resp && find_pte) || (s_pmp_check && accessFault)) 1197 val id = Reg(UInt(log2Up(l2tlbParams.llptwsize).W)) 1198 val source = RegEnable(io.req.bits.source, io.req.fire) 1199 1200 io.req.ready := idle 1201 val resp = Wire(new HptwResp()) 1202 // accessFault > pageFault > ppn_af 1203 resp.apply( 1204 gpf = pageFault && !accessFault, 1205 gaf = accessFault || (ppn_af && !pageFault), 1206 level = Mux(accessFault, af_level, level), 1207 pte = pte, 1208 vpn = vpn, 1209 vmid = hgatp.vmid 1210 ) 1211 io.resp.valid := resp_valid 1212 io.resp.bits.id := id 1213 io.resp.bits.resp := resp 1214 io.resp.bits.source := source 1215 1216 io.pmp.req.valid := DontCare 1217 io.pmp.req.bits.addr := mem_addr 1218 io.pmp.req.bits.size := 3.U 1219 io.pmp.req.bits.cmd := TlbCmd.read 1220 1221 if (HasBitmapCheck) { 1222 val way_info = DataHoldBypass(io.l0_way_info.get, RegNext(io.mem.resp.fire, init=false.B)) 1223 val cache_hitway = RegEnable(io.req.bits.bitmapCheck.get.hitway, io.req.fire) 1224 val cache_level = RegEnable(io.req.bits.bitmapCheck.get.SPlevel, io.req.fire) 1225 io.bitmap.get.req.valid := !s_bitmap_check 1226 io.bitmap.get.req.bits.bmppn := pte.ppn 1227 io.bitmap.get.req.bits.id := HptwReqId.U(bMemID.W) 1228 io.bitmap.get.req.bits.vpn := vpn 1229 io.bitmap.get.req.bits.level := Mux(jmp_bitmap_check, Mux(fromSP,cache_level,0.U), level) 1230 io.bitmap.get.req.bits.way_info := Mux(jmp_bitmap_check, cache_hitway, way_info) 1231 io.bitmap.get.req.bits.hptw_bypassed := bypassed 1232 io.bitmap.get.resp.ready := !w_bitmap_resp 1233 } 1234 1235 io.mem.req.valid := !s_mem_req && !io.mem.mask && !accessFault && s_pmp_check 1236 io.mem.req.bits.addr := mem_addr 1237 io.mem.req.bits.id := HptwReqId.U(bMemID.W) 1238 io.mem.req.bits.hptw_bypassed := bypassed 1239 1240 io.refill.req_info.vpn := vpn 1241 io.refill.level := level 1242 io.refill.req_info.source := source 1243 io.refill.req_info.s2xlate := onlyStage2 1244 1245 when (idle){ 1246 if (HasBitmapCheck) { 1247 when (io.req.bits.bitmapCheck.get.jmp_bitmap_check && io.req.fire) { 1248 idle := false.B 1249 gpaddr := Cat(io.req.bits.gvpn, 0.U(offLen.W)) 1250 s_bitmap_check := false.B 1251 id := io.req.bits.id 1252 level := Mux(io.req.bits.bitmapCheck.get.fromSP, io.req.bits.bitmapCheck.get.SPlevel, 0.U) 1253 } 1254 } 1255 when (io.req.fire && (if (HasBitmapCheck) !io.req.bits.bitmapCheck.get.jmp_bitmap_check else true.B)) { 1256 bypassed := io.req.bits.bypassed 1257 idle := false.B 1258 gpaddr := Cat(io.req.bits.gvpn, 0.U(offLen.W)) 1259 accessFault := false.B 1260 s_pmp_check := false.B 1261 id := io.req.bits.id 1262 req_ppn := io.req.bits.ppn 1263 if (EnableSv48) { 1264 when (mode === Sv48) { 1265 level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, Mux(io.req.bits.l3Hit.get, 2.U, 3.U))) 1266 af_level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, Mux(io.req.bits.l3Hit.get, 2.U, 3.U))) 1267 l3Hit := io.req.bits.l3Hit.get 1268 } .otherwise { 1269 level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, 2.U)) 1270 af_level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, 2.U)) 1271 l3Hit := false.B 1272 } 1273 } else { 1274 level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, 2.U)) 1275 af_level := Mux(io.req.bits.l1Hit, 0.U, Mux(io.req.bits.l2Hit, 1.U, 2.U)) 1276 l3Hit := false.B 1277 } 1278 l2Hit := io.req.bits.l2Hit 1279 l1Hit := io.req.bits.l1Hit 1280 } 1281 } 1282 1283 when(sent_to_pmp && !mem_addr_update){ 1284 s_mem_req := false.B 1285 s_pmp_check := true.B 1286 } 1287 1288 when(accessFault && !idle){ 1289 s_pmp_check := true.B 1290 s_mem_req := true.B 1291 w_mem_resp := true.B 1292 mem_addr_update := true.B 1293 if (HasBitmapCheck) { 1294 s_bitmap_check := true.B 1295 w_bitmap_resp := true.B 1296 whether_need_bitmap_check := false.B 1297 bitmap_checkfailed := false.B 1298 } 1299 } 1300 1301 when(io.mem.req.fire){ 1302 s_mem_req := true.B 1303 w_mem_resp := false.B 1304 } 1305 1306 when(io.mem.resp.fire && !w_mem_resp){ 1307 w_mem_resp := true.B 1308 af_level := af_level - 1.U 1309 if (HasBitmapCheck) { 1310 when (bitmap_enable) { 1311 whether_need_bitmap_check := true.B 1312 } .otherwise { 1313 mem_addr_update := true.B 1314 whether_need_bitmap_check := false.B 1315 } 1316 } else { 1317 mem_addr_update := true.B 1318 } 1319 } 1320 1321 if (HasBitmapCheck) { 1322 when (whether_need_bitmap_check) { 1323 when (bitmap_enable && pte.isLeaf()) { 1324 s_bitmap_check := false.B 1325 whether_need_bitmap_check := false.B 1326 } .otherwise { 1327 mem_addr_update := true.B 1328 whether_need_bitmap_check := false.B 1329 } 1330 } 1331 // bitmapcheck 1332 when (io.bitmap.get.req.fire) { 1333 s_bitmap_check := true.B 1334 w_bitmap_resp := false.B 1335 } 1336 when (io.bitmap.get.resp.fire) { 1337 w_bitmap_resp := true.B 1338 mem_addr_update := true.B 1339 bitmap_checkfailed := io.bitmap.get.resp.bits.cf 1340 } 1341 } 1342 1343 when(mem_addr_update){ 1344 when(!(find_pte || accessFault)){ 1345 level := levelNext 1346 s_mem_req := false.B 1347 mem_addr_update := false.B 1348 }.elsewhen(resp_valid){ 1349 when(io.resp.fire){ 1350 idle := true.B 1351 mem_addr_update := false.B 1352 accessFault := false.B 1353 } 1354 finish := true.B 1355 } 1356 } 1357 when (flush) { 1358 idle := true.B 1359 s_pmp_check := true.B 1360 s_mem_req := true.B 1361 w_mem_resp := true.B 1362 accessFault := false.B 1363 mem_addr_update := false.B 1364 if (HasBitmapCheck) { 1365 s_bitmap_check := true.B 1366 w_bitmap_resp := true.B 1367 whether_need_bitmap_check := false.B 1368 bitmap_checkfailed := false.B 1369 } 1370 } 1371} 1372