1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import chisel3.internal.naming.chiselName 23import xiangshan._ 24import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 25import utils._ 26import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 27import freechips.rocketchip.tilelink._ 28 29/* ptw cache caches the page table of all the three layers 30 * ptw cache resp at next cycle 31 * the cache should not be blocked 32 * when miss queue if full, just block req outside 33 */ 34 35class PageCachePerPespBundle(implicit p: Parameters) extends PtwBundle { 36 val hit = Bool() 37 val pre = Bool() 38 val ppn = UInt(ppnLen.W) 39 val perm = new PtePermBundle() 40 val ecc = Bool() 41 val level = UInt(2.W) 42 43 def apply(hit: Bool, pre: Bool, ppn: UInt, perm: PtePermBundle = 0.U.asTypeOf(new PtePermBundle()), 44 ecc: Bool = false.B, level: UInt = 0.U) { 45 this.hit := hit && !ecc 46 this.pre := pre 47 this.ppn := ppn 48 this.perm := perm 49 this.ecc := ecc && hit 50 this.level := level 51 } 52} 53 54class PageCacheRespBundle(implicit p: Parameters) extends PtwBundle { 55 val l1 = new PageCachePerPespBundle 56 val l2 = new PageCachePerPespBundle 57 val l3 = new PageCachePerPespBundle 58 val sp = new PageCachePerPespBundle 59} 60 61class PtwCacheReq(implicit p: Parameters) extends PtwBundle { 62 val req_info = new L2TlbInnerBundle() 63 val isFirst = Bool() 64} 65 66class PtwCacheIO()(implicit p: Parameters) extends MMUIOBaseBundle with HasPtwConst { 67 val req = Flipped(DecoupledIO(new PtwCacheReq())) 68 val resp = DecoupledIO(new Bundle { 69 val req_info = new L2TlbInnerBundle() 70 val hit = Bool() 71 val prefetch = Bool() // is the entry fetched by prefetch 72 val toFsm = new Bundle { 73 val l1Hit = Bool() 74 val l2Hit = Bool() 75 val ppn = UInt(ppnLen.W) 76 } 77 val toTlb = new PtwEntry(tagLen = vpnLen, hasPerm = true, hasLevel = true) 78 }) 79 val refill = Flipped(ValidIO(new Bundle { 80 val ptes = UInt(blockBits.W) 81 val req_info = new L2TlbInnerBundle() 82 val level = UInt(log2Up(Level).W) 83 val addr_low = UInt((log2Up(l2tlbParams.blockBytes) - log2Up(XLEN/8)).W) 84 })) 85} 86 87@chiselName 88class PtwCache()(implicit p: Parameters) extends XSModule with HasPtwConst { 89 val io = IO(new PtwCacheIO) 90 91 val ecc = Code.fromString(l2tlbParams.ecc) 92 val l2EntryType = new PTWEntriesWithEcc(ecc, num = PtwL2SectorSize, tagLen = PtwL2TagLen, level = 1, hasPerm = false) 93 val l3EntryType = new PTWEntriesWithEcc(ecc, num = PtwL3SectorSize, tagLen = PtwL3TagLen, level = 2, hasPerm = true) 94 95 // TODO: four caches make the codes dirty, think about how to deal with it 96 97 val sfence = io.sfence 98 val refill = io.refill.bits 99 val refill_prefetch = from_pre(io.refill.bits.req_info.source) 100 val flush = sfence.valid || io.csr.satp.changed 101 102 // when refill, refuce to accept new req 103 val rwHarzad = if (sramSinglePort) io.refill.valid else false.B 104 105 // handle hand signal and req_info 106 val stage1 = Wire(Decoupled(new PtwCacheReq())) 107 val stage2 = Wire(Decoupled(new PtwCacheReq())) 108 val stage3 = Wire(Decoupled(new PtwCacheReq())) 109 stage1 <> io.req 110 PipelineConnect(stage1, stage2, stage3.ready, flush, rwHarzad) 111 PipelineConnect(stage2, stage3, io.resp.ready, flush) 112 stage3.ready := io.resp.ready 113 114 // l1: level 0 non-leaf pte 115 val l1 = Reg(Vec(l2tlbParams.l1Size, new PtwEntry(tagLen = PtwL1TagLen))) 116 val l1v = RegInit(0.U(l2tlbParams.l1Size.W)) 117 val l1g = Reg(UInt(l2tlbParams.l1Size.W)) 118 val l1asids = Reg(Vec(l2tlbParams.l1Size, UInt(AsidLength.W))) 119 120 // l2: level 1 non-leaf pte 121 val l2 = Module(new SRAMTemplate( 122 l2EntryType, 123 set = l2tlbParams.l2nSets, 124 way = l2tlbParams.l2nWays, 125 singlePort = sramSinglePort 126 )) 127 val l2v = RegInit(0.U((l2tlbParams.l2nSets * l2tlbParams.l2nWays).W)) 128 val l2g = Reg(UInt((l2tlbParams.l2nSets * l2tlbParams.l2nWays).W)) 129 val l2asids = Reg(Vec(l2tlbParams.l2nSets, Vec(l2tlbParams.l2nWays, UInt(AsidLength.W)))) 130 def getl2vSet(vpn: UInt) = { 131 require(log2Up(l2tlbParams.l2nWays) == log2Down(l2tlbParams.l2nWays)) 132 val set = genPtwL2SetIdx(vpn) 133 require(set.getWidth == log2Up(l2tlbParams.l2nSets)) 134 val l2vVec = l2v.asTypeOf(Vec(l2tlbParams.l2nSets, UInt(l2tlbParams.l2nWays.W))) 135 l2vVec(set) 136 } 137 def getl2asidSet(vpn: UInt) = { 138 require(log2Up(l2tlbParams.l2nWays) == log2Down(l2tlbParams.l2nWays)) 139 val set = genPtwL2SetIdx(vpn) 140 require(set.getWidth == log2Up(l2tlbParams.l2nSets)) 141 l2asids(set) 142 } 143 144 // l3: level 2 leaf pte of 4KB pages 145 val l3 = Module(new SRAMTemplate( 146 l3EntryType, 147 set = l2tlbParams.l3nSets, 148 way = l2tlbParams.l3nWays, 149 singlePort = sramSinglePort 150 )) 151 val l3v = RegInit(0.U((l2tlbParams.l3nSets * l2tlbParams.l3nWays).W)) 152 val l3g = Reg(UInt((l2tlbParams.l3nSets * l2tlbParams.l3nWays).W)) 153 val l3asids = Reg(Vec(l2tlbParams.l3nSets, Vec(l2tlbParams.l3nWays, UInt(AsidLength.W)))) 154 def getl3vSet(vpn: UInt) = { 155 require(log2Up(l2tlbParams.l3nWays) == log2Down(l2tlbParams.l3nWays)) 156 val set = genPtwL3SetIdx(vpn) 157 require(set.getWidth == log2Up(l2tlbParams.l3nSets)) 158 val l3vVec = l3v.asTypeOf(Vec(l2tlbParams.l3nSets, UInt(l2tlbParams.l3nWays.W))) 159 l3vVec(set) 160 } 161 def getl3asidSet(vpn: UInt) = { 162 require(log2Up(l2tlbParams.l3nWays) == log2Down(l2tlbParams.l3nWays)) 163 val set = genPtwL3SetIdx(vpn) 164 require(set.getWidth == log2Up(l2tlbParams.l3nSets)) 165 l3asids(set) 166 } 167 168 // sp: level 0/1 leaf pte of 1GB/2MB super pages 169 val sp = Reg(Vec(l2tlbParams.spSize, new PtwEntry(tagLen = SPTagLen, hasPerm = true, hasLevel = true))) 170 val spv = RegInit(0.U(l2tlbParams.spSize.W)) 171 val spg = Reg(UInt(l2tlbParams.spSize.W)) 172 val spasids = Reg(Vec(l2tlbParams.spSize, UInt(AsidLength.W))) 173 174 // Access Perf 175 val l1AccessPerf = Wire(Vec(l2tlbParams.l1Size, Bool())) 176 val l2AccessPerf = Wire(Vec(l2tlbParams.l2nWays, Bool())) 177 val l3AccessPerf = Wire(Vec(l2tlbParams.l3nWays, Bool())) 178 val spAccessPerf = Wire(Vec(l2tlbParams.spSize, Bool())) 179 l1AccessPerf.map(_ := false.B) 180 l2AccessPerf.map(_ := false.B) 181 l3AccessPerf.map(_ := false.B) 182 spAccessPerf.map(_ := false.B) 183 184 // stage1 & stage2, read page cache and data resp 185 186 val cache_read_valid = OneCycleValid(stage1.fire, flush) 187 // l1 188 val ptwl1replace = ReplacementPolicy.fromString(l2tlbParams.l1Replacer, l2tlbParams.l1Size) 189 val (l1Hit, l1HitPPN, l1Pre) = { 190 val hitVecT = l1.zipWithIndex.map { case (e, i) => e.hit(stage1.bits.req_info.vpn, io.csr.satp.asid) && l1v(i) } 191 val hitVec = hitVecT.map(RegEnable(_, stage1.fire)) 192 val hitPPN = ParallelPriorityMux(hitVec zip l1.map(_.ppn)) 193 val hitPre = ParallelPriorityMux(hitVec zip l1.map(_.prefetch)) 194 val hit = ParallelOR(hitVec) && cache_read_valid 195 196 when (hit) { ptwl1replace.access(OHToUInt(hitVec)) } 197 198 l1AccessPerf.zip(hitVec).map{ case (l, h) => l := h && RegNext(stage1.fire)} 199 for (i <- 0 until l2tlbParams.l1Size) { 200 XSDebug(stage1.fire, p"[l1] l1(${i.U}) ${l1(i)} hit:${l1(i).hit(stage1.bits.req_info.vpn, io.csr.satp.asid)}\n") 201 } 202 XSDebug(stage1.fire, p"[l1] l1v:${Binary(l1v)} hitVecT:${Binary(VecInit(hitVecT).asUInt)}\n") 203 XSDebug(stage2.valid, p"[l1] l1Hit:${hit} l1HitPPN:0x${Hexadecimal(hitPPN)} hitVec:${VecInit(hitVec).asUInt}\n") 204 205 VecInit(hitVecT).suggestName(s"l1_hitVecT") 206 VecInit(hitVec).suggestName(s"l1_hitVec") 207 208 (hit, hitPPN, hitPre) 209 } 210 211 // l2 212 val ptwl2replace = ReplacementPolicy.fromString(l2tlbParams.l2Replacer,l2tlbParams.l2nWays,l2tlbParams.l2nSets) 213 val (l2Hit, l2HitPPN, l2Pre, l2eccError) = { 214 val ridx = genPtwL2SetIdx(stage1.bits.req_info.vpn) 215 val vidx = RegEnable(VecInit(getl2vSet(stage1.bits.req_info.vpn).asBools), stage1.fire) 216 val asids_idx = RegEnable(getl2asidSet(stage1.bits.req_info.vpn), stage1.fire) 217 l2.io.r.req.valid := stage1.fire 218 l2.io.r.req.bits.apply(setIdx = ridx) 219 val ramDatas = l2.io.r.resp.data 220 val hitVec = VecInit(ramDatas.zip(vidx).map { case (wayData, v) => wayData.entries.hit(stage2.bits.req_info.vpn, io.csr.satp.asid) && v }) 221 val hitWayEntry = ParallelPriorityMux(hitVec zip ramDatas) 222 val hitWayData = hitWayEntry.entries 223 val hit = ParallelOR(hitVec) && cache_read_valid && RegNext(l2.io.r.req.ready, init = false.B) 224 val hitWay = ParallelPriorityMux(hitVec zip (0 until l2tlbParams.l2nWays).map(_.U)) 225 val eccError = hitWayEntry.decode() 226 227 ridx.suggestName(s"l2_ridx") 228 vidx.suggestName(s"l2_vidx") 229 ramDatas.suggestName(s"l2_ramDatas") 230 hitVec.suggestName(s"l2_hitVec") 231 hitWayData.suggestName(s"l2_hitWayData") 232 hitWay.suggestName(s"l2_hitWay") 233 234 when (hit) { ptwl2replace.access(genPtwL2SetIdx(stage2.bits.req_info.vpn), hitWay) } 235 236 l2AccessPerf.zip(hitVec).map{ case (l, h) => l := h && RegNext(stage1.fire) } 237 XSDebug(stage1.fire, p"[l2] ridx:0x${Hexadecimal(ridx)}\n") 238 for (i <- 0 until l2tlbParams.l2nWays) { 239 XSDebug(RegNext(stage1.fire), p"[l2] ramDatas(${i.U}) ${ramDatas(i)} l2v:${vidx(i)} hit:${ramDatas(i).entries.hit(stage2.bits.req_info.vpn, io.csr.satp.asid)}\n") 240 } 241 XSDebug(stage2.valid, p"[l2] l2Hit:${hit} l2HitPPN:0x${Hexadecimal(hitWayData.ppns(genPtwL2SectorIdx(stage2.bits.req_info.vpn)))} hitVec:${Binary(hitVec.asUInt)} hitWay:${hitWay} vidx:${Binary(vidx.asUInt)}\n") 242 243 (hit, hitWayData.ppns(genPtwL2SectorIdx(stage2.bits.req_info.vpn)), hitWayData.prefetch, eccError) 244 } 245 246 // l3 247 val ptwl3replace = ReplacementPolicy.fromString(l2tlbParams.l3Replacer,l2tlbParams.l3nWays,l2tlbParams.l3nSets) 248 val (l3Hit, l3HitData, l3Pre, l3eccError) = { 249 val ridx = genPtwL3SetIdx(stage1.bits.req_info.vpn) 250 val vidx = RegEnable(VecInit(getl3vSet(stage1.bits.req_info.vpn).asBools), stage1.fire) 251 val asids_idx = RegEnable(getl3asidSet(stage1.bits.req_info.vpn), stage1.fire) 252 l3.io.r.req.valid := stage1.fire 253 l3.io.r.req.bits.apply(setIdx = ridx) 254 val ramDatas = l3.io.r.resp.data 255 val hitVec = VecInit(ramDatas.zip(vidx).map{ case (wayData, v) => wayData.entries.hit(stage2.bits.req_info.vpn, io.csr.satp.asid) && v }) 256 val hitWayEntry = ParallelPriorityMux(hitVec zip ramDatas) 257 val hitWayData = hitWayEntry.entries 258 val hitWayEcc = hitWayEntry.ecc 259 val hit = ParallelOR(hitVec) && cache_read_valid && RegNext(l3.io.r.req.ready, init = false.B) 260 val hitWay = ParallelPriorityMux(hitVec zip (0 until l2tlbParams.l3nWays).map(_.U)) 261 val eccError = hitWayEntry.decode() 262 263 when (hit) { ptwl3replace.access(genPtwL3SetIdx(stage2.bits.req_info.vpn), hitWay) } 264 265 l3AccessPerf.zip(hitVec).map{ case (l, h) => l := h && RegNext(stage1.fire) } 266 XSDebug(stage1.fire, p"[l3] ridx:0x${Hexadecimal(ridx)}\n") 267 for (i <- 0 until l2tlbParams.l3nWays) { 268 XSDebug(RegNext(stage1.fire), p"[l3] ramDatas(${i.U}) ${ramDatas(i)} l3v:${vidx(i)} hit:${ramDatas(i).entries.hit(stage2.bits.req_info.vpn, io.csr.satp.asid)}\n") 269 } 270 XSDebug(stage2.valid, p"[l3] l3Hit:${hit} l3HitData:${hitWayData} hitVec:${Binary(hitVec.asUInt)} hitWay:${hitWay} vidx:${Binary(vidx.asUInt)}\n") 271 272 ridx.suggestName(s"l3_ridx") 273 vidx.suggestName(s"l3_vidx") 274 ramDatas.suggestName(s"l3_ramDatas") 275 hitVec.suggestName(s"l3_hitVec") 276 hitWay.suggestName(s"l3_hitWay") 277 278 (hit, hitWayData, hitWayData.prefetch, eccError) 279 } 280 val l3HitPPN = l3HitData.ppns(genPtwL3SectorIdx(stage2.bits.req_info.vpn)) 281 val l3HitPerm = l3HitData.perms.getOrElse(0.U.asTypeOf(Vec(PtwL3SectorSize, new PtePermBundle)))(genPtwL3SectorIdx(stage2.bits.req_info.vpn)) 282 283 // super page 284 val spreplace = ReplacementPolicy.fromString(l2tlbParams.spReplacer, l2tlbParams.spSize) 285 val (spHit, spHitData, spPre) = { 286 val hitVecT = sp.zipWithIndex.map { case (e, i) => e.hit(stage1.bits.req_info.vpn, io.csr.satp.asid) && spv(i) } 287 val hitVec = hitVecT.map(RegEnable(_, stage1.fire)) 288 val hitData = ParallelPriorityMux(hitVec zip sp) 289 val hit = ParallelOR(hitVec) && cache_read_valid 290 291 when (hit) { spreplace.access(OHToUInt(hitVec)) } 292 293 spAccessPerf.zip(hitVec).map{ case (s, h) => s := h && RegNext(stage1.fire) } 294 for (i <- 0 until l2tlbParams.spSize) { 295 XSDebug(stage1.fire, p"[sp] sp(${i.U}) ${sp(i)} hit:${sp(i).hit(stage1.bits.req_info.vpn, io.csr.satp.asid)} spv:${spv(i)}\n") 296 } 297 XSDebug(stage2.valid, p"[sp] spHit:${hit} spHitData:${hitData} hitVec:${Binary(VecInit(hitVec).asUInt)}\n") 298 299 VecInit(hitVecT).suggestName(s"sp_hitVecT") 300 VecInit(hitVec).suggestName(s"sp_hitVec") 301 302 (hit, hitData, hitData.prefetch) 303 } 304 val spHitPerm = spHitData.perm.getOrElse(0.U.asTypeOf(new PtePermBundle)) 305 val spHitLevel = spHitData.level.getOrElse(0.U) 306 307 val s2_res = Wire(new PageCacheRespBundle) 308 s2_res.l1.apply(l1Hit, l1Pre, l1HitPPN) 309 s2_res.l2.apply(l2Hit, l2Pre, l2HitPPN, ecc = l2eccError) 310 s2_res.l3.apply(l3Hit, l3Pre, l3HitPPN, l3HitPerm, l3eccError) 311 s2_res.sp.apply(spHit, spPre, spHitData.ppn, spHitPerm, false.B, spHitLevel) 312 val s2_res_reg = DataHoldBypass(s2_res, RegNext(stage1.fire())) 313 314 // stage3, add stage 3 for ecc check... 315 val s3_res = Reg(new PageCacheRespBundle) 316 when (stage2.fire()) { 317 s3_res := s2_res_reg 318 } 319 320 io.resp.bits.req_info := stage3.bits.req_info 321 io.resp.bits.hit := s3_res.l3.hit || s3_res.sp.hit 322 io.resp.bits.prefetch := s3_res.l3.pre && s3_res.l3.hit || s3_res.sp.pre && s3_res.sp.hit 323 io.resp.bits.toFsm.l1Hit := s3_res.l1.hit 324 io.resp.bits.toFsm.l2Hit := s3_res.l2.hit 325 io.resp.bits.toFsm.ppn := Mux(s3_res.l2.hit, s3_res.l2.ppn, s3_res.l1.ppn) 326 io.resp.bits.toTlb.tag := stage3.bits.req_info.vpn 327 io.resp.bits.toTlb.asid := io.csr.satp.asid // DontCare 328 io.resp.bits.toTlb.ppn := Mux(s3_res.l3.hit, s3_res.l3.ppn, s3_res.sp.ppn) 329 io.resp.bits.toTlb.perm.map(_ := Mux(s3_res.l3.hit, s3_res.l3.perm, s3_res.sp.perm)) 330 io.resp.bits.toTlb.level.map(_ := Mux(s3_res.l3.hit, 2.U, s3_res.sp.level)) 331 io.resp.bits.toTlb.prefetch := from_pre(stage3.bits.req_info.source) 332 io.resp.valid := stage3.valid 333 assert(!(l3Hit && spHit), "normal page and super page both hit") 334 335 // refill Perf 336 val l1RefillPerf = Wire(Vec(l2tlbParams.l1Size, Bool())) 337 val l2RefillPerf = Wire(Vec(l2tlbParams.l2nWays, Bool())) 338 val l3RefillPerf = Wire(Vec(l2tlbParams.l3nWays, Bool())) 339 val spRefillPerf = Wire(Vec(l2tlbParams.spSize, Bool())) 340 l1RefillPerf.map(_ := false.B) 341 l2RefillPerf.map(_ := false.B) 342 l3RefillPerf.map(_ := false.B) 343 spRefillPerf.map(_ := false.B) 344 345 // refill 346 l2.io.w.req <> DontCare 347 l3.io.w.req <> DontCare 348 l2.io.w.req.valid := false.B 349 l3.io.w.req.valid := false.B 350 351 def get_part(data: UInt, index: UInt): UInt = { 352 val inner_data = data.asTypeOf(Vec(data.getWidth / XLEN, UInt(XLEN.W))) 353 inner_data(index) 354 } 355 356 val memRdata = refill.ptes 357 val memSelData = get_part(memRdata, refill.addr_low) 358 val memPtes = (0 until (l2tlbParams.blockBytes/(XLEN/8))).map(i => memRdata((i+1)*XLEN-1, i*XLEN).asTypeOf(new PteBundle)) 359 val memPte = memSelData.asTypeOf(new PteBundle) 360 361 memPte.suggestName("memPte") 362 363 // TODO: handle sfenceLatch outsize 364 when (io.refill.valid && !memPte.isPf(refill.level) && !flush ) { 365 when (refill.level === 0.U && !memPte.isLeaf()) { 366 // val refillIdx = LFSR64()(log2Up(l2tlbParams.l1Size)-1,0) // TODO: may be LRU 367 val refillIdx = replaceWrapper(l1v, ptwl1replace.way) 368 refillIdx.suggestName(s"PtwL1RefillIdx") 369 val rfOH = UIntToOH(refillIdx) 370 l1(refillIdx).refill( 371 refill.req_info.vpn, 372 io.csr.satp.asid, 373 memSelData, 374 0.U, 375 refill_prefetch 376 ) 377 ptwl1replace.access(refillIdx) 378 l1v := l1v | rfOH 379 l1g := (l1g & ~rfOH) | Mux(memPte.perm.g, rfOH, 0.U) 380 381 for (i <- 0 until l2tlbParams.l1Size) { 382 l1RefillPerf(i) := i.U === refillIdx 383 } 384 385 XSDebug(p"[l1 refill] refillIdx:${refillIdx} refillEntry:${l1(refillIdx).genPtwEntry(refill.req_info.vpn, io.csr.satp.asid, memSelData, 0.U, refill_prefetch)}\n") 386 XSDebug(p"[l1 refill] l1v:${Binary(l1v)}->${Binary(l1v | rfOH)} l1g:${Binary(l1g)}->${Binary((l1g & ~rfOH) | Mux(memPte.perm.g, rfOH, 0.U))}\n") 387 388 refillIdx.suggestName(s"l1_refillIdx") 389 rfOH.suggestName(s"l1_rfOH") 390 } 391 392 when (refill.level === 1.U && !memPte.isLeaf()) { 393 val refillIdx = genPtwL2SetIdx(refill.req_info.vpn) 394 val victimWay = replaceWrapper(RegEnable(VecInit(getl2vSet(refill.req_info.vpn).asBools).asUInt, stage1.fire), ptwl2replace.way(refillIdx)) 395 val victimWayOH = UIntToOH(victimWay) 396 val rfvOH = UIntToOH(Cat(refillIdx, victimWay)) 397 val wdata = Wire(l2EntryType) 398 wdata.gen( 399 vpn = refill.req_info.vpn, 400 asid = io.csr.satp.asid, 401 data = memRdata, 402 levelUInt = 1.U, 403 refill_prefetch 404 ) 405 l2.io.w.apply( 406 valid = true.B, 407 setIdx = refillIdx, 408 data = wdata, 409 waymask = victimWayOH 410 ) 411 ptwl2replace.access(refillIdx, victimWay) 412 l2v := l2v | rfvOH 413 l2g := l2g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U) 414 415 for (i <- 0 until l2tlbParams.l2nWays) { 416 l2RefillPerf(i) := i.U === victimWay 417 } 418 419 XSDebug(p"[l2 refill] refillIdx:0x${Hexadecimal(refillIdx)} victimWay:${victimWay} victimWayOH:${Binary(victimWayOH)} rfvOH(in UInt):${Cat(refillIdx, victimWay)}\n") 420 XSDebug(p"[l2 refill] refilldata:0x${wdata}\n") 421 XSDebug(p"[l2 refill] l2v:${Binary(l2v)} -> ${Binary(l2v | rfvOH)}\n") 422 XSDebug(p"[l2 refill] l2g:${Binary(l2g)} -> ${Binary(l2g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U))}\n") 423 424 refillIdx.suggestName(s"l2_refillIdx") 425 victimWay.suggestName(s"l2_victimWay") 426 victimWayOH.suggestName(s"l2_victimWayOH") 427 rfvOH.suggestName(s"l2_rfvOH") 428 } 429 430 when (refill.level === 2.U && memPte.isLeaf()) { 431 val refillIdx = genPtwL3SetIdx(refill.req_info.vpn) 432 val victimWay = replaceWrapper(RegEnable(VecInit(getl3vSet(refill.req_info.vpn).asBools).asUInt, stage1.fire), ptwl3replace.way(refillIdx)) 433 val victimWayOH = UIntToOH(victimWay) 434 val rfvOH = UIntToOH(Cat(refillIdx, victimWay)) 435 val wdata = Wire(l3EntryType) 436 wdata.gen( 437 vpn = refill.req_info.vpn, 438 asid = io.csr.satp.asid, 439 data = memRdata, 440 levelUInt = 2.U, 441 refill_prefetch 442 ) 443 l3.io.w.apply( 444 valid = true.B, 445 setIdx = refillIdx, 446 data = wdata, 447 waymask = victimWayOH 448 ) 449 ptwl3replace.access(refillIdx, victimWay) 450 l3v := l3v | rfvOH 451 l3g := l3g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U) 452 453 for (i <- 0 until l2tlbParams.l3nWays) { 454 l3RefillPerf(i) := i.U === victimWay 455 } 456 457 XSDebug(p"[l3 refill] refillIdx:0x${Hexadecimal(refillIdx)} victimWay:${victimWay} victimWayOH:${Binary(victimWayOH)} rfvOH(in UInt):${Cat(refillIdx, victimWay)}\n") 458 XSDebug(p"[l3 refill] refilldata:0x${wdata}\n") 459 XSDebug(p"[l3 refill] l3v:${Binary(l3v)} -> ${Binary(l3v | rfvOH)}\n") 460 XSDebug(p"[l3 refill] l3g:${Binary(l3g)} -> ${Binary(l3g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U))}\n") 461 462 refillIdx.suggestName(s"l3_refillIdx") 463 victimWay.suggestName(s"l3_victimWay") 464 victimWayOH.suggestName(s"l3_victimWayOH") 465 rfvOH.suggestName(s"l3_rfvOH") 466 } 467 when ((refill.level === 0.U || refill.level === 1.U) && memPte.isLeaf()) { 468 val refillIdx = spreplace.way// LFSR64()(log2Up(l2tlbParams.spSize)-1,0) // TODO: may be LRU 469 val rfOH = UIntToOH(refillIdx) 470 sp(refillIdx).refill( 471 refill.req_info.vpn, 472 io.csr.satp.asid, 473 memSelData, 474 refill.level, 475 refill_prefetch 476 ) 477 spreplace.access(refillIdx) 478 spv := spv | rfOH 479 spg := spg & ~rfOH | Mux(memPte.perm.g, rfOH, 0.U) 480 481 for (i <- 0 until l2tlbParams.spSize) { 482 spRefillPerf(i) := i.U === refillIdx 483 } 484 485 XSDebug(p"[sp refill] refillIdx:${refillIdx} refillEntry:${sp(refillIdx).genPtwEntry(refill.req_info.vpn, io.csr.satp.asid, memSelData, refill.level, refill_prefetch)}\n") 486 XSDebug(p"[sp refill] spv:${Binary(spv)}->${Binary(spv | rfOH)} spg:${Binary(spg)}->${Binary(spg & ~rfOH | Mux(memPte.perm.g, rfOH, 0.U))}\n") 487 488 refillIdx.suggestName(s"sp_refillIdx") 489 rfOH.suggestName(s"sp_rfOH") 490 } 491 } 492 493 val l2eccFlush = s3_res.l2.ecc && stage3.fire() // RegNext(l2eccError, init = false.B) 494 val l3eccFlush = s3_res.l3.ecc && stage3.fire() // RegNext(l3eccError, init = false.B) 495 val eccVpn = stage3.bits.req_info.vpn 496 497 assert(!l2eccFlush) 498 assert(!l3eccFlush) 499 when (l2eccFlush) { 500 val flushSetIdxOH = UIntToOH(genPtwL2SetIdx(eccVpn)) 501 val flushMask = VecInit(flushSetIdxOH.asBools.map { a => Fill(l2tlbParams.l2nWays, a.asUInt) }).asUInt 502 l2v := l2v & ~flushMask 503 l2g := l2g & ~flushMask 504 } 505 506 when (l3eccFlush) { 507 val flushSetIdxOH = UIntToOH(genPtwL3SetIdx(eccVpn)) 508 val flushMask = VecInit(flushSetIdxOH.asBools.map { a => Fill(l2tlbParams.l3nWays, a.asUInt) }).asUInt 509 l3v := l3v & ~flushMask 510 l3g := l3g & ~flushMask 511 } 512 513 // sfence 514 when (sfence.valid) { 515 val l1asidhit = VecInit(l1asids.map(_ === sfence.bits.asid)).asUInt 516 val spasidhit = VecInit(spasids.map(_ === sfence.bits.asid)).asUInt 517 val sfence_vpn = sfence.bits.addr(sfence.bits.addr.getWidth-1, offLen) 518 519 when (sfence.bits.rs1/*va*/) { 520 when (sfence.bits.rs2) { 521 // all va && all asid 522 l1v := 0.U 523 l2v := 0.U 524 l3v := 0.U 525 spv := 0.U 526 } .otherwise { 527 // all va && specific asid except global 528 529 l1v := l1v & (~l1asidhit | l1g) 530 l2v := l2v & l2g 531 l3v := l3v & l3g 532 spv := spv & (~spasidhit | spg) 533 } 534 } .otherwise { 535 // val flushMask = UIntToOH(genTlbL2Idx(sfence.bits.addr(sfence.bits.addr.getWidth-1, offLen))) 536 val flushSetIdxOH = UIntToOH(genPtwL3SetIdx(sfence_vpn)) 537 // val flushMask = VecInit(flushSetIdxOH.asBools.map(Fill(l2tlbParams.l3nWays, _.asUInt))).asUInt 538 val flushMask = VecInit(flushSetIdxOH.asBools.map { a => Fill(l2tlbParams.l3nWays, a.asUInt) }).asUInt 539 flushSetIdxOH.suggestName(s"sfence_nrs1_flushSetIdxOH") 540 flushMask.suggestName(s"sfence_nrs1_flushMask") 541 542 when (sfence.bits.rs2) { 543 // specific leaf of addr && all asid 544 l3v := l3v & ~flushMask 545 spv := spv & (~VecInit(sp.map(_.hit(sfence_vpn, sfence.bits.asid, ignoreAsid = true))).asUInt | spg) 546 } .otherwise { 547 // specific leaf of addr && specific asid 548 l3v := l3v & (~flushMask | l3g) 549 spv := spv & (~VecInit(sp.map(_.hit(sfence_vpn, sfence.bits.asid))).asUInt | spg) 550 } 551 } 552 } 553 554 // Perf Count 555 val resp_l3 = s3_res.l3.hit 556 val resp_sp = s3_res.sp.hit 557 val resp_l1_pre = s3_res.l1.pre 558 val resp_l2_pre = s3_res.l2.pre 559 val resp_l3_pre = s3_res.l3.pre 560 val resp_sp_pre = s3_res.sp.pre 561 val base_valid_access_0 = !from_pre(io.resp.bits.req_info.source) && io.resp.fire() 562 XSPerfAccumulate("access", base_valid_access_0) 563 XSPerfAccumulate("l1_hit", base_valid_access_0 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 564 XSPerfAccumulate("l2_hit", base_valid_access_0 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 565 XSPerfAccumulate("l3_hit", base_valid_access_0 && resp_l3) 566 XSPerfAccumulate("sp_hit", base_valid_access_0 && resp_sp) 567 XSPerfAccumulate("pte_hit",base_valid_access_0 && io.resp.bits.hit) 568 569 XSPerfAccumulate("l1_hit_pre", base_valid_access_0 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 570 XSPerfAccumulate("l2_hit_pre", base_valid_access_0 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 571 XSPerfAccumulate("l3_hit_pre", base_valid_access_0 && resp_l3_pre && resp_l3) 572 XSPerfAccumulate("sp_hit_pre", base_valid_access_0 && resp_sp_pre && resp_sp) 573 XSPerfAccumulate("pte_hit_pre",base_valid_access_0 && (resp_l3_pre && resp_l3 || resp_sp_pre && resp_sp) && io.resp.bits.hit) 574 575 val base_valid_access_1 = from_pre(io.resp.bits.req_info.source) && io.resp.fire() 576 XSPerfAccumulate("pre_access", base_valid_access_1) 577 XSPerfAccumulate("pre_l1_hit", base_valid_access_1 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 578 XSPerfAccumulate("pre_l2_hit", base_valid_access_1 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 579 XSPerfAccumulate("pre_l3_hit", base_valid_access_1 && resp_l3) 580 XSPerfAccumulate("pre_sp_hit", base_valid_access_1 && resp_sp) 581 XSPerfAccumulate("pre_pte_hit",base_valid_access_1 && io.resp.bits.hit) 582 583 XSPerfAccumulate("pre_l1_hit_pre", base_valid_access_1 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 584 XSPerfAccumulate("pre_l2_hit_pre", base_valid_access_1 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 585 XSPerfAccumulate("pre_l3_hit_pre", base_valid_access_1 && resp_l3_pre && resp_l3) 586 XSPerfAccumulate("pre_sp_hit_pre", base_valid_access_1 && resp_sp_pre && resp_sp) 587 XSPerfAccumulate("pre_pte_hit_pre",base_valid_access_1 && (resp_l3_pre && resp_l3 || resp_sp_pre && resp_sp) && io.resp.bits.hit) 588 589 val base_valid_access_2 = stage3.bits.isFirst && !from_pre(io.resp.bits.req_info.source) && io.resp.fire() 590 XSPerfAccumulate("access_first", base_valid_access_2) 591 XSPerfAccumulate("l1_hit_first", base_valid_access_2 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 592 XSPerfAccumulate("l2_hit_first", base_valid_access_2 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 593 XSPerfAccumulate("l3_hit_first", base_valid_access_2 && resp_l3) 594 XSPerfAccumulate("sp_hit_first", base_valid_access_2 && resp_sp) 595 XSPerfAccumulate("pte_hit_first",base_valid_access_2 && io.resp.bits.hit) 596 597 XSPerfAccumulate("l1_hit_pre_first", base_valid_access_2 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 598 XSPerfAccumulate("l2_hit_pre_first", base_valid_access_2 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 599 XSPerfAccumulate("l3_hit_pre_first", base_valid_access_2 && resp_l3_pre && resp_l3) 600 XSPerfAccumulate("sp_hit_pre_first", base_valid_access_2 && resp_sp_pre && resp_sp) 601 XSPerfAccumulate("pte_hit_pre_first",base_valid_access_2 && (resp_l3_pre && resp_l3 || resp_sp_pre && resp_sp) && io.resp.bits.hit) 602 603 val base_valid_access_3 = stage3.bits.isFirst && from_pre(io.resp.bits.req_info.source) && io.resp.fire() 604 XSPerfAccumulate("pre_access_first", base_valid_access_3) 605 XSPerfAccumulate("pre_l1_hit_first", base_valid_access_3 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 606 XSPerfAccumulate("pre_l2_hit_first", base_valid_access_3 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 607 XSPerfAccumulate("pre_l3_hit_first", base_valid_access_3 && resp_l3) 608 XSPerfAccumulate("pre_sp_hit_first", base_valid_access_3 && resp_sp) 609 XSPerfAccumulate("pre_pte_hit_first", base_valid_access_3 && io.resp.bits.hit) 610 611 XSPerfAccumulate("pre_l1_hit_pre_first", base_valid_access_3 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 612 XSPerfAccumulate("pre_l2_hit_pre_first", base_valid_access_3 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 613 XSPerfAccumulate("pre_l3_hit_pre_first", base_valid_access_3 && resp_l3_pre && resp_l3) 614 XSPerfAccumulate("pre_sp_hit_pre_first", base_valid_access_3 && resp_sp_pre && resp_sp) 615 XSPerfAccumulate("pre_pte_hit_pre_first",base_valid_access_3 && (resp_l3_pre && resp_l3 || resp_sp_pre && resp_sp) && io.resp.bits.hit) 616 617 XSPerfAccumulate("rwHarzad", io.req.valid && !io.req.ready) 618 XSPerfAccumulate("out_blocked", io.resp.valid && !io.resp.ready) 619 l1AccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L1AccessIndex${i}", l) } 620 l2AccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L2AccessIndex${i}", l) } 621 l3AccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L3AccessIndex${i}", l) } 622 spAccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"SPAccessIndex${i}", l) } 623 l1RefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L1RefillIndex${i}", l) } 624 l2RefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L2RefillIndex${i}", l) } 625 l3RefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L3RefillIndex${i}", l) } 626 spRefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"SPRefillIndex${i}", l) } 627 628 XSPerfAccumulate("l1Refill", Cat(l1RefillPerf).orR) 629 XSPerfAccumulate("l2Refill", Cat(l2RefillPerf).orR) 630 XSPerfAccumulate("l3Refill", Cat(l3RefillPerf).orR) 631 XSPerfAccumulate("spRefill", Cat(spRefillPerf).orR) 632 XSPerfAccumulate("l1Refill_pre", Cat(l1RefillPerf).orR && refill_prefetch) 633 XSPerfAccumulate("l2Refill_pre", Cat(l2RefillPerf).orR && refill_prefetch) 634 XSPerfAccumulate("l3Refill_pre", Cat(l3RefillPerf).orR && refill_prefetch) 635 XSPerfAccumulate("spRefill_pre", Cat(spRefillPerf).orR && refill_prefetch) 636 637 // debug 638 XSDebug(sfence.valid, p"[sfence] original v and g vector:\n") 639 XSDebug(sfence.valid, p"[sfence] l1v:${Binary(l1v)}\n") 640 XSDebug(sfence.valid, p"[sfence] l2v:${Binary(l2v)}\n") 641 XSDebug(sfence.valid, p"[sfence] l3v:${Binary(l3v)}\n") 642 XSDebug(sfence.valid, p"[sfence] l3g:${Binary(l3g)}\n") 643 XSDebug(sfence.valid, p"[sfence] spv:${Binary(spv)}\n") 644 XSDebug(RegNext(sfence.valid), p"[sfence] new v and g vector:\n") 645 XSDebug(RegNext(sfence.valid), p"[sfence] l1v:${Binary(l1v)}\n") 646 XSDebug(RegNext(sfence.valid), p"[sfence] l2v:${Binary(l2v)}\n") 647 XSDebug(RegNext(sfence.valid), p"[sfence] l3v:${Binary(l3v)}\n") 648 XSDebug(RegNext(sfence.valid), p"[sfence] l3g:${Binary(l3g)}\n") 649 XSDebug(RegNext(sfence.valid), p"[sfence] spv:${Binary(spv)}\n") 650 651 val perfinfo = IO(new Bundle(){ 652 val perfEvents = Output(new PerfEventsBundle(8)) 653 }) 654 val perfEvents = Seq( 655 ("access ", base_valid_access_0 ), 656 ("l1_hit ", l1Hit ), 657 ("l2_hit ", l2Hit ), 658 ("l3_hit ", l3Hit ), 659 ("sp_hit ", spHit ), 660 ("pte_hit ", l3Hit || spHit ), 661 ("rwHarzad ", io.req.valid && !io.req.ready ), 662 ("out_blocked ", io.resp.valid && !io.resp.ready), 663 ) 664 665 for (((perf_out,(perf_name,perf)),i) <- perfinfo.perfEvents.perf_events.zip(perfEvents).zipWithIndex) { 666 perf_out.incr_step := RegNext(perf) 667 } 668} 669