1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: 9* http://license.coscl.org.cn/MulanPSL2 10* 11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14* 15* See the Mulan PSL v2 for more details. 16***************************************************************************************/ 17 18package xiangshan.cache.mmu 19 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import xiangshan._ 24import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 25import utils._ 26import utility._ 27import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 28import freechips.rocketchip.tilelink._ 29 30 31case class TLBParameters 32( 33 name: String = "none", 34 fetchi: Boolean = false, // TODO: remove it 35 fenceDelay: Int = 2, 36 useDmode: Boolean = true, 37 NSets: Int = 1, 38 NWays: Int = 2, 39 Replacer: Option[String] = Some("plru"), 40 Associative: String = "fa", // must be fa 41 outReplace: Boolean = false, 42 partialStaticPMP: Boolean = false, // partial static pmp result stored in entries 43 outsideRecvFlush: Boolean = false, // if outside moudle waiting for tlb recv flush pipe 44 saveLevel: Boolean = false, 45 lgMaxSize: Int = 3 46) 47 48case class L2TLBParameters 49( 50 name: String = "l2tlb", 51 // l3 52 l3Size: Int = 16, 53 l3Associative: String = "fa", 54 l3Replacer: Option[String] = Some("plru"), 55 // l2 56 l2Size: Int = 16, 57 l2Associative: String = "fa", 58 l2Replacer: Option[String] = Some("plru"), 59 // l1 60 l1nSets: Int = 8, 61 l1nWays: Int = 4, 62 l1ReservedBits: Int = 10, 63 l1Replacer: Option[String] = Some("setplru"), 64 // l0 65 l0nSets: Int = 32, 66 l0nWays: Int = 8, 67 l0ReservedBits: Int = 3, 68 l0Replacer: Option[String] = Some("setplru"), 69 // sp 70 spSize: Int = 16, 71 spReplacer: Option[String] = Some("plru"), 72 // filter 73 ifilterSize: Int = 8, 74 dfilterSize: Int = 32, 75 // miss queue, add more entries than 'must require' 76 // 0 for easier bug trigger, please set as big as u can, 8 maybe 77 missqueueExtendSize: Int = 0, 78 // llptw 79 llptwsize: Int = 6, 80 // way size 81 blockBytes: Int = 64, 82 // prefetch 83 enablePrefetch: Boolean = true, 84 // ecc 85 ecc: Option[String] = Some("secded"), 86 // enable ecc 87 enablePTWECC: Boolean = false 88) 89 90trait HasTlbConst extends HasXSParameter { 91 val Level = if (EnableSv48) 3 else 2 92 93 val offLen = 12 94 val ppnLen = PAddrBits - offLen 95 val vpnnLen = 9 96 val extendVpnnBits = if (HasHExtension) 2 else 0 97 val vpnLen = VAddrBits - offLen // when opening H extention, vpnlen broaden two bits 98 /* 99 Sv39 page table entry 100 +--+------+--------+----------------------+-----+--------+ 101 |63|62 61|60 54|53 10|9 8|7 0| 102 +--+------+--------+----------------------+-----+--------+ 103 |N | PBMT |Reserved| PPNs | RSW | FALG | 104 +--+------+--------+----------------------+-----+--------+ 105 */ 106 val pteFlagLen = 8 107 val pteRswLen = 2 108 val ptePPNLen = 44 109 val pteResLen = 7 110 val ptePbmtLen = 2 111 val pteNLen = 1 112 val ppnHignLen = ptePPNLen - ppnLen 113 val gvpnLen = GPAddrBits - offLen 114 115 val tlbcontiguous = 8 116 val sectortlbwidth = log2Up(tlbcontiguous) 117 val sectorppnLen = ppnLen - sectortlbwidth 118 val sectorgvpnLen = gvpnLen - sectortlbwidth 119 val sectorvpnLen = vpnLen - sectortlbwidth 120 val sectorptePPNLen = ptePPNLen - sectortlbwidth 121 122 val loadfiltersize = 16 // 4*3(LduCnt:2 + HyuCnt:1) + 4(prefetch:1) 123 val storefiltersize = if (StorePipelineWidth >= 3) 16 else 8 124 val prefetchfiltersize = 8 125 126 val sramSinglePort = true 127 128 val timeOutThreshold = 100000 129 130 def noS2xlate = "b00".U 131 def allStage = "b11".U 132 def onlyStage1 = "b01".U 133 def onlyStage2 = "b10".U 134 135 def Sv39 = "h8".U 136 def Sv48 = "h9".U 137 138 def Sv39x4 = "h8".U 139 def Sv48x4 = "h9".U 140 141 def get_pn(addr: UInt) = { 142 require(addr.getWidth > offLen) 143 addr(addr.getWidth-1, offLen) 144 } 145 def get_off(addr: UInt) = { 146 require(addr.getWidth > offLen) 147 addr(offLen-1, 0) 148 } 149 150 def get_set_idx(vpn: UInt, nSets: Int): UInt = { 151 require(nSets >= 1) 152 vpn(log2Up(nSets)-1, 0) 153 } 154 155 def drop_set_idx(vpn: UInt, nSets: Int): UInt = { 156 require(nSets >= 1) 157 require(vpn.getWidth > log2Ceil(nSets)) 158 vpn(vpn.getWidth-1, log2Ceil(nSets)) 159 } 160 161 def drop_set_equal(vpn1: UInt, vpn2: UInt, nSets: Int): Bool = { 162 require(nSets >= 1) 163 require(vpn1.getWidth == vpn2.getWidth) 164 if (vpn1.getWidth <= log2Ceil(nSets)) { 165 true.B 166 } else { 167 drop_set_idx(vpn1, nSets) === drop_set_idx(vpn2, nSets) 168 } 169 } 170 171 def replaceWrapper(v: UInt, lruIdx: UInt): UInt = { 172 val width = v.getWidth 173 val emptyIdx = ParallelPriorityMux((0 until width).map( i => (!v(i), i.U(log2Up(width).W)))) 174 val full = Cat(v).andR 175 Mux(full, lruIdx, emptyIdx) 176 } 177 178 def replaceWrapper(v: Seq[Bool], lruIdx: UInt): UInt = { 179 replaceWrapper(VecInit(v).asUInt, lruIdx) 180 } 181 182 import scala.language.implicitConversions 183 184 implicit def hptwresp_to_tlbperm(hptwResp: HptwResp): TlbPermBundle = { 185 val tp = Wire(new TlbPermBundle) 186 val ptePerm = hptwResp.entry.perm.get.asTypeOf(new PtePermBundle().cloneType) 187 tp.pf := hptwResp.gpf 188 tp.af := hptwResp.gaf 189 tp.v := DontCare 190 tp.d := ptePerm.d 191 tp.a := ptePerm.a 192 tp.g := ptePerm.g 193 tp.u := ptePerm.u 194 tp.x := ptePerm.x 195 tp.w := ptePerm.w 196 tp.r := ptePerm.r 197 tp 198 } 199 200 implicit def ptwresp_to_tlbperm(ptwResp: PtwSectorResp): TlbPermBundle = { 201 val tp = Wire(new TlbPermBundle) 202 val ptePerm = ptwResp.entry.perm.get.asTypeOf(new PtePermBundle().cloneType) 203 tp.pf := ptwResp.pf 204 tp.af := ptwResp.af 205 tp.v := ptwResp.entry.v 206 tp.d := ptePerm.d 207 tp.a := ptePerm.a 208 tp.g := ptePerm.g 209 tp.u := ptePerm.u 210 tp.x := ptePerm.x 211 tp.w := ptePerm.w 212 tp.r := ptePerm.r 213 tp 214 } 215} 216 217trait HasPtwConst extends HasTlbConst with MemoryOpConstants{ 218 val PtwWidth = 2 219 val sourceWidth = { if (l2tlbParams.enablePrefetch) PtwWidth + 1 else PtwWidth} 220 val prefetchID = PtwWidth 221 222 val blockBits = l2tlbParams.blockBytes * 8 223 224 val bPtwWidth = log2Up(PtwWidth) 225 val bSourceWidth = log2Up(sourceWidth) 226 // ptwl3: fully-associated 227 val PtwL3TagLen = if (EnableSv48) vpnnLen + extendVpnnBits else 0 228 // ptwl2: fully-associated 229 val PtwL2TagLen = if (EnableSv48) vpnnLen * 2 + extendVpnnBits else vpnnLen + extendVpnnBits 230 231 /* +-------+----------+-------------+ 232 * | Tag | SetIdx | SectorIdx | 233 * +-------+----------+-------------+ 234 */ 235 // ptwl1: 8-way group-associated 236 val PtwL1SetNum = l2tlbParams.l1nSets 237 val PtwL1SectorSize = blockBits / XLEN 238 val PtwL1IdxLen = log2Up(PtwL1SetNum * PtwL1SectorSize) 239 val PtwL1SectorIdxLen = log2Up(PtwL1SectorSize) 240 val PtwL1SetIdxLen = log2Up(PtwL1SetNum) 241 val PtwL1TagLen = if (EnableSv48) vpnnLen * 3 - PtwL1IdxLen + extendVpnnBits else vpnnLen * 2 - PtwL1IdxLen + extendVpnnBits 242 243 // ptwl0: 16-way group-associated 244 val PtwL0SetNum = l2tlbParams.l0nSets 245 val PtwL0SectorSize = blockBits / XLEN 246 val PtwL0IdxLen = log2Up(PtwL0SetNum * PtwL0SectorSize) 247 val PtwL0SectorIdxLen = log2Up(PtwL0SectorSize) 248 val PtwL0SetIdxLen = log2Up(PtwL0SetNum) 249 val PtwL0TagLen = if (EnableSv48) vpnnLen * 4 - PtwL0IdxLen + extendVpnnBits else vpnnLen * 3 - PtwL0IdxLen + extendVpnnBits 250 251 // super page, including 1GB and 2MB page 252 val SPTagLen = if (EnableSv48) vpnnLen * 3 + extendVpnnBits else vpnnLen * 2 + extendVpnnBits 253 254 // miss queue 255 val MissQueueSize = l2tlbParams.ifilterSize + l2tlbParams.dfilterSize 256 val MemReqWidth = l2tlbParams.llptwsize + 1 + 1 257 val HptwReqId = l2tlbParams.llptwsize + 1 258 val FsmReqID = l2tlbParams.llptwsize 259 val bMemID = log2Up(MemReqWidth) 260 261 def genPtwL1Idx(vpn: UInt) = { 262 (vpn(vpnLen - 1, vpnnLen))(PtwL1IdxLen - 1, 0) 263 } 264 265 def genPtwL1SectorIdx(vpn: UInt) = { 266 genPtwL1Idx(vpn)(PtwL1SectorIdxLen - 1, 0) 267 } 268 269 def genPtwL1SetIdx(vpn: UInt) = { 270 genPtwL1Idx(vpn)(PtwL1SetIdxLen + PtwL1SectorIdxLen - 1, PtwL1SectorIdxLen) 271 } 272 273 def genPtwL0Idx(vpn: UInt) = { 274 vpn(PtwL0IdxLen - 1, 0) 275 } 276 277 def genPtwL0SectorIdx(vpn: UInt) = { 278 genPtwL0Idx(vpn)(PtwL0SectorIdxLen - 1, 0) 279 } 280 281 def dropL0SectorBits(vpn: UInt) = { 282 vpn(vpn.getWidth-1, PtwL0SectorIdxLen) 283 } 284 285 def genPtwL0SetIdx(vpn: UInt) = { 286 genPtwL0Idx(vpn)(PtwL0SetIdxLen + PtwL0SectorIdxLen - 1, PtwL0SectorIdxLen) 287 } 288 289 def MakeAddr(ppn: UInt, off: UInt) = { 290 require(off.getWidth == 9) 291 Cat(ppn, off, 0.U(log2Up(XLEN/8).W)) 292 } 293 294 def MakeGPAddr(ppn: UInt, off: UInt) = { 295 require(off.getWidth == 9 || off.getWidth == 11) 296 (Cat(ppn, 0.U(offLen.W)) + Cat(off, 0.U(log2Up(XLEN / 8).W)))(GPAddrBits - 1, 0) 297 } 298 299 def getVpnn(vpn: UInt, idx: Int): UInt = { 300 vpn(vpnnLen*(idx+1)-1, vpnnLen*idx) 301 } 302 303 def getVpnn(vpn: UInt, idx: UInt): UInt = { 304 MuxLookup(idx, 0.U)(Seq( 305 0.U -> vpn(vpnnLen - 1, 0), 306 1.U -> vpn(vpnnLen * 2 - 1, vpnnLen), 307 2.U -> vpn(vpnnLen * 3 - 1, vpnnLen * 2), 308 3.U -> vpn(vpnnLen * 4 - 1, vpnnLen * 3)) 309 ) 310 } 311 312 def getGVpnn(vpn: UInt, idx: UInt, mode: UInt): UInt = { 313 MuxLookup(idx, 0.U)(Seq( 314 0.U -> vpn(vpnnLen - 1, 0), 315 1.U -> vpn(vpnnLen * 2 - 1, vpnnLen), 316 2.U -> Mux(mode === Sv48, vpn(vpnnLen * 3 - 1, vpnnLen * 2), vpn(vpnnLen * 3 + 1, vpnnLen * 2)), 317 3.U -> vpn(vpnnLen * 4 + 1, vpnnLen * 3)) 318 ) 319 } 320 321 def getVpnClip(vpn: UInt, level: Int) = { 322 // level 2 /* vpnn2 */ 323 // level 1 /* vpnn2 * vpnn1 */ 324 // level 0 /* vpnn2 * vpnn1 * vpnn0*/ 325 vpn(vpnLen - 1, level * vpnnLen) 326 } 327 328 def get_next_line(vpn: UInt) = { 329 Cat(dropL0SectorBits(vpn) + 1.U, 0.U(PtwL0SectorIdxLen.W)) 330 } 331 332 def same_l1entry(vpn1: UInt, vpn2: UInt) = { 333 vpn1(vpnLen-1, vpnnLen) === vpn2(vpnLen-1, vpnnLen) 334 } 335 336 def from_pre(source: UInt) = { 337 (source === prefetchID.U) 338 } 339 340 def sel_data(data: UInt, index: UInt): UInt = { 341 val inner_data = data.asTypeOf(Vec(data.getWidth / XLEN, UInt(XLEN.W))) 342 inner_data(index) 343 } 344 345 // vpn1 and vpn2 is at same cacheline 346 def dup(vpn1: UInt, vpn2: UInt): Bool = { 347 dropL0SectorBits(vpn1) === dropL0SectorBits(vpn2) 348 } 349 350 351 def printVec[T <: Data](x: Seq[T]): Printable = { 352 (0 until x.length).map(i => p"(${i.U})${x(i)} ").reduce(_+_) 353 } 354} 355