1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 24import utils._ 25import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 26import freechips.rocketchip.tilelink._ 27 28case class L2TLBParameters 29( 30 name: String = "l2tlb", 31 // l1 32 l1Size: Int = 16, 33 l1Associative: String = "fa", 34 l1Replacer: Option[String] = Some("plru"), 35 // l2 36 l2nSets: Int = 8, 37 l2nWays: Int = 4, 38 l2Replacer: Option[String] = Some("setplru"), 39 // l3 40 l3nSets: Int = 64, 41 l3nWays: Int = 8, 42 l3Replacer: Option[String] = Some("setplru"), 43 // sp 44 spSize: Int = 16, 45 spReplacer: Option[String] = Some("plru"), 46 // miss queue 47 missQueueSize: Int = 8, 48 // sram 49 sramSinglePort: Boolean = true, 50 // way size 51 blockBytes: Int = 64 52) 53 54trait HasTlbConst extends HasXSParameter { 55 val Level = 3 56 57 val offLen = 12 58 val ppnLen = PAddrBits - offLen 59 val vpnnLen = 9 60 val vpnLen = VAddrBits - offLen 61 val flagLen = 8 62 val pteResLen = XLEN - ppnLen - 2 - flagLen 63 val asidLen = 16 64 65 def vaBundle = new Bundle { 66 val vpn = UInt(vpnLen.W) 67 val off = UInt(offLen.W) 68 } 69 def pteBundle = new Bundle { 70 val reserved = UInt(pteResLen.W) 71 val ppn = UInt(ppnLen.W) 72 val rsw = UInt(2.W) 73 val perm = new Bundle { 74 val d = Bool() 75 val a = Bool() 76 val g = Bool() 77 val u = Bool() 78 val x = Bool() 79 val w = Bool() 80 val r = Bool() 81 val v = Bool() 82 } 83 } 84 85 def replaceWrapper(v: UInt, lruIdx: UInt): UInt = { 86 val width = v.getWidth 87 val emptyIdx = ParallelPriorityMux((0 until width).map( i => (!v(i), i.U))) 88 val full = Cat(v).andR 89 Mux(full, lruIdx, emptyIdx) 90 } 91 92 def replaceWrapper(v: Seq[Bool], lruIdx: UInt): UInt = { 93 replaceWrapper(VecInit(v).asUInt, lruIdx) 94 } 95} 96 97trait HasPtwConst extends HasTlbConst with MemoryOpConstants{ 98 val PtwWidth = 2 99 val sramSinglePort = true // NOTE: ptwl2, ptwl3 sram single port or not 100 val blockBits = l2tlbParams.blockBytes * 8 101 102 val bPtwWidth = log2Up(PtwWidth) 103 104 // ptwl1: fully-associated 105 val PtwL1TagLen = vpnnLen 106 107 /* +-------+----------+-------------+ 108 * | Tag | SetIdx | SectorIdx | 109 * +-------+----------+-------------+ 110 */ 111 // ptwl2: 8-way group-associated 112 val l2tlbParams.l2nWays = l2tlbParams.l2nWays 113 val PtwL2SetNum = l2tlbParams.l2nSets 114 val PtwL2SectorSize = blockBits /XLEN 115 val PtwL2IdxLen = log2Up(PtwL2SetNum * PtwL2SectorSize) 116 val PtwL2SectorIdxLen = log2Up(PtwL2SectorSize) 117 val PtwL2SetIdxLen = log2Up(PtwL2SetNum) 118 val PtwL2TagLen = vpnnLen * 2 - PtwL2IdxLen 119 120 // ptwl3: 16-way group-associated 121 val l2tlbParams.l3nWays = l2tlbParams.l3nWays 122 val PtwL3SetNum = l2tlbParams.l3nSets 123 val PtwL3SectorSize = blockBits / XLEN 124 val PtwL3IdxLen = log2Up(PtwL3SetNum * PtwL3SectorSize) 125 val PtwL3SectorIdxLen = log2Up(PtwL3SectorSize) 126 val PtwL3SetIdxLen = log2Up(PtwL3SetNum) 127 val PtwL3TagLen = vpnnLen * 3 - PtwL3IdxLen 128 129 // super page, including 1GB and 2MB page 130 val SPTagLen = vpnnLen * 2 131 132 val MSHRSize = l2tlbParams.missQueueSize 133 134 def genPtwL2Idx(vpn: UInt) = { 135 (vpn(vpnLen - 1, vpnnLen))(PtwL2IdxLen - 1, 0) 136 } 137 138 def genPtwL2SectorIdx(vpn: UInt) = { 139 genPtwL2Idx(vpn)(PtwL2SectorIdxLen - 1, 0) 140 } 141 142 def genPtwL2SetIdx(vpn: UInt) = { 143 genPtwL2Idx(vpn)(PtwL2SetIdxLen + PtwL2SectorIdxLen - 1, PtwL2SectorIdxLen) 144 } 145 146 def genPtwL3Idx(vpn: UInt) = { 147 vpn(PtwL3IdxLen - 1, 0) 148 } 149 150 def genPtwL3SectorIdx(vpn: UInt) = { 151 genPtwL3Idx(vpn)(PtwL3SectorIdxLen - 1, 0) 152 } 153 154 def genPtwL3SetIdx(vpn: UInt) = { 155 genPtwL3Idx(vpn)(PtwL3SetIdxLen + PtwL3SectorIdxLen - 1, PtwL3SectorIdxLen) 156 } 157 158 def MakeAddr(ppn: UInt, off: UInt) = { 159 require(off.getWidth == 9) 160 Cat(ppn, off, 0.U(log2Up(XLEN/8).W))(PAddrBits-1, 0) 161 } 162 163 def getVpnn(vpn: UInt, idx: Int) = { 164 vpn(vpnnLen*(idx+1)-1, vpnnLen*idx) 165 } 166 167 def getVpnClip(vpn: UInt, level: Int) = { 168 // level 0 /* vpnn2 */ 169 // level 1 /* vpnn2 * vpnn1 */ 170 // level 2 /* vpnn2 * vpnn1 * vpnn0*/ 171 vpn(vpnLen - 1, (2 - level) * vpnnLen) 172 } 173 174 def printVec[T <: Data](x: Seq[T]): Printable = { 175 (0 until x.length).map(i => p"(${i.U})${x(i)} ").reduce(_+_) 176 } 177 178} 179