1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 24import utils._ 25import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 26import freechips.rocketchip.tilelink._ 27 28case class TLBParameters 29( 30 name: String = "none", 31 fetchi: Boolean = false, // TODO: remove it 32 useDmode: Boolean = true, 33 sameCycle: Boolean = false, 34 normalNSets: Int = 1, // when da or sa 35 normalNWays: Int = 8, // when fa or sa 36 superNSets: Int = 1, 37 superNWays: Int = 2, 38 normalReplacer: Option[String] = Some("random"), 39 superReplacer: Option[String] = Some("plru"), 40 normalAssociative: String = "fa", // "fa", "sa", "da", "sa" is not supported 41 superAssociative: String = "fa", // must be fa 42 normalAsVictim: Boolean = false, // when get replace from fa, store it into sram 43 outReplace: Boolean = false, 44 shouldBlock: Boolean = false // only for perf, not support for io 45) 46 47case class L2TLBParameters 48( 49 name: String = "l2tlb", 50 // l1 51 l1Size: Int = 16, 52 l1Associative: String = "fa", 53 l1Replacer: Option[String] = Some("plru"), 54 // l2 55 l2nSets: Int = 32, 56 l2nWays: Int = 2, 57 l2Replacer: Option[String] = Some("setplru"), 58 // l3 59 l3nSets: Int = 128, 60 l3nWays: Int = 4, 61 l3Replacer: Option[String] = Some("setplru"), 62 // sp 63 spSize: Int = 16, 64 spReplacer: Option[String] = Some("plru"), 65 // dtlb filter 66 filterSize: Int = 8, 67 // miss queue, add more entries than 'must require' 68 // 0 for easier bug trigger, please set as big as u can, 8 maybe 69 missqueueExtendSize: Int = 0, 70 // way size 71 blockBytes: Int = 64, 72 // prefetch 73 enablePrefetch: Boolean = true, 74 // ecc 75 ecc: Option[String] = Some("secded") 76) 77 78trait HasTlbConst extends HasXSParameter { 79 val Level = 3 80 81 val offLen = 12 82 val ppnLen = PAddrBits - offLen 83 val vpnnLen = 9 84 val vpnLen = VAddrBits - offLen 85 val flagLen = 8 86 val pteResLen = XLEN - ppnLen - 2 - flagLen 87 88 val sramSinglePort = true 89 90 val timeOutThreshold = 5000 91 92 def get_set_idx(vpn: UInt, nSets: Int): UInt = { 93 vpn(log2Up(nSets)-1, 0) 94 } 95 96 def replaceWrapper(v: UInt, lruIdx: UInt): UInt = { 97 val width = v.getWidth 98 val emptyIdx = ParallelPriorityMux((0 until width).map( i => (!v(i), i.U))) 99 val full = Cat(v).andR 100 Mux(full, lruIdx, emptyIdx) 101 } 102 103 def replaceWrapper(v: Seq[Bool], lruIdx: UInt): UInt = { 104 replaceWrapper(VecInit(v).asUInt, lruIdx) 105 } 106 107} 108 109trait HasPtwConst extends HasTlbConst with MemoryOpConstants{ 110 val PtwWidth = 2 111 val sourceWidth = { if (l2tlbParams.enablePrefetch) PtwWidth + 1 else PtwWidth} 112 val prefetchID = PtwWidth 113 val maxPrefetchNum = l2tlbParams.filterSize 114 115 val blockBits = l2tlbParams.blockBytes * 8 116 117 val bPtwWidth = log2Up(PtwWidth) 118 val bSourceWidth = log2Up(sourceWidth) 119 // ptwl1: fully-associated 120 val PtwL1TagLen = vpnnLen 121 122 /* +-------+----------+-------------+ 123 * | Tag | SetIdx | SectorIdx | 124 * +-------+----------+-------------+ 125 */ 126 // ptwl2: 8-way group-associated 127 val l2tlbParams.l2nWays = l2tlbParams.l2nWays 128 val PtwL2SetNum = l2tlbParams.l2nSets 129 val PtwL2SectorSize = blockBits /XLEN 130 val PtwL2IdxLen = log2Up(PtwL2SetNum * PtwL2SectorSize) 131 val PtwL2SectorIdxLen = log2Up(PtwL2SectorSize) 132 val PtwL2SetIdxLen = log2Up(PtwL2SetNum) 133 val PtwL2TagLen = vpnnLen * 2 - PtwL2IdxLen 134 135 // ptwl3: 16-way group-associated 136 val l2tlbParams.l3nWays = l2tlbParams.l3nWays 137 val PtwL3SetNum = l2tlbParams.l3nSets 138 val PtwL3SectorSize = blockBits / XLEN 139 val PtwL3IdxLen = log2Up(PtwL3SetNum * PtwL3SectorSize) 140 val PtwL3SectorIdxLen = log2Up(PtwL3SectorSize) 141 val PtwL3SetIdxLen = log2Up(PtwL3SetNum) 142 val PtwL3TagLen = vpnnLen * 3 - PtwL3IdxLen 143 144 // super page, including 1GB and 2MB page 145 val SPTagLen = vpnnLen * 2 146 147 // miss queue 148 val MSHRBaseSize = 1 + l2tlbParams.filterSize + l2tlbParams.missqueueExtendSize 149 val MSHRSize = { if (l2tlbParams.enablePrefetch) (MSHRBaseSize + 1) else MSHRBaseSize } 150 val MemReqWidth = MSHRSize + 1 151 val FsmReqID = MSHRSize 152 val bMemID = log2Up(MSHRSize + 1) 153 154 def genPtwL2Idx(vpn: UInt) = { 155 (vpn(vpnLen - 1, vpnnLen))(PtwL2IdxLen - 1, 0) 156 } 157 158 def genPtwL2SectorIdx(vpn: UInt) = { 159 genPtwL2Idx(vpn)(PtwL2SectorIdxLen - 1, 0) 160 } 161 162 def genPtwL2SetIdx(vpn: UInt) = { 163 genPtwL2Idx(vpn)(PtwL2SetIdxLen + PtwL2SectorIdxLen - 1, PtwL2SectorIdxLen) 164 } 165 166 def genPtwL3Idx(vpn: UInt) = { 167 vpn(PtwL3IdxLen - 1, 0) 168 } 169 170 def genPtwL3SectorIdx(vpn: UInt) = { 171 genPtwL3Idx(vpn)(PtwL3SectorIdxLen - 1, 0) 172 } 173 174 def dropL3SectorBits(vpn: UInt) = { 175 vpn(vpn.getWidth-1, PtwL3SectorIdxLen) 176 } 177 178 def genPtwL3SetIdx(vpn: UInt) = { 179 genPtwL3Idx(vpn)(PtwL3SetIdxLen + PtwL3SectorIdxLen - 1, PtwL3SectorIdxLen) 180 } 181 182 def MakeAddr(ppn: UInt, off: UInt) = { 183 require(off.getWidth == 9) 184 Cat(ppn, off, 0.U(log2Up(XLEN/8).W))(PAddrBits-1, 0) 185 } 186 187 def getVpnn(vpn: UInt, idx: Int): UInt = { 188 vpn(vpnnLen*(idx+1)-1, vpnnLen*idx) 189 } 190 191 def getVpnClip(vpn: UInt, level: Int) = { 192 // level 0 /* vpnn2 */ 193 // level 1 /* vpnn2 * vpnn1 */ 194 // level 2 /* vpnn2 * vpnn1 * vpnn0*/ 195 vpn(vpnLen - 1, (2 - level) * vpnnLen) 196 } 197 198 def get_next_line(vpn: UInt) = { 199 Cat(dropL3SectorBits(vpn) + 1.U, 0.U(PtwL3SectorIdxLen.W)) 200 } 201 202 def same_l2entry(vpn1: UInt, vpn2: UInt) = { 203 vpn1(vpnLen-1, vpnnLen) === vpn2(vpnLen-1, vpnnLen) 204 } 205 206 def from_pre(source: UInt) = { 207 (source === prefetchID.U) 208 } 209 210 def printVec[T <: Data](x: Seq[T]): Printable = { 211 (0 until x.length).map(i => p"(${i.U})${x(i)} ").reduce(_+_) 212 } 213} 214