1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 24import utils._ 25import utility._ 26import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 27import freechips.rocketchip.tilelink._ 28 29 30case class TLBParameters 31( 32 name: String = "none", 33 fetchi: Boolean = false, // TODO: remove it 34 fenceDelay: Int = 2, 35 useDmode: Boolean = true, 36 normalNSets: Int = 1, // when da or sa 37 normalNWays: Int = 8, // when fa or sa 38 superNSets: Int = 1, 39 superNWays: Int = 2, 40 normalReplacer: Option[String] = Some("random"), 41 superReplacer: Option[String] = Some("plru"), 42 normalAssociative: String = "fa", // "fa", "sa", "da", "sa" is not supported 43 superAssociative: String = "fa", // must be fa 44 normalAsVictim: Boolean = false, // when get replace from fa, store it into sram 45 outReplace: Boolean = false, 46 partialStaticPMP: Boolean = false, // partial static pmp result stored in entries 47 outsideRecvFlush: Boolean = false, // if outside moudle waiting for tlb recv flush pipe 48 saveLevel: Boolean = false 49) 50 51case class L2TLBParameters 52( 53 name: String = "l2tlb", 54 // l1 55 l1Size: Int = 16, 56 l1Associative: String = "fa", 57 l1Replacer: Option[String] = Some("plru"), 58 // l2 59 l2nSets: Int = 32, 60 l2nWays: Int = 2, 61 l2Replacer: Option[String] = Some("setplru"), 62 // l3 63 l3nSets: Int = 128, 64 l3nWays: Int = 4, 65 l3Replacer: Option[String] = Some("setplru"), 66 // sp 67 spSize: Int = 16, 68 spReplacer: Option[String] = Some("plru"), 69 // filter 70 ifilterSize: Int = 4, 71 dfilterSize: Int = 8, 72 // miss queue, add more entries than 'must require' 73 // 0 for easier bug trigger, please set as big as u can, 8 maybe 74 missqueueExtendSize: Int = 0, 75 // llptw 76 llptwsize: Int = 6, 77 // way size 78 blockBytes: Int = 64, 79 // prefetch 80 enablePrefetch: Boolean = true, 81 // ecc 82 ecc: Option[String] = Some("secded") 83) 84 85trait HasTlbConst extends HasXSParameter { 86 val Level = 3 87 88 val offLen = 12 89 val ppnLen = PAddrBits - offLen 90 val vpnnLen = 9 91 val vpnLen = VAddrBits - offLen 92 val flagLen = 8 93 val pteResLen = XLEN - 44 - 2 - flagLen 94 val ppnHignLen = 44 - ppnLen 95 96 val sramSinglePort = true 97 98 val timeOutThreshold = 10000 99 100 def get_pn(addr: UInt) = { 101 require(addr.getWidth > offLen) 102 addr(addr.getWidth-1, offLen) 103 } 104 def get_off(addr: UInt) = { 105 require(addr.getWidth > offLen) 106 addr(offLen-1, 0) 107 } 108 109 def get_set_idx(vpn: UInt, nSets: Int): UInt = { 110 require(nSets >= 1) 111 vpn(log2Up(nSets)-1, 0) 112 } 113 114 def drop_set_idx(vpn: UInt, nSets: Int): UInt = { 115 require(nSets >= 1) 116 require(vpn.getWidth > log2Ceil(nSets)) 117 vpn(vpn.getWidth-1, log2Ceil(nSets)) 118 } 119 120 def drop_set_equal(vpn1: UInt, vpn2: UInt, nSets: Int): Bool = { 121 require(nSets >= 1) 122 require(vpn1.getWidth == vpn2.getWidth) 123 if (vpn1.getWidth <= log2Ceil(nSets)) { 124 true.B 125 } else { 126 drop_set_idx(vpn1, nSets) === drop_set_idx(vpn2, nSets) 127 } 128 } 129 130 def replaceWrapper(v: UInt, lruIdx: UInt): UInt = { 131 val width = v.getWidth 132 val emptyIdx = ParallelPriorityMux((0 until width).map( i => (!v(i), i.U(log2Up(width).W)))) 133 val full = Cat(v).andR 134 Mux(full, lruIdx, emptyIdx) 135 } 136 137 def replaceWrapper(v: Seq[Bool], lruIdx: UInt): UInt = { 138 replaceWrapper(VecInit(v).asUInt, lruIdx) 139 } 140 141 implicit def ptwresp_to_tlbperm(ptwResp: PtwResp): TlbPermBundle = { 142 val tp = Wire(new TlbPermBundle) 143 val ptePerm = ptwResp.entry.perm.get.asTypeOf(new PtePermBundle().cloneType) 144 tp.pf := ptwResp.pf 145 tp.af := ptwResp.af 146 tp.d := ptePerm.d 147 tp.a := ptePerm.a 148 tp.g := ptePerm.g 149 tp.u := ptePerm.u 150 tp.x := ptePerm.x 151 tp.w := ptePerm.w 152 tp.r := ptePerm.r 153 tp.pm := DontCare 154 tp 155 } 156} 157 158trait HasPtwConst extends HasTlbConst with MemoryOpConstants{ 159 val PtwWidth = 2 160 val sourceWidth = { if (l2tlbParams.enablePrefetch) PtwWidth + 1 else PtwWidth} 161 val prefetchID = PtwWidth 162 163 val blockBits = l2tlbParams.blockBytes * 8 164 165 val bPtwWidth = log2Up(PtwWidth) 166 val bSourceWidth = log2Up(sourceWidth) 167 // ptwl1: fully-associated 168 val PtwL1TagLen = vpnnLen 169 170 /* +-------+----------+-------------+ 171 * | Tag | SetIdx | SectorIdx | 172 * +-------+----------+-------------+ 173 */ 174 // ptwl2: 8-way group-associated 175 val l2tlbParams.l2nWays = l2tlbParams.l2nWays 176 val PtwL2SetNum = l2tlbParams.l2nSets 177 val PtwL2SectorSize = blockBits /XLEN 178 val PtwL2IdxLen = log2Up(PtwL2SetNum * PtwL2SectorSize) 179 val PtwL2SectorIdxLen = log2Up(PtwL2SectorSize) 180 val PtwL2SetIdxLen = log2Up(PtwL2SetNum) 181 val PtwL2TagLen = vpnnLen * 2 - PtwL2IdxLen 182 183 // ptwl3: 16-way group-associated 184 val l2tlbParams.l3nWays = l2tlbParams.l3nWays 185 val PtwL3SetNum = l2tlbParams.l3nSets 186 val PtwL3SectorSize = blockBits / XLEN 187 val PtwL3IdxLen = log2Up(PtwL3SetNum * PtwL3SectorSize) 188 val PtwL3SectorIdxLen = log2Up(PtwL3SectorSize) 189 val PtwL3SetIdxLen = log2Up(PtwL3SetNum) 190 val PtwL3TagLen = vpnnLen * 3 - PtwL3IdxLen 191 192 // super page, including 1GB and 2MB page 193 val SPTagLen = vpnnLen * 2 194 195 // miss queue 196 val MissQueueSize = l2tlbParams.ifilterSize + l2tlbParams.dfilterSize 197 val MemReqWidth = l2tlbParams.llptwsize + 1 198 val FsmReqID = l2tlbParams.llptwsize 199 val bMemID = log2Up(MemReqWidth) 200 201 def genPtwL2Idx(vpn: UInt) = { 202 (vpn(vpnLen - 1, vpnnLen))(PtwL2IdxLen - 1, 0) 203 } 204 205 def genPtwL2SectorIdx(vpn: UInt) = { 206 genPtwL2Idx(vpn)(PtwL2SectorIdxLen - 1, 0) 207 } 208 209 def genPtwL2SetIdx(vpn: UInt) = { 210 genPtwL2Idx(vpn)(PtwL2SetIdxLen + PtwL2SectorIdxLen - 1, PtwL2SectorIdxLen) 211 } 212 213 def genPtwL3Idx(vpn: UInt) = { 214 vpn(PtwL3IdxLen - 1, 0) 215 } 216 217 def genPtwL3SectorIdx(vpn: UInt) = { 218 genPtwL3Idx(vpn)(PtwL3SectorIdxLen - 1, 0) 219 } 220 221 def dropL3SectorBits(vpn: UInt) = { 222 vpn(vpn.getWidth-1, PtwL3SectorIdxLen) 223 } 224 225 def genPtwL3SetIdx(vpn: UInt) = { 226 genPtwL3Idx(vpn)(PtwL3SetIdxLen + PtwL3SectorIdxLen - 1, PtwL3SectorIdxLen) 227 } 228 229 def MakeAddr(ppn: UInt, off: UInt) = { 230 require(off.getWidth == 9) 231 Cat(ppn, off, 0.U(log2Up(XLEN/8).W))(PAddrBits-1, 0) 232 } 233 234 def getVpnn(vpn: UInt, idx: Int): UInt = { 235 vpn(vpnnLen*(idx+1)-1, vpnnLen*idx) 236 } 237 238 def getVpnClip(vpn: UInt, level: Int) = { 239 // level 0 /* vpnn2 */ 240 // level 1 /* vpnn2 * vpnn1 */ 241 // level 2 /* vpnn2 * vpnn1 * vpnn0*/ 242 vpn(vpnLen - 1, (2 - level) * vpnnLen) 243 } 244 245 def get_next_line(vpn: UInt) = { 246 Cat(dropL3SectorBits(vpn) + 1.U, 0.U(PtwL3SectorIdxLen.W)) 247 } 248 249 def same_l2entry(vpn1: UInt, vpn2: UInt) = { 250 vpn1(vpnLen-1, vpnnLen) === vpn2(vpnLen-1, vpnnLen) 251 } 252 253 def from_pre(source: UInt) = { 254 (source === prefetchID.U) 255 } 256 257 def sel_data(data: UInt, index: UInt): UInt = { 258 val inner_data = data.asTypeOf(Vec(data.getWidth / XLEN, UInt(XLEN.W))) 259 inner_data(index) 260 } 261 262 // vpn1 and vpn2 is at same cacheline 263 def dup(vpn1: UInt, vpn2: UInt): Bool = { 264 dropL3SectorBits(vpn1) === dropL3SectorBits(vpn2) 265 } 266 267 268 def printVec[T <: Data](x: Seq[T]): Printable = { 269 (0 until x.length).map(i => p"(${i.U})${x(i)} ").reduce(_+_) 270 } 271} 272