1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: 9* http://license.coscl.org.cn/MulanPSL2 10* 11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14* 15* See the Mulan PSL v2 for more details. 16***************************************************************************************/ 17 18package xiangshan.cache.mmu 19 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import xiangshan._ 24import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 25import utils._ 26import utility._ 27import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 28import freechips.rocketchip.tilelink._ 29 30 31case class TLBParameters 32( 33 name: String = "none", 34 fetchi: Boolean = false, // TODO: remove it 35 fenceDelay: Int = 2, 36 useDmode: Boolean = true, 37 NSets: Int = 1, 38 NWays: Int = 2, 39 Replacer: Option[String] = Some("plru"), 40 Associative: String = "fa", // must be fa 41 outReplace: Boolean = false, 42 partialStaticPMP: Boolean = false, // partial static pmp result stored in entries 43 outsideRecvFlush: Boolean = false, // if outside moudle waiting for tlb recv flush pipe 44 saveLevel: Boolean = false, 45 lgMaxSize: Int = 3 46) 47 48case class L2TLBParameters 49( 50 name: String = "l2tlb", 51 // l1 52 l1Size: Int = 16, 53 l1Associative: String = "fa", 54 l1Replacer: Option[String] = Some("plru"), 55 // l2 56 l2nSets: Int = 8, 57 l2nWays: Int = 4, 58 l2Replacer: Option[String] = Some("setplru"), 59 // l3 60 l3nSets: Int = 32, 61 l3nWays: Int = 8, 62 l3Replacer: Option[String] = Some("setplru"), 63 // sp 64 spSize: Int = 16, 65 spReplacer: Option[String] = Some("plru"), 66 // filter 67 ifilterSize: Int = 8, 68 dfilterSize: Int = 32, 69 // miss queue, add more entries than 'must require' 70 // 0 for easier bug trigger, please set as big as u can, 8 maybe 71 missqueueExtendSize: Int = 0, 72 // llptw 73 llptwsize: Int = 6, 74 // way size 75 blockBytes: Int = 64, 76 // prefetch 77 enablePrefetch: Boolean = true, 78 // ecc 79 ecc: Option[String] = Some("secded"), 80 // enable ecc 81 enablePTWECC: Boolean = false 82) 83 84trait HasTlbConst extends HasXSParameter { 85 val Level = 3 86 87 val offLen = 12 88 val ppnLen = PAddrBits - offLen 89 val vpnnLen = 9 90 val extendVpnnBits = if (HasHExtension) 2 else 0 91 val vpnLen = VAddrBits - offLen // when opening H extention, vpnlen broaden two bits 92 val flagLen = 8 93 val pteResLen = XLEN - 44 - 2 - flagLen 94 val ppnHignLen = 44 - ppnLen 95 val gvpnLen = GPAddrBits - offLen 96 97 val tlbcontiguous = 8 98 val sectortlbwidth = log2Up(tlbcontiguous) 99 val sectorppnLen = ppnLen - sectortlbwidth 100 val sectorgvpnLen = gvpnLen - sectortlbwidth 101 val sectorvpnLen = vpnLen - sectortlbwidth 102 103 val loadfiltersize = 16 // 4*3(LduCnt:2 + HyuCnt:1) + 4(prefetch:1) 104 val storefiltersize = if (StorePipelineWidth >= 3) 16 else 8 105 val prefetchfiltersize = 8 106 107 val sramSinglePort = true 108 109 val timeOutThreshold = 10000 110 111 def noS2xlate = "b00".U 112 def allStage = "b11".U 113 def onlyStage1 = "b01".U 114 def onlyStage2 = "b10".U 115 116 def get_pn(addr: UInt) = { 117 require(addr.getWidth > offLen) 118 addr(addr.getWidth-1, offLen) 119 } 120 def get_off(addr: UInt) = { 121 require(addr.getWidth > offLen) 122 addr(offLen-1, 0) 123 } 124 125 def get_set_idx(vpn: UInt, nSets: Int): UInt = { 126 require(nSets >= 1) 127 vpn(log2Up(nSets)-1, 0) 128 } 129 130 def drop_set_idx(vpn: UInt, nSets: Int): UInt = { 131 require(nSets >= 1) 132 require(vpn.getWidth > log2Ceil(nSets)) 133 vpn(vpn.getWidth-1, log2Ceil(nSets)) 134 } 135 136 def drop_set_equal(vpn1: UInt, vpn2: UInt, nSets: Int): Bool = { 137 require(nSets >= 1) 138 require(vpn1.getWidth == vpn2.getWidth) 139 if (vpn1.getWidth <= log2Ceil(nSets)) { 140 true.B 141 } else { 142 drop_set_idx(vpn1, nSets) === drop_set_idx(vpn2, nSets) 143 } 144 } 145 146 def replaceWrapper(v: UInt, lruIdx: UInt): UInt = { 147 val width = v.getWidth 148 val emptyIdx = ParallelPriorityMux((0 until width).map( i => (!v(i), i.U(log2Up(width).W)))) 149 val full = Cat(v).andR 150 Mux(full, lruIdx, emptyIdx) 151 } 152 153 def replaceWrapper(v: Seq[Bool], lruIdx: UInt): UInt = { 154 replaceWrapper(VecInit(v).asUInt, lruIdx) 155 } 156 157 import scala.language.implicitConversions 158 159 implicit def hptwresp_to_tlbperm(hptwResp: HptwResp): TlbPermBundle = { 160 val tp = Wire(new TlbPermBundle) 161 val ptePerm = hptwResp.entry.perm.get.asTypeOf(new PtePermBundle().cloneType) 162 tp.pf := hptwResp.gpf 163 tp.af := hptwResp.gaf 164 tp.d := ptePerm.d 165 tp.a := ptePerm.a 166 tp.g := ptePerm.g 167 tp.u := ptePerm.u 168 tp.x := ptePerm.x 169 tp.w := ptePerm.w 170 tp.r := ptePerm.r 171 tp 172 } 173 174 implicit def ptwresp_to_tlbperm(ptwResp: PtwSectorResp): TlbPermBundle = { 175 val tp = Wire(new TlbPermBundle) 176 val ptePerm = ptwResp.entry.perm.get.asTypeOf(new PtePermBundle().cloneType) 177 tp.pf := ptwResp.pf 178 tp.af := ptwResp.af 179 tp.d := ptePerm.d 180 tp.a := ptePerm.a 181 tp.g := ptePerm.g 182 tp.u := ptePerm.u 183 tp.x := ptePerm.x 184 tp.w := ptePerm.w 185 tp.r := ptePerm.r 186 tp 187 } 188} 189 190trait HasPtwConst extends HasTlbConst with MemoryOpConstants{ 191 val PtwWidth = 2 192 val sourceWidth = { if (l2tlbParams.enablePrefetch) PtwWidth + 1 else PtwWidth} 193 val prefetchID = PtwWidth 194 195 val blockBits = l2tlbParams.blockBytes * 8 196 197 val bPtwWidth = log2Up(PtwWidth) 198 val bSourceWidth = log2Up(sourceWidth) 199 // ptwl1: fully-associated 200 val PtwL1TagLen = vpnnLen + extendVpnnBits 201 202 /* +-------+----------+-------------+ 203 * | Tag | SetIdx | SectorIdx | 204 * +-------+----------+-------------+ 205 */ 206 // ptwl2: 8-way group-associated 207 val PtwL2SetNum = l2tlbParams.l2nSets 208 val PtwL2SectorSize = blockBits / XLEN 209 val PtwL2IdxLen = log2Up(PtwL2SetNum * PtwL2SectorSize) 210 val PtwL2SectorIdxLen = log2Up(PtwL2SectorSize) 211 val PtwL2SetIdxLen = log2Up(PtwL2SetNum) 212 val PtwL2TagLen = vpnnLen * 2 - PtwL2IdxLen + extendVpnnBits 213 214 // ptwl3: 16-way group-associated 215 val PtwL3SetNum = l2tlbParams.l3nSets 216 val PtwL3SectorSize = blockBits / XLEN 217 val PtwL3IdxLen = log2Up(PtwL3SetNum * PtwL3SectorSize) 218 val PtwL3SectorIdxLen = log2Up(PtwL3SectorSize) 219 val PtwL3SetIdxLen = log2Up(PtwL3SetNum) 220 val PtwL3TagLen = vpnnLen * 3 - PtwL3IdxLen + extendVpnnBits 221 222 // super page, including 1GB and 2MB page 223 val SPTagLen = vpnnLen * 2 + extendVpnnBits 224 225 // miss queue 226 val MissQueueSize = l2tlbParams.ifilterSize + l2tlbParams.dfilterSize 227 val MemReqWidth = l2tlbParams.llptwsize + 1 + 1 228 val HptwReqId = l2tlbParams.llptwsize + 1 229 val FsmReqID = l2tlbParams.llptwsize 230 val bMemID = log2Up(MemReqWidth) 231 232 def genPtwL2Idx(vpn: UInt) = { 233 (vpn(vpnLen - 1, vpnnLen))(PtwL2IdxLen - 1, 0) 234 } 235 236 def genPtwL2SectorIdx(vpn: UInt) = { 237 genPtwL2Idx(vpn)(PtwL2SectorIdxLen - 1, 0) 238 } 239 240 def genPtwL2SetIdx(vpn: UInt) = { 241 genPtwL2Idx(vpn)(PtwL2SetIdxLen + PtwL2SectorIdxLen - 1, PtwL2SectorIdxLen) 242 } 243 244 def genPtwL3Idx(vpn: UInt) = { 245 vpn(PtwL3IdxLen - 1, 0) 246 } 247 248 def genPtwL3SectorIdx(vpn: UInt) = { 249 genPtwL3Idx(vpn)(PtwL3SectorIdxLen - 1, 0) 250 } 251 252 def dropL3SectorBits(vpn: UInt) = { 253 vpn(vpn.getWidth-1, PtwL3SectorIdxLen) 254 } 255 256 def genPtwL3SetIdx(vpn: UInt) = { 257 genPtwL3Idx(vpn)(PtwL3SetIdxLen + PtwL3SectorIdxLen - 1, PtwL3SectorIdxLen) 258 } 259 260 def MakeAddr(ppn: UInt, off: UInt) = { 261 require(off.getWidth == 9) 262 Cat(ppn, off, 0.U(log2Up(XLEN/8).W))(PAddrBits-1, 0) 263 } 264 265 def MakeGPAddr(ppn: UInt, off: UInt) = { 266 require(off.getWidth == 9 || off.getWidth == 11) 267 (Cat(ppn, 0.U(offLen.W)) + Cat(off, 0.U(log2Up(XLEN / 8).W)))(GPAddrBits - 1, 0) 268 } 269 270 def getVpnn(vpn: UInt, idx: Int): UInt = { 271 vpn(vpnnLen*(idx+1)-1, vpnnLen*idx) 272 } 273 274 def getVpnn(vpn: UInt, idx: UInt): UInt = { 275 Mux(idx === 0.U, vpn(vpnnLen - 1, 0), Mux(idx === 1.U, vpn(vpnnLen * 2 - 1, vpnnLen), vpn(vpnnLen * 3 - 1, vpnnLen * 2))) 276 } 277 278 def getGVpnn(vpn: UInt, idx: UInt): UInt = { 279 Mux(idx === 0.U, vpn(vpnnLen - 1, 0), Mux(idx === 1.U, vpn(vpnnLen * 2 - 1, vpnnLen), vpn(vpnnLen * 3 + 1, vpnnLen * 2))) 280 } 281 282 def getVpnClip(vpn: UInt, level: Int) = { 283 // level 0 /* vpnn2 */ 284 // level 1 /* vpnn2 * vpnn1 */ 285 // level 2 /* vpnn2 * vpnn1 * vpnn0*/ 286 vpn(vpnLen - 1, (2 - level) * vpnnLen) 287 } 288 289 def get_next_line(vpn: UInt) = { 290 Cat(dropL3SectorBits(vpn) + 1.U, 0.U(PtwL3SectorIdxLen.W)) 291 } 292 293 def same_l2entry(vpn1: UInt, vpn2: UInt) = { 294 vpn1(vpnLen-1, vpnnLen) === vpn2(vpnLen-1, vpnnLen) 295 } 296 297 def from_pre(source: UInt) = { 298 (source === prefetchID.U) 299 } 300 301 def sel_data(data: UInt, index: UInt): UInt = { 302 val inner_data = data.asTypeOf(Vec(data.getWidth / XLEN, UInt(XLEN.W))) 303 inner_data(index) 304 } 305 306 // vpn1 and vpn2 is at same cacheline 307 def dup(vpn1: UInt, vpn2: UInt): Bool = { 308 dropL3SectorBits(vpn1) === dropL3SectorBits(vpn2) 309 } 310 311 312 def printVec[T <: Data](x: Seq[T]): Printable = { 313 (0 until x.length).map(i => p"(${i.U})${x(i)} ").reduce(_+_) 314 } 315} 316