1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 24import utils._ 25import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 26import freechips.rocketchip.tilelink._ 27 28case class TLBParameters 29( 30 name: String = "none", 31 fetchi: Boolean = false, // TODO: remove it 32 useDmode: Boolean = true, 33 sameCycle: Boolean = false, 34 normalNSets: Int = 1, // when da or sa 35 normalNWays: Int = 8, // when fa or sa 36 superNSets: Int = 1, 37 superNWays: Int = 2, 38 normalReplacer: Option[String] = Some("random"), 39 superReplacer: Option[String] = Some("plru"), 40 normalAssociative: String = "fa", // "fa", "sa", "da", "sa" is not supported 41 superAssociative: String = "fa", // must be fa 42 normalAsVictim: Boolean = false, // when get replace from fa, store it into sram 43 outReplace: Boolean = false, 44 shouldBlock: Boolean = false // only for perf, not support for io 45) 46 47case class L2TLBParameters 48( 49 name: String = "l2tlb", 50 // l1 51 l1Size: Int = 16, 52 l1Associative: String = "fa", 53 l1Replacer: Option[String] = Some("plru"), 54 // l2 55 l2nSets: Int = 32, 56 l2nWays: Int = 2, 57 l2Replacer: Option[String] = Some("setplru"), 58 // l3 59 l3nSets: Int = 128, 60 l3nWays: Int = 4, 61 l3Replacer: Option[String] = Some("setplru"), 62 // sp 63 spSize: Int = 16, 64 spReplacer: Option[String] = Some("plru"), 65 // miss queue 66 missQueueSize: Int = 9, 67 // way size 68 blockBytes: Int = 64 69) 70 71trait HasTlbConst extends HasXSParameter { 72 val Level = 3 73 74 val offLen = 12 75 val ppnLen = PAddrBits - offLen 76 val vpnnLen = 9 77 val vpnLen = VAddrBits - offLen 78 val flagLen = 8 79 val pteResLen = XLEN - ppnLen - 2 - flagLen 80 val asidLen = 16 81 82 val sramSinglePort = true 83 84 val timeOutThreshold = 2000 85 86 def get_idx(vpn: UInt, nSets: Int): UInt = { 87 vpn(log2Up(nSets)-1, 0) 88 } 89 90 def replaceWrapper(v: UInt, lruIdx: UInt): UInt = { 91 val width = v.getWidth 92 val emptyIdx = ParallelPriorityMux((0 until width).map( i => (!v(i), i.U))) 93 val full = Cat(v).andR 94 Mux(full, lruIdx, emptyIdx) 95 } 96 97 def replaceWrapper(v: Seq[Bool], lruIdx: UInt): UInt = { 98 replaceWrapper(VecInit(v).asUInt, lruIdx) 99 } 100 101} 102 103trait HasPtwConst extends HasTlbConst with MemoryOpConstants{ 104 val PtwWidth = 2 105 val blockBits = l2tlbParams.blockBytes * 8 106 107 val bPtwWidth = log2Up(PtwWidth) 108 109 // ptwl1: fully-associated 110 val PtwL1TagLen = vpnnLen 111 112 /* +-------+----------+-------------+ 113 * | Tag | SetIdx | SectorIdx | 114 * +-------+----------+-------------+ 115 */ 116 // ptwl2: 8-way group-associated 117 val l2tlbParams.l2nWays = l2tlbParams.l2nWays 118 val PtwL2SetNum = l2tlbParams.l2nSets 119 val PtwL2SectorSize = blockBits /XLEN 120 val PtwL2IdxLen = log2Up(PtwL2SetNum * PtwL2SectorSize) 121 val PtwL2SectorIdxLen = log2Up(PtwL2SectorSize) 122 val PtwL2SetIdxLen = log2Up(PtwL2SetNum) 123 val PtwL2TagLen = vpnnLen * 2 - PtwL2IdxLen 124 125 // ptwl3: 16-way group-associated 126 val l2tlbParams.l3nWays = l2tlbParams.l3nWays 127 val PtwL3SetNum = l2tlbParams.l3nSets 128 val PtwL3SectorSize = blockBits / XLEN 129 val PtwL3IdxLen = log2Up(PtwL3SetNum * PtwL3SectorSize) 130 val PtwL3SectorIdxLen = log2Up(PtwL3SectorSize) 131 val PtwL3SetIdxLen = log2Up(PtwL3SetNum) 132 val PtwL3TagLen = vpnnLen * 3 - PtwL3IdxLen 133 134 // super page, including 1GB and 2MB page 135 val SPTagLen = vpnnLen * 2 136 137 val MSHRSize = l2tlbParams.missQueueSize 138 val MemReqWidth = MSHRSize + 1 139 val bMemID = log2Up(MSHRSize + 1) 140 141 def genPtwL2Idx(vpn: UInt) = { 142 (vpn(vpnLen - 1, vpnnLen))(PtwL2IdxLen - 1, 0) 143 } 144 145 def genPtwL2SectorIdx(vpn: UInt) = { 146 genPtwL2Idx(vpn)(PtwL2SectorIdxLen - 1, 0) 147 } 148 149 def genPtwL2SetIdx(vpn: UInt) = { 150 genPtwL2Idx(vpn)(PtwL2SetIdxLen + PtwL2SectorIdxLen - 1, PtwL2SectorIdxLen) 151 } 152 153 def genPtwL3Idx(vpn: UInt) = { 154 vpn(PtwL3IdxLen - 1, 0) 155 } 156 157 def genPtwL3SectorIdx(vpn: UInt) = { 158 genPtwL3Idx(vpn)(PtwL3SectorIdxLen - 1, 0) 159 } 160 161 def dropL3SectorBits(vpn: UInt) = { 162 vpn(vpn.getWidth-1, PtwL3SectorIdxLen) 163 } 164 165 def genPtwL3SetIdx(vpn: UInt) = { 166 genPtwL3Idx(vpn)(PtwL3SetIdxLen + PtwL3SectorIdxLen - 1, PtwL3SectorIdxLen) 167 } 168 169 def MakeAddr(ppn: UInt, off: UInt) = { 170 require(off.getWidth == 9) 171 Cat(ppn, off, 0.U(log2Up(XLEN/8).W))(PAddrBits-1, 0) 172 } 173 174 def getVpnn(vpn: UInt, idx: Int): UInt = { 175 vpn(vpnnLen*(idx+1)-1, vpnnLen*idx) 176 } 177 178 def getVpnClip(vpn: UInt, level: Int) = { 179 // level 0 /* vpnn2 */ 180 // level 1 /* vpnn2 * vpnn1 */ 181 // level 2 /* vpnn2 * vpnn1 * vpnn0*/ 182 vpn(vpnLen - 1, (2 - level) * vpnnLen) 183 } 184 185 def printVec[T <: Data](x: Seq[T]): Printable = { 186 (0 until x.length).map(i => p"(${i.U})${x(i)} ").reduce(_+_) 187 } 188 189} 190