1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 24import utils._ 25import utility._ 26import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 27import freechips.rocketchip.tilelink._ 28 29 30case class TLBParameters 31( 32 name: String = "none", 33 fetchi: Boolean = false, // TODO: remove it 34 fenceDelay: Int = 2, 35 useDmode: Boolean = true, 36 NSets: Int = 1, 37 NWays: Int = 2, 38 Replacer: Option[String] = Some("plru"), 39 Associative: String = "fa", // must be fa 40 outReplace: Boolean = false, 41 partialStaticPMP: Boolean = false, // partial static pmp result stored in entries 42 outsideRecvFlush: Boolean = false, // if outside moudle waiting for tlb recv flush pipe 43 saveLevel: Boolean = false 44) 45 46case class L2TLBParameters 47( 48 name: String = "l2tlb", 49 // l1 50 l1Size: Int = 16, 51 l1Associative: String = "fa", 52 l1Replacer: Option[String] = Some("plru"), 53 // l2 54 l2nSets: Int = 32, 55 l2nWays: Int = 2, 56 l2Replacer: Option[String] = Some("setplru"), 57 // l3 58 l3nSets: Int = 128, 59 l3nWays: Int = 4, 60 l3Replacer: Option[String] = Some("setplru"), 61 // sp 62 spSize: Int = 16, 63 spReplacer: Option[String] = Some("plru"), 64 // filter 65 ifilterSize: Int = 8, 66 dfilterSize: Int = 8, 67 // miss queue, add more entries than 'must require' 68 // 0 for easier bug trigger, please set as big as u can, 8 maybe 69 missqueueExtendSize: Int = 0, 70 // llptw 71 llptwsize: Int = 6, 72 // way size 73 blockBytes: Int = 64, 74 // prefetch 75 enablePrefetch: Boolean = true, 76 // ecc 77 ecc: Option[String] = Some("secded") 78) 79 80trait HasTlbConst extends HasXSParameter { 81 val Level = 3 82 83 val offLen = 12 84 val ppnLen = PAddrBits - offLen 85 val vpnnLen = 9 86 val vpnLen = VAddrBits - offLen 87 val flagLen = 8 88 val pteResLen = XLEN - 44 - 2 - flagLen 89 val ppnHignLen = 44 - ppnLen 90 91 val tlbcontiguous = 8 92 val sectortlbwidth = log2Up(tlbcontiguous) 93 val sectorppnLen = ppnLen - sectortlbwidth 94 val sectorvpnLen = vpnLen - sectortlbwidth 95 96 val sramSinglePort = true 97 98 val timeOutThreshold = 10000 99 100 def get_pn(addr: UInt) = { 101 require(addr.getWidth > offLen) 102 addr(addr.getWidth-1, offLen) 103 } 104 def get_off(addr: UInt) = { 105 require(addr.getWidth > offLen) 106 addr(offLen-1, 0) 107 } 108 109 def get_set_idx(vpn: UInt, nSets: Int): UInt = { 110 require(nSets >= 1) 111 vpn(log2Up(nSets)-1, 0) 112 } 113 114 def drop_set_idx(vpn: UInt, nSets: Int): UInt = { 115 require(nSets >= 1) 116 require(vpn.getWidth > log2Ceil(nSets)) 117 vpn(vpn.getWidth-1, log2Ceil(nSets)) 118 } 119 120 def drop_set_equal(vpn1: UInt, vpn2: UInt, nSets: Int): Bool = { 121 require(nSets >= 1) 122 require(vpn1.getWidth == vpn2.getWidth) 123 if (vpn1.getWidth <= log2Ceil(nSets)) { 124 true.B 125 } else { 126 drop_set_idx(vpn1, nSets) === drop_set_idx(vpn2, nSets) 127 } 128 } 129 130 def replaceWrapper(v: UInt, lruIdx: UInt): UInt = { 131 val width = v.getWidth 132 val emptyIdx = ParallelPriorityMux((0 until width).map( i => (!v(i), i.U(log2Up(width).W)))) 133 val full = Cat(v).andR 134 Mux(full, lruIdx, emptyIdx) 135 } 136 137 def replaceWrapper(v: Seq[Bool], lruIdx: UInt): UInt = { 138 replaceWrapper(VecInit(v).asUInt, lruIdx) 139 } 140 141 implicit def ptwresp_to_tlbperm(ptwResp: PtwSectorRespwithMemIdx): TlbPermBundle = { 142 val tp = Wire(new TlbPermBundle) 143 val ptePerm = ptwResp.entry.perm.get.asTypeOf(new PtePermBundle().cloneType) 144 tp.pf := ptwResp.pf 145 tp.af := ptwResp.af 146 tp.d := ptePerm.d 147 tp.a := ptePerm.a 148 tp.g := ptePerm.g 149 tp.u := ptePerm.u 150 tp.x := ptePerm.x 151 tp.w := ptePerm.w 152 tp.r := ptePerm.r 153 tp 154 } 155} 156 157trait HasPtwConst extends HasTlbConst with MemoryOpConstants{ 158 val PtwWidth = 2 159 val sourceWidth = { if (l2tlbParams.enablePrefetch) PtwWidth + 1 else PtwWidth} 160 val prefetchID = PtwWidth 161 162 val blockBits = l2tlbParams.blockBytes * 8 163 164 val bPtwWidth = log2Up(PtwWidth) 165 val bSourceWidth = log2Up(sourceWidth) 166 // ptwl1: fully-associated 167 val PtwL1TagLen = vpnnLen 168 169 /* +-------+----------+-------------+ 170 * | Tag | SetIdx | SectorIdx | 171 * +-------+----------+-------------+ 172 */ 173 // ptwl2: 8-way group-associated 174 val l2tlbParams.l2nWays = l2tlbParams.l2nWays 175 val PtwL2SetNum = l2tlbParams.l2nSets 176 val PtwL2SectorSize = blockBits / XLEN 177 val PtwL2IdxLen = log2Up(PtwL2SetNum * PtwL2SectorSize) 178 val PtwL2SectorIdxLen = log2Up(PtwL2SectorSize) 179 val PtwL2SetIdxLen = log2Up(PtwL2SetNum) 180 val PtwL2TagLen = vpnnLen * 2 - PtwL2IdxLen 181 182 // ptwl3: 16-way group-associated 183 val l2tlbParams.l3nWays = l2tlbParams.l3nWays 184 val PtwL3SetNum = l2tlbParams.l3nSets 185 val PtwL3SectorSize = blockBits / XLEN 186 val PtwL3IdxLen = log2Up(PtwL3SetNum * PtwL3SectorSize) 187 val PtwL3SectorIdxLen = log2Up(PtwL3SectorSize) 188 val PtwL3SetIdxLen = log2Up(PtwL3SetNum) 189 val PtwL3TagLen = vpnnLen * 3 - PtwL3IdxLen 190 191 // super page, including 1GB and 2MB page 192 val SPTagLen = vpnnLen * 2 193 194 // miss queue 195 val MissQueueSize = l2tlbParams.ifilterSize + l2tlbParams.dfilterSize 196 val MemReqWidth = l2tlbParams.llptwsize + 1 197 val FsmReqID = l2tlbParams.llptwsize 198 val bMemID = log2Up(MemReqWidth) 199 200 def genPtwL2Idx(vpn: UInt) = { 201 (vpn(vpnLen - 1, vpnnLen))(PtwL2IdxLen - 1, 0) 202 } 203 204 def genPtwL2SectorIdx(vpn: UInt) = { 205 genPtwL2Idx(vpn)(PtwL2SectorIdxLen - 1, 0) 206 } 207 208 def genPtwL2SetIdx(vpn: UInt) = { 209 genPtwL2Idx(vpn)(PtwL2SetIdxLen + PtwL2SectorIdxLen - 1, PtwL2SectorIdxLen) 210 } 211 212 def genPtwL3Idx(vpn: UInt) = { 213 vpn(PtwL3IdxLen - 1, 0) 214 } 215 216 def genPtwL3SectorIdx(vpn: UInt) = { 217 genPtwL3Idx(vpn)(PtwL3SectorIdxLen - 1, 0) 218 } 219 220 def dropL3SectorBits(vpn: UInt) = { 221 vpn(vpn.getWidth-1, PtwL3SectorIdxLen) 222 } 223 224 def genPtwL3SetIdx(vpn: UInt) = { 225 genPtwL3Idx(vpn)(PtwL3SetIdxLen + PtwL3SectorIdxLen - 1, PtwL3SectorIdxLen) 226 } 227 228 def MakeAddr(ppn: UInt, off: UInt) = { 229 require(off.getWidth == 9) 230 Cat(ppn, off, 0.U(log2Up(XLEN/8).W))(PAddrBits-1, 0) 231 } 232 233 def getVpnn(vpn: UInt, idx: Int): UInt = { 234 vpn(vpnnLen*(idx+1)-1, vpnnLen*idx) 235 } 236 237 def getVpnClip(vpn: UInt, level: Int) = { 238 // level 0 /* vpnn2 */ 239 // level 1 /* vpnn2 * vpnn1 */ 240 // level 2 /* vpnn2 * vpnn1 * vpnn0*/ 241 vpn(vpnLen - 1, (2 - level) * vpnnLen) 242 } 243 244 def get_next_line(vpn: UInt) = { 245 Cat(dropL3SectorBits(vpn) + 1.U, 0.U(PtwL3SectorIdxLen.W)) 246 } 247 248 def same_l2entry(vpn1: UInt, vpn2: UInt) = { 249 vpn1(vpnLen-1, vpnnLen) === vpn2(vpnLen-1, vpnnLen) 250 } 251 252 def from_pre(source: UInt) = { 253 (source === prefetchID.U) 254 } 255 256 def sel_data(data: UInt, index: UInt): UInt = { 257 val inner_data = data.asTypeOf(Vec(data.getWidth / XLEN, UInt(XLEN.W))) 258 inner_data(index) 259 } 260 261 // vpn1 and vpn2 is at same cacheline 262 def dup(vpn1: UInt, vpn2: UInt): Bool = { 263 dropL3SectorBits(vpn1) === dropL3SectorBits(vpn2) 264 } 265 266 267 def printVec[T <: Data](x: Seq[T]): Printable = { 268 (0 until x.length).map(i => p"(${i.U})${x(i)} ").reduce(_+_) 269 } 270} 271