1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: 9* http://license.coscl.org.cn/MulanPSL2 10* 11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14* 15* See the Mulan PSL v2 for more details. 16***************************************************************************************/ 17 18package xiangshan.cache.mmu 19 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import xiangshan._ 24import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 25import utils._ 26import utility._ 27import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 28import freechips.rocketchip.tilelink._ 29 30 31case class TLBParameters 32( 33 name: String = "none", 34 fetchi: Boolean = false, // TODO: remove it 35 fenceDelay: Int = 2, 36 useDmode: Boolean = true, 37 NSets: Int = 1, 38 NWays: Int = 2, 39 Replacer: Option[String] = Some("plru"), 40 Associative: String = "fa", // must be fa 41 outReplace: Boolean = false, 42 partialStaticPMP: Boolean = false, // partial static pmp result stored in entries 43 outsideRecvFlush: Boolean = false, // if outside moudle waiting for tlb recv flush pipe 44 saveLevel: Boolean = false, 45 lgMaxSize: Int = 3 46) 47 48case class L2TLBParameters 49( 50 name: String = "l2tlb", 51 // l3 52 l3Size: Int = 16, 53 l3Associative: String = "fa", 54 l3Replacer: Option[String] = Some("plru"), 55 // l2 56 l2Size: Int = 16, 57 l2Associative: String = "fa", 58 l2Replacer: Option[String] = Some("plru"), 59 // l1 60 l1nSets: Int = 8, 61 l1nWays: Int = 2, 62 l1ReservedBits: Int = 10, 63 l1Replacer: Option[String] = Some("setplru"), 64 // l0 65 l0nSets: Int = 32, 66 l0nWays: Int = 4, 67 l0ReservedBits: Int = 3, 68 l0Replacer: Option[String] = Some("setplru"), 69 // sp 70 spSize: Int = 16, 71 spReplacer: Option[String] = Some("plru"), 72 // hash asid width 73 hashAsidWidth: Int = 3, 74 // hash vpn width 75 hashVpnWidth: Int = 6, 76 // filter 77 ifilterSize: Int = 8, 78 dfilterSize: Int = 32, 79 // miss queue, add more entries than 'must require' 80 // 0 for easier bug trigger, please set as big as u can, 8 maybe 81 missqueueExtendSize: Int = 0, 82 // llptw 83 llptwsize: Int = 6, 84 // way size 85 blockBytes: Int = 64, 86 // prefetch 87 enablePrefetch: Boolean = true, 88 // ecc 89 ecc: Option[String] = Some("secded"), 90 // enable ecc 91 enablePTWECC: Boolean = false 92) 93 94trait HasTlbConst extends HasXSParameter { 95 val Level = if (EnableSv48) 3 else 2 96 97 val offLen = 12 98 val ppnLen = PAddrBits - offLen 99 val vpnnLen = 9 100 val extendVpnnBits = if (HasHExtension) 2 else 0 101 val vpnLen = VAddrBits - offLen // when opening H extention, vpnlen broaden two bits 102 /* 103 Sv39 page table entry 104 +--+------+--------+----------------------+-----+--------+ 105 |63|62 61|60 54|53 10|9 8|7 0| 106 +--+------+--------+----------------------+-----+--------+ 107 |N | PBMT |Reserved| PPNs | RSW | FALG | 108 +--+------+--------+----------------------+-----+--------+ 109 */ 110 val pteFlagLen = 8 111 val pteRswLen = 2 112 val ptePPNLen = 44 113 val pteResLen = 7 114 val ptePbmtLen = 2 115 val pteNLen = 1 116 val pteNapotBits = 4 117 val ppnHignLen = ptePPNLen - ppnLen 118 val gvpnLen = GPAddrBits - offLen 119 120 val tlbcontiguous = 8 121 val sectortlbwidth = log2Up(tlbcontiguous) 122 val sectorppnLen = ppnLen - sectortlbwidth 123 val sectorgvpnLen = gvpnLen - sectortlbwidth 124 val sectorvpnLen = vpnLen - sectortlbwidth 125 val sectorptePPNLen = ptePPNLen - sectortlbwidth 126 127 val loadfiltersize = 16 // 4*3(LduCnt:2 + HyuCnt:1) + 4(prefetch:1) 128 val storefiltersize = if (StorePipelineWidth >= 3) 16 else 8 129 val prefetchfiltersize = 8 130 131 val sramSinglePort = true 132 133 val timeOutThreshold = 100000 134 135 def noS2xlate = "b00".U 136 def allStage = "b11".U 137 def onlyStage1 = "b01".U 138 def onlyStage2 = "b10".U 139 140 def Sv39 = "h8".U 141 def Sv48 = "h9".U 142 143 def Sv39x4 = "h8".U 144 def Sv48x4 = "h9".U 145 146 def PMLEN7 = "b10".U 147 def PMLEN16 = "b11".U 148 def MaxMaskedWidth = 16 149 150 def get_pn(addr: UInt) = { 151 require(addr.getWidth > offLen) 152 addr(addr.getWidth-1, offLen) 153 } 154 def get_off(addr: UInt) = { 155 require(addr.getWidth > offLen) 156 addr(offLen-1, 0) 157 } 158 159 def get_set_idx(vpn: UInt, nSets: Int): UInt = { 160 require(nSets >= 1) 161 vpn(log2Up(nSets)-1, 0) 162 } 163 164 def drop_set_idx(vpn: UInt, nSets: Int): UInt = { 165 require(nSets >= 1) 166 require(vpn.getWidth > log2Ceil(nSets)) 167 vpn(vpn.getWidth-1, log2Ceil(nSets)) 168 } 169 170 def drop_set_equal(vpn1: UInt, vpn2: UInt, nSets: Int): Bool = { 171 require(nSets >= 1) 172 require(vpn1.getWidth == vpn2.getWidth) 173 if (vpn1.getWidth <= log2Ceil(nSets)) { 174 true.B 175 } else { 176 drop_set_idx(vpn1, nSets) === drop_set_idx(vpn2, nSets) 177 } 178 } 179 180 def replaceWrapper(v: UInt, lruIdx: UInt): UInt = { 181 val width = v.getWidth 182 val emptyIdx = ParallelPriorityMux((0 until width).map( i => (!v(i), i.U(log2Up(width).W)))) 183 val full = Cat(v).andR 184 Mux(full, lruIdx, emptyIdx) 185 } 186 187 def replaceWrapper(v: Seq[Bool], lruIdx: UInt): UInt = { 188 replaceWrapper(VecInit(v).asUInt, lruIdx) 189 } 190 191 import scala.language.implicitConversions 192 193 implicit def hptwresp_to_tlbperm(hptwResp: HptwResp): TlbPermBundle = { 194 val tp = Wire(new TlbPermBundle) 195 val ptePerm = hptwResp.entry.perm.get.asTypeOf(new PtePermBundle().cloneType) 196 tp.pf := hptwResp.gpf 197 tp.af := hptwResp.gaf 198 tp.v := DontCare 199 tp.d := ptePerm.d 200 tp.a := ptePerm.a 201 tp.g := ptePerm.g 202 tp.u := ptePerm.u 203 tp.x := ptePerm.x 204 tp.w := ptePerm.w 205 tp.r := ptePerm.r 206 tp 207 } 208 209 implicit def ptwresp_to_tlbperm(ptwResp: PtwSectorResp): TlbPermBundle = { 210 val tp = Wire(new TlbPermBundle) 211 val ptePerm = ptwResp.entry.perm.get.asTypeOf(new PtePermBundle().cloneType) 212 tp.pf := ptwResp.pf 213 tp.af := ptwResp.af 214 tp.v := ptwResp.entry.v 215 tp.d := ptePerm.d 216 tp.a := ptePerm.a 217 tp.g := ptePerm.g 218 tp.u := ptePerm.u 219 tp.x := ptePerm.x 220 tp.w := ptePerm.w 221 tp.r := ptePerm.r 222 tp 223 } 224} 225 226trait HasPtwConst extends HasTlbConst with MemoryOpConstants{ 227 val PtwWidth = 2 228 val sourceWidth = { if (l2tlbParams.enablePrefetch) PtwWidth + 1 else PtwWidth} 229 val prefetchID = PtwWidth 230 231 val blockBits = l2tlbParams.blockBytes * 8 232 233 val bPtwWidth = log2Up(PtwWidth) 234 val bSourceWidth = log2Up(sourceWidth) 235 // ptwl3: fully-associated 236 val PtwL3TagLen = if (EnableSv48) vpnnLen + extendVpnnBits else 0 237 // ptwl2: fully-associated 238 val PtwL2TagLen = if (EnableSv48) vpnnLen * 2 + extendVpnnBits else vpnnLen + extendVpnnBits 239 240 /* +-------+----------+-------------+ 241 * | Tag | SetIdx | SectorIdx | 242 * +-------+----------+-------------+ 243 */ 244 // ptwl1: 8-way group-associated 245 val PtwL1SetNum = l2tlbParams.l1nSets 246 val PtwL1SectorSize = blockBits / XLEN 247 val PtwL1IdxLen = log2Up(PtwL1SetNum * PtwL1SectorSize) 248 val PtwL1SectorIdxLen = log2Up(PtwL1SectorSize) 249 val PtwL1SetIdxLen = log2Up(PtwL1SetNum) 250 val PtwL1TagLen = if (EnableSv48) vpnnLen * 3 - PtwL1IdxLen + extendVpnnBits else vpnnLen * 2 - PtwL1IdxLen + extendVpnnBits 251 252 // ptwl0: 16-way group-associated 253 val PtwL0SetNum = l2tlbParams.l0nSets 254 val PtwL0SectorSize = blockBits / XLEN 255 val PtwL0IdxLen = log2Up(PtwL0SetNum * PtwL0SectorSize) 256 val PtwL0SectorIdxLen = log2Up(PtwL0SectorSize) 257 val PtwL0SetIdxLen = log2Up(PtwL0SetNum) 258 val PtwL0TagLen = if (EnableSv48) vpnnLen * 4 - PtwL0IdxLen + extendVpnnBits else vpnnLen * 3 - PtwL0IdxLen + extendVpnnBits 259 260 // super page, including 512GB, 1GB, 2MB page && Svnapot page 261 val SPTagLen = if (EnableSv48) vpnnLen * 4 + extendVpnnBits else vpnnLen * 3 + extendVpnnBits 262 263 // miss queue 264 val MissQueueSize = l2tlbParams.ifilterSize + l2tlbParams.dfilterSize 265 val MemReqWidth = if (HasBitmapCheck) 2 *(l2tlbParams.llptwsize + 1 + 1) else (l2tlbParams.llptwsize + 1 + 1) 266 val HptwReqId = l2tlbParams.llptwsize + 1 267 val FsmReqID = l2tlbParams.llptwsize 268 val bMemID = log2Up(MemReqWidth) 269 270 def ptwTranVec(flushMask: UInt): Vec[Bool] = { 271 val vec = Wire(Vec(tlbcontiguous, Bool())) 272 for (i <- 0 until tlbcontiguous) { 273 vec(i) := flushMask(i) 274 } 275 vec 276 } 277 278 def dupBitmapPPN(ppn1: UInt, ppn2: UInt) : Bool = { 279 ppn1(ppnLen-1, ppnLen-log2Up(XLEN)) === ppn2(ppnLen-1, ppnLen-log2Up(XLEN)) 280 } 281 282 def genPtwL1Idx(vpn: UInt) = { 283 (vpn(vpnLen - 1, vpnnLen))(PtwL1IdxLen - 1, 0) 284 } 285 286 def genPtwL1SectorIdx(vpn: UInt) = { 287 genPtwL1Idx(vpn)(PtwL1SectorIdxLen - 1, 0) 288 } 289 290 def genPtwL1SetIdx(vpn: UInt) = { 291 genPtwL1Idx(vpn)(PtwL1SetIdxLen + PtwL1SectorIdxLen - 1, PtwL1SectorIdxLen) 292 } 293 294 def genPtwL0Idx(vpn: UInt) = { 295 vpn(PtwL0IdxLen - 1, 0) 296 } 297 298 def genPtwL0SectorIdx(vpn: UInt) = { 299 genPtwL0Idx(vpn)(PtwL0SectorIdxLen - 1, 0) 300 } 301 302 def dropL0SectorBits(vpn: UInt) = { 303 vpn(vpn.getWidth-1, PtwL0SectorIdxLen) 304 } 305 306 def genPtwL0SetIdx(vpn: UInt) = { 307 genPtwL0Idx(vpn)(PtwL0SetIdxLen + PtwL0SectorIdxLen - 1, PtwL0SectorIdxLen) 308 } 309 310 def MakeAddr(ppn: UInt, off: UInt) = { 311 require(off.getWidth == 9) 312 Cat(ppn, off, 0.U(log2Up(XLEN/8).W)) 313 } 314 315 def MakeGPAddr(ppn: UInt, off: UInt) = { 316 require(off.getWidth == 9 || off.getWidth == 11) 317 (Cat(ppn, 0.U(offLen.W)) + Cat(off, 0.U(log2Up(XLEN / 8).W)))(GPAddrBits - 1, 0) 318 } 319 320 def getVpnn(vpn: UInt, idx: Int): UInt = { 321 vpn(vpnnLen*(idx+1)-1, vpnnLen*idx) 322 } 323 324 def getVpnn(vpn: UInt, idx: UInt): UInt = { 325 MuxLookup(idx, 0.U)(Seq( 326 0.U -> vpn(vpnnLen - 1, 0), 327 1.U -> vpn(vpnnLen * 2 - 1, vpnnLen), 328 2.U -> vpn(vpnnLen * 3 - 1, vpnnLen * 2), 329 3.U -> vpn(vpnnLen * 4 - 1, vpnnLen * 3)) 330 ) 331 } 332 333 def getGVpnn(vpn: UInt, idx: UInt, mode: UInt): UInt = { 334 MuxLookup(idx, 0.U)(Seq( 335 0.U -> vpn(vpnnLen - 1, 0), 336 1.U -> vpn(vpnnLen * 2 - 1, vpnnLen), 337 2.U -> Mux(mode === Sv48, vpn(vpnnLen * 3 - 1, vpnnLen * 2), vpn(vpnnLen * 3 + 1, vpnnLen * 2)), 338 3.U -> vpn(vpnnLen * 4 + 1, vpnnLen * 3)) 339 ) 340 } 341 342 def getVpnClip(vpn: UInt, level: Int) = { 343 // level 2 /* vpnn2 */ 344 // level 1 /* vpnn2 * vpnn1 */ 345 // level 0 /* vpnn2 * vpnn1 * vpnn0*/ 346 vpn(vpnLen - 1, level * vpnnLen) 347 } 348 349 def get_next_line(vpn: UInt) = { 350 Cat(dropL0SectorBits(vpn) + 1.U, 0.U(PtwL0SectorIdxLen.W)) 351 } 352 353 def same_l1entry(vpn1: UInt, vpn2: UInt) = { 354 vpn1(vpnLen-1, vpnnLen) === vpn2(vpnLen-1, vpnnLen) 355 } 356 357 def from_pre(source: UInt) = { 358 (source === prefetchID.U) 359 } 360 361 def sel_data(data: UInt, index: UInt): UInt = { 362 val inner_data = data.asTypeOf(Vec(data.getWidth / XLEN, UInt(XLEN.W))) 363 inner_data(index) 364 } 365 366 // vpn1 and vpn2 is at same cacheline 367 def dup(vpn1: UInt, vpn2: UInt): Bool = { 368 dropL0SectorBits(vpn1) === dropL0SectorBits(vpn2) 369 } 370 371 372 def printVec[T <: Data](x: Seq[T]): Printable = { 373 (0 until x.length).map(i => p"(${i.U})${x(i)} ").reduce(_+_) 374 } 375} 376