1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 24import utils._ 25import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 26import freechips.rocketchip.tilelink._ 27 28case class TLBParameters 29( 30 name: String = "none", 31 fetchi: Boolean = false, // TODO: remove it 32 useDmode: Boolean = true, 33 sameCycle: Boolean = false, 34 missSameCycle: Boolean = false, 35 normalNSets: Int = 1, // when da or sa 36 normalNWays: Int = 8, // when fa or sa 37 superNSets: Int = 1, 38 superNWays: Int = 2, 39 normalReplacer: Option[String] = Some("random"), 40 superReplacer: Option[String] = Some("plru"), 41 normalAssociative: String = "fa", // "fa", "sa", "da", "sa" is not supported 42 superAssociative: String = "fa", // must be fa 43 normalAsVictim: Boolean = false, // when get replace from fa, store it into sram 44 outReplace: Boolean = false, 45 shouldBlock: Boolean = false, // only for perf, not support for io 46 partialStaticPMP: Boolean = false, // partila static pmp result stored in entries 47 saveLevel: Boolean = false 48) 49 50case class L2TLBParameters 51( 52 name: String = "l2tlb", 53 // l1 54 l1Size: Int = 16, 55 l1Associative: String = "fa", 56 l1Replacer: Option[String] = Some("plru"), 57 // l2 58 l2nSets: Int = 32, 59 l2nWays: Int = 2, 60 l2Replacer: Option[String] = Some("setplru"), 61 // l3 62 l3nSets: Int = 128, 63 l3nWays: Int = 4, 64 l3Replacer: Option[String] = Some("setplru"), 65 // sp 66 spSize: Int = 16, 67 spReplacer: Option[String] = Some("plru"), 68 // dtlb filter 69 filterSize: Int = 8, 70 // miss queue, add more entries than 'must require' 71 // 0 for easier bug trigger, please set as big as u can, 8 maybe 72 missqueueExtendSize: Int = 0, 73 // way size 74 blockBytes: Int = 64, 75 // prefetch 76 enablePrefetch: Boolean = true, 77 // ecc 78 ecc: Option[String] = Some("secded") 79) 80 81trait HasTlbConst extends HasXSParameter { 82 val Level = 3 83 84 val offLen = 12 85 val ppnLen = PAddrBits - offLen 86 val vpnnLen = 9 87 val vpnLen = VAddrBits - offLen 88 val flagLen = 8 89 val pteResLen = XLEN - ppnLen - 2 - flagLen 90 91 val sramSinglePort = true 92 93 val timeOutThreshold = 10000 94 95 def get_set_idx(vpn: UInt, nSets: Int): UInt = { 96 require(nSets >= 1) 97 vpn(log2Up(nSets)-1, 0) 98 } 99 100 def drop_set_idx(vpn: UInt, nSets: Int): UInt = { 101 require(nSets >= 1) 102 require(vpn.getWidth > log2Ceil(nSets)) 103 vpn(vpn.getWidth-1, log2Ceil(nSets)) 104 } 105 106 def drop_set_equal(vpn1: UInt, vpn2: UInt, nSets: Int): Bool = { 107 require(nSets >= 1) 108 require(vpn1.getWidth == vpn2.getWidth) 109 if (vpn1.getWidth <= log2Ceil(nSets)) { 110 true.B 111 } else { 112 drop_set_idx(vpn1, nSets) === drop_set_idx(vpn2, nSets) 113 } 114 } 115 116 def replaceWrapper(v: UInt, lruIdx: UInt): UInt = { 117 val width = v.getWidth 118 val emptyIdx = ParallelPriorityMux((0 until width).map( i => (!v(i), i.U))) 119 val full = Cat(v).andR 120 Mux(full, lruIdx, emptyIdx) 121 } 122 123 def replaceWrapper(v: Seq[Bool], lruIdx: UInt): UInt = { 124 replaceWrapper(VecInit(v).asUInt, lruIdx) 125 } 126 127} 128 129trait HasPtwConst extends HasTlbConst with MemoryOpConstants{ 130 val PtwWidth = 2 131 val sourceWidth = { if (l2tlbParams.enablePrefetch) PtwWidth + 1 else PtwWidth} 132 val prefetchID = PtwWidth 133 val maxPrefetchNum = l2tlbParams.filterSize 134 135 val blockBits = l2tlbParams.blockBytes * 8 136 137 val bPtwWidth = log2Up(PtwWidth) 138 val bSourceWidth = log2Up(sourceWidth) 139 // ptwl1: fully-associated 140 val PtwL1TagLen = vpnnLen 141 142 /* +-------+----------+-------------+ 143 * | Tag | SetIdx | SectorIdx | 144 * +-------+----------+-------------+ 145 */ 146 // ptwl2: 8-way group-associated 147 val l2tlbParams.l2nWays = l2tlbParams.l2nWays 148 val PtwL2SetNum = l2tlbParams.l2nSets 149 val PtwL2SectorSize = blockBits /XLEN 150 val PtwL2IdxLen = log2Up(PtwL2SetNum * PtwL2SectorSize) 151 val PtwL2SectorIdxLen = log2Up(PtwL2SectorSize) 152 val PtwL2SetIdxLen = log2Up(PtwL2SetNum) 153 val PtwL2TagLen = vpnnLen * 2 - PtwL2IdxLen 154 155 // ptwl3: 16-way group-associated 156 val l2tlbParams.l3nWays = l2tlbParams.l3nWays 157 val PtwL3SetNum = l2tlbParams.l3nSets 158 val PtwL3SectorSize = blockBits / XLEN 159 val PtwL3IdxLen = log2Up(PtwL3SetNum * PtwL3SectorSize) 160 val PtwL3SectorIdxLen = log2Up(PtwL3SectorSize) 161 val PtwL3SetIdxLen = log2Up(PtwL3SetNum) 162 val PtwL3TagLen = vpnnLen * 3 - PtwL3IdxLen 163 164 // super page, including 1GB and 2MB page 165 val SPTagLen = vpnnLen * 2 166 167 // miss queue 168 val MSHRBaseSize = 1 + l2tlbParams.filterSize + l2tlbParams.missqueueExtendSize 169 val MSHRSize = { if (l2tlbParams.enablePrefetch) (MSHRBaseSize + 1) else MSHRBaseSize } 170 val MemReqWidth = MSHRSize + 1 171 val FsmReqID = MSHRSize 172 val bMemID = log2Up(MSHRSize + 1) 173 174 def genPtwL2Idx(vpn: UInt) = { 175 (vpn(vpnLen - 1, vpnnLen))(PtwL2IdxLen - 1, 0) 176 } 177 178 def genPtwL2SectorIdx(vpn: UInt) = { 179 genPtwL2Idx(vpn)(PtwL2SectorIdxLen - 1, 0) 180 } 181 182 def genPtwL2SetIdx(vpn: UInt) = { 183 genPtwL2Idx(vpn)(PtwL2SetIdxLen + PtwL2SectorIdxLen - 1, PtwL2SectorIdxLen) 184 } 185 186 def genPtwL3Idx(vpn: UInt) = { 187 vpn(PtwL3IdxLen - 1, 0) 188 } 189 190 def genPtwL3SectorIdx(vpn: UInt) = { 191 genPtwL3Idx(vpn)(PtwL3SectorIdxLen - 1, 0) 192 } 193 194 def dropL3SectorBits(vpn: UInt) = { 195 vpn(vpn.getWidth-1, PtwL3SectorIdxLen) 196 } 197 198 def genPtwL3SetIdx(vpn: UInt) = { 199 genPtwL3Idx(vpn)(PtwL3SetIdxLen + PtwL3SectorIdxLen - 1, PtwL3SectorIdxLen) 200 } 201 202 def MakeAddr(ppn: UInt, off: UInt) = { 203 require(off.getWidth == 9) 204 Cat(ppn, off, 0.U(log2Up(XLEN/8).W))(PAddrBits-1, 0) 205 } 206 207 def getVpnn(vpn: UInt, idx: Int): UInt = { 208 vpn(vpnnLen*(idx+1)-1, vpnnLen*idx) 209 } 210 211 def getVpnClip(vpn: UInt, level: Int) = { 212 // level 0 /* vpnn2 */ 213 // level 1 /* vpnn2 * vpnn1 */ 214 // level 2 /* vpnn2 * vpnn1 * vpnn0*/ 215 vpn(vpnLen - 1, (2 - level) * vpnnLen) 216 } 217 218 def get_next_line(vpn: UInt) = { 219 Cat(dropL3SectorBits(vpn) + 1.U, 0.U(PtwL3SectorIdxLen.W)) 220 } 221 222 def same_l2entry(vpn1: UInt, vpn2: UInt) = { 223 vpn1(vpnLen-1, vpnnLen) === vpn2(vpnLen-1, vpnnLen) 224 } 225 226 def from_pre(source: UInt) = { 227 (source === prefetchID.U) 228 } 229 230 def printVec[T <: Data](x: Seq[T]): Printable = { 231 (0 until x.length).map(i => p"(${i.U})${x(i)} ").reduce(_+_) 232 } 233} 234