1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: 9* http://license.coscl.org.cn/MulanPSL2 10* 11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14* 15* See the Mulan PSL v2 for more details. 16***************************************************************************************/ 17 18package xiangshan.cache.mmu 19 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import xiangshan._ 24import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 25import utils._ 26import utility._ 27import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 28import freechips.rocketchip.tilelink._ 29 30 31case class TLBParameters 32( 33 name: String = "none", 34 fetchi: Boolean = false, // TODO: remove it 35 fenceDelay: Int = 2, 36 useDmode: Boolean = true, 37 NSets: Int = 1, 38 NWays: Int = 2, 39 Replacer: Option[String] = Some("plru"), 40 Associative: String = "fa", // must be fa 41 outReplace: Boolean = false, 42 partialStaticPMP: Boolean = false, // partial static pmp result stored in entries 43 outsideRecvFlush: Boolean = false, // if outside moudle waiting for tlb recv flush pipe 44 saveLevel: Boolean = false, 45 lgMaxSize: Int = 3 46) 47 48case class L2TLBParameters 49( 50 name: String = "l2tlb", 51 // l3 52 l3Size: Int = 16, 53 l3Associative: String = "fa", 54 l3Replacer: Option[String] = Some("plru"), 55 // l2 56 l2Size: Int = 16, 57 l2Associative: String = "fa", 58 l2Replacer: Option[String] = Some("plru"), 59 // l1 60 l1nSets: Int = 8, 61 l1nWays: Int = 4, 62 l1Replacer: Option[String] = Some("setplru"), 63 // l0 64 l0nSets: Int = 32, 65 l0nWays: Int = 8, 66 l0Replacer: Option[String] = Some("setplru"), 67 // sp 68 spSize: Int = 16, 69 spReplacer: Option[String] = Some("plru"), 70 // filter 71 ifilterSize: Int = 8, 72 dfilterSize: Int = 32, 73 // miss queue, add more entries than 'must require' 74 // 0 for easier bug trigger, please set as big as u can, 8 maybe 75 missqueueExtendSize: Int = 0, 76 // llptw 77 llptwsize: Int = 6, 78 // way size 79 blockBytes: Int = 64, 80 // prefetch 81 enablePrefetch: Boolean = true, 82 // ecc 83 ecc: Option[String] = Some("secded"), 84 // enable ecc 85 enablePTWECC: Boolean = false 86) 87 88trait HasTlbConst extends HasXSParameter { 89 val Level = if (EnableSv48) 3 else 2 90 91 val offLen = 12 92 val ppnLen = PAddrBits - offLen 93 val vpnnLen = 9 94 val extendVpnnBits = if (HasHExtension) 2 else 0 95 val vpnLen = VAddrBits - offLen // when opening H extention, vpnlen broaden two bits 96 /* 97 Sv39 page table entry 98 +--+------+--------+----------------------+-----+--------+ 99 |63|62 61|60 54|53 10|9 8|7 0| 100 +--+------+--------+----------------------+-----+--------+ 101 |N | PBMT |Reserved| PPNs | RSW | FALG | 102 +--+------+--------+----------------------+-----+--------+ 103 */ 104 val pteFlagLen = 8 105 val pteRswLen = 2 106 val ptePPNLen = 44 107 val pteResLen = 7 108 val ptePbmtLen = 2 109 val pteNLen = 1 110 val ppnHignLen = ptePPNLen - ppnLen 111 val gvpnLen = GPAddrBits - offLen 112 113 val tlbcontiguous = 8 114 val sectortlbwidth = log2Up(tlbcontiguous) 115 val sectorppnLen = ppnLen - sectortlbwidth 116 val sectorgvpnLen = gvpnLen - sectortlbwidth 117 val sectorvpnLen = vpnLen - sectortlbwidth 118 val sectorptePPNLen = ptePPNLen - sectortlbwidth 119 120 val loadfiltersize = 16 // 4*3(LduCnt:2 + HyuCnt:1) + 4(prefetch:1) 121 val storefiltersize = if (StorePipelineWidth >= 3) 16 else 8 122 val prefetchfiltersize = 8 123 124 val sramSinglePort = true 125 126 val timeOutThreshold = 10000 127 128 def noS2xlate = "b00".U 129 def allStage = "b11".U 130 def onlyStage1 = "b01".U 131 def onlyStage2 = "b10".U 132 133 def Sv39 = "h8".U 134 def Sv48 = "h9".U 135 136 def Sv39x4 = "h8".U 137 def Sv48x4 = "h9".U 138 139 def get_pn(addr: UInt) = { 140 require(addr.getWidth > offLen) 141 addr(addr.getWidth-1, offLen) 142 } 143 def get_off(addr: UInt) = { 144 require(addr.getWidth > offLen) 145 addr(offLen-1, 0) 146 } 147 148 def get_set_idx(vpn: UInt, nSets: Int): UInt = { 149 require(nSets >= 1) 150 vpn(log2Up(nSets)-1, 0) 151 } 152 153 def drop_set_idx(vpn: UInt, nSets: Int): UInt = { 154 require(nSets >= 1) 155 require(vpn.getWidth > log2Ceil(nSets)) 156 vpn(vpn.getWidth-1, log2Ceil(nSets)) 157 } 158 159 def drop_set_equal(vpn1: UInt, vpn2: UInt, nSets: Int): Bool = { 160 require(nSets >= 1) 161 require(vpn1.getWidth == vpn2.getWidth) 162 if (vpn1.getWidth <= log2Ceil(nSets)) { 163 true.B 164 } else { 165 drop_set_idx(vpn1, nSets) === drop_set_idx(vpn2, nSets) 166 } 167 } 168 169 def replaceWrapper(v: UInt, lruIdx: UInt): UInt = { 170 val width = v.getWidth 171 val emptyIdx = ParallelPriorityMux((0 until width).map( i => (!v(i), i.U(log2Up(width).W)))) 172 val full = Cat(v).andR 173 Mux(full, lruIdx, emptyIdx) 174 } 175 176 def replaceWrapper(v: Seq[Bool], lruIdx: UInt): UInt = { 177 replaceWrapper(VecInit(v).asUInt, lruIdx) 178 } 179 180 import scala.language.implicitConversions 181 182 implicit def hptwresp_to_tlbperm(hptwResp: HptwResp): TlbPermBundle = { 183 val tp = Wire(new TlbPermBundle) 184 val ptePerm = hptwResp.entry.perm.get.asTypeOf(new PtePermBundle().cloneType) 185 tp.pf := hptwResp.gpf 186 tp.af := hptwResp.gaf 187 tp.d := ptePerm.d 188 tp.a := ptePerm.a 189 tp.g := ptePerm.g 190 tp.u := ptePerm.u 191 tp.x := ptePerm.x 192 tp.w := ptePerm.w 193 tp.r := ptePerm.r 194 tp 195 } 196 197 implicit def ptwresp_to_tlbperm(ptwResp: PtwSectorResp): TlbPermBundle = { 198 val tp = Wire(new TlbPermBundle) 199 val ptePerm = ptwResp.entry.perm.get.asTypeOf(new PtePermBundle().cloneType) 200 tp.pf := ptwResp.pf 201 tp.af := ptwResp.af 202 tp.d := ptePerm.d 203 tp.a := ptePerm.a 204 tp.g := ptePerm.g 205 tp.u := ptePerm.u 206 tp.x := ptePerm.x 207 tp.w := ptePerm.w 208 tp.r := ptePerm.r 209 tp 210 } 211} 212 213trait HasPtwConst extends HasTlbConst with MemoryOpConstants{ 214 val PtwWidth = 2 215 val sourceWidth = { if (l2tlbParams.enablePrefetch) PtwWidth + 1 else PtwWidth} 216 val prefetchID = PtwWidth 217 218 val blockBits = l2tlbParams.blockBytes * 8 219 220 val bPtwWidth = log2Up(PtwWidth) 221 val bSourceWidth = log2Up(sourceWidth) 222 // ptwl3: fully-associated 223 val PtwL3TagLen = if (EnableSv48) vpnnLen + extendVpnnBits else 0 224 // ptwl2: fully-associated 225 val PtwL2TagLen = if (EnableSv48) vpnnLen * 2 + extendVpnnBits else vpnnLen + extendVpnnBits 226 227 /* +-------+----------+-------------+ 228 * | Tag | SetIdx | SectorIdx | 229 * +-------+----------+-------------+ 230 */ 231 // ptwl1: 8-way group-associated 232 val PtwL1SetNum = l2tlbParams.l1nSets 233 val PtwL1SectorSize = blockBits / XLEN 234 val PtwL1IdxLen = log2Up(PtwL1SetNum * PtwL1SectorSize) 235 val PtwL1SectorIdxLen = log2Up(PtwL1SectorSize) 236 val PtwL1SetIdxLen = log2Up(PtwL1SetNum) 237 val PtwL1TagLen = if (EnableSv48) vpnnLen * 3 - PtwL1IdxLen + extendVpnnBits else vpnnLen * 2 - PtwL1IdxLen + extendVpnnBits 238 239 // ptwl0: 16-way group-associated 240 val PtwL0SetNum = l2tlbParams.l0nSets 241 val PtwL0SectorSize = blockBits / XLEN 242 val PtwL0IdxLen = log2Up(PtwL0SetNum * PtwL0SectorSize) 243 val PtwL0SectorIdxLen = log2Up(PtwL0SectorSize) 244 val PtwL0SetIdxLen = log2Up(PtwL0SetNum) 245 val PtwL0TagLen = if (EnableSv48) vpnnLen * 4 - PtwL0IdxLen + extendVpnnBits else vpnnLen * 3 - PtwL0IdxLen + extendVpnnBits 246 247 // super page, including 1GB and 2MB page 248 val SPTagLen = if (EnableSv48) vpnnLen * 3 + extendVpnnBits else vpnnLen * 2 + extendVpnnBits 249 250 // miss queue 251 val MissQueueSize = l2tlbParams.ifilterSize + l2tlbParams.dfilterSize 252 val MemReqWidth = l2tlbParams.llptwsize + 1 + 1 253 val HptwReqId = l2tlbParams.llptwsize + 1 254 val FsmReqID = l2tlbParams.llptwsize 255 val bMemID = log2Up(MemReqWidth) 256 257 def genPtwL1Idx(vpn: UInt) = { 258 (vpn(vpnLen - 1, vpnnLen))(PtwL1IdxLen - 1, 0) 259 } 260 261 def genPtwL1SectorIdx(vpn: UInt) = { 262 genPtwL1Idx(vpn)(PtwL1SectorIdxLen - 1, 0) 263 } 264 265 def genPtwL1SetIdx(vpn: UInt) = { 266 genPtwL1Idx(vpn)(PtwL1SetIdxLen + PtwL1SectorIdxLen - 1, PtwL1SectorIdxLen) 267 } 268 269 def genPtwL0Idx(vpn: UInt) = { 270 vpn(PtwL0IdxLen - 1, 0) 271 } 272 273 def genPtwL0SectorIdx(vpn: UInt) = { 274 genPtwL0Idx(vpn)(PtwL0SectorIdxLen - 1, 0) 275 } 276 277 def dropL0SectorBits(vpn: UInt) = { 278 vpn(vpn.getWidth-1, PtwL0SectorIdxLen) 279 } 280 281 def genPtwL0SetIdx(vpn: UInt) = { 282 genPtwL0Idx(vpn)(PtwL0SetIdxLen + PtwL0SectorIdxLen - 1, PtwL0SectorIdxLen) 283 } 284 285 def MakeAddr(ppn: UInt, off: UInt) = { 286 require(off.getWidth == 9) 287 Cat(ppn, off, 0.U(log2Up(XLEN/8).W)) 288 } 289 290 def MakeGPAddr(ppn: UInt, off: UInt) = { 291 require(off.getWidth == 9 || off.getWidth == 11) 292 (Cat(ppn, 0.U(offLen.W)) + Cat(off, 0.U(log2Up(XLEN / 8).W)))(GPAddrBits - 1, 0) 293 } 294 295 def getVpnn(vpn: UInt, idx: Int): UInt = { 296 vpn(vpnnLen*(idx+1)-1, vpnnLen*idx) 297 } 298 299 def getVpnn(vpn: UInt, idx: UInt): UInt = { 300 MuxLookup(idx, 0.U)(Seq( 301 0.U -> vpn(vpnnLen - 1, 0), 302 1.U -> vpn(vpnnLen * 2 - 1, vpnnLen), 303 2.U -> vpn(vpnnLen * 3 - 1, vpnnLen * 2), 304 3.U -> vpn(vpnnLen * 4 - 1, vpnnLen * 3)) 305 ) 306 } 307 308 def getGVpnn(vpn: UInt, idx: UInt, mode: UInt): UInt = { 309 MuxLookup(idx, 0.U)(Seq( 310 0.U -> vpn(vpnnLen - 1, 0), 311 1.U -> vpn(vpnnLen * 2 - 1, vpnnLen), 312 2.U -> Mux(mode === Sv48, vpn(vpnnLen * 3 - 1, vpnnLen * 2), vpn(vpnnLen * 3 + 1, vpnnLen * 2)), 313 3.U -> vpn(vpnnLen * 4 + 1, vpnnLen * 3)) 314 ) 315 } 316 317 def getVpnClip(vpn: UInt, level: Int) = { 318 // level 2 /* vpnn2 */ 319 // level 1 /* vpnn2 * vpnn1 */ 320 // level 0 /* vpnn2 * vpnn1 * vpnn0*/ 321 vpn(vpnLen - 1, level * vpnnLen) 322 } 323 324 def get_next_line(vpn: UInt) = { 325 Cat(dropL0SectorBits(vpn) + 1.U, 0.U(PtwL0SectorIdxLen.W)) 326 } 327 328 def same_l1entry(vpn1: UInt, vpn2: UInt) = { 329 vpn1(vpnLen-1, vpnnLen) === vpn2(vpnLen-1, vpnnLen) 330 } 331 332 def from_pre(source: UInt) = { 333 (source === prefetchID.U) 334 } 335 336 def sel_data(data: UInt, index: UInt): UInt = { 337 val inner_data = data.asTypeOf(Vec(data.getWidth / XLEN, UInt(XLEN.W))) 338 inner_data(index) 339 } 340 341 // vpn1 and vpn2 is at same cacheline 342 def dup(vpn1: UInt, vpn2: UInt): Bool = { 343 dropL0SectorBits(vpn1) === dropL0SectorBits(vpn2) 344 } 345 346 347 def printVec[T <: Data](x: Seq[T]): Printable = { 348 (0 until x.length).map(i => p"(${i.U})${x(i)} ").reduce(_+_) 349 } 350} 351