1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: 9* http://license.coscl.org.cn/MulanPSL2 10* 11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14* 15* See the Mulan PSL v2 for more details. 16***************************************************************************************/ 17 18package xiangshan.cache.mmu 19 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import xiangshan._ 24import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 25import utils._ 26import utility._ 27import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 28import freechips.rocketchip.tilelink._ 29 30 31case class TLBParameters 32( 33 name: String = "none", 34 fetchi: Boolean = false, // TODO: remove it 35 fenceDelay: Int = 2, 36 useDmode: Boolean = true, 37 NSets: Int = 1, 38 NWays: Int = 2, 39 Replacer: Option[String] = Some("plru"), 40 Associative: String = "fa", // must be fa 41 outReplace: Boolean = false, 42 partialStaticPMP: Boolean = false, // partial static pmp result stored in entries 43 outsideRecvFlush: Boolean = false, // if outside moudle waiting for tlb recv flush pipe 44 saveLevel: Boolean = false, 45 lgMaxSize: Int = 3 46) 47 48case class L2TLBParameters 49( 50 name: String = "l2tlb", 51 // l3 52 l3Size: Int = 16, 53 l3Associative: String = "fa", 54 l3Replacer: Option[String] = Some("plru"), 55 // l2 56 l2Size: Int = 16, 57 l2Associative: String = "fa", 58 l2Replacer: Option[String] = Some("plru"), 59 // l1 60 l1nSets: Int = 8, 61 l1nWays: Int = 2, 62 l1ReservedBits: Int = 10, 63 l1Replacer: Option[String] = Some("setplru"), 64 // l0 65 l0nSets: Int = 32, 66 l0nWays: Int = 4, 67 l0ReservedBits: Int = 3, 68 l0Replacer: Option[String] = Some("setplru"), 69 // sp 70 spSize: Int = 16, 71 spReplacer: Option[String] = Some("plru"), 72 // filter 73 ifilterSize: Int = 8, 74 dfilterSize: Int = 32, 75 // miss queue, add more entries than 'must require' 76 // 0 for easier bug trigger, please set as big as u can, 8 maybe 77 missqueueExtendSize: Int = 0, 78 // llptw 79 llptwsize: Int = 6, 80 // way size 81 blockBytes: Int = 64, 82 // prefetch 83 enablePrefetch: Boolean = true, 84 // ecc 85 ecc: Option[String] = Some("secded"), 86 // enable ecc 87 enablePTWECC: Boolean = false 88) 89 90trait HasTlbConst extends HasXSParameter { 91 val Level = if (EnableSv48) 3 else 2 92 93 val offLen = 12 94 val ppnLen = PAddrBits - offLen 95 val vpnnLen = 9 96 val extendVpnnBits = if (HasHExtension) 2 else 0 97 val vpnLen = VAddrBits - offLen // when opening H extention, vpnlen broaden two bits 98 /* 99 Sv39 page table entry 100 +--+------+--------+----------------------+-----+--------+ 101 |63|62 61|60 54|53 10|9 8|7 0| 102 +--+------+--------+----------------------+-----+--------+ 103 |N | PBMT |Reserved| PPNs | RSW | FALG | 104 +--+------+--------+----------------------+-----+--------+ 105 */ 106 val pteFlagLen = 8 107 val pteRswLen = 2 108 val ptePPNLen = 44 109 val pteResLen = 7 110 val ptePbmtLen = 2 111 val pteNLen = 1 112 val pteNapotBits = 4 113 val ppnHignLen = ptePPNLen - ppnLen 114 val gvpnLen = GPAddrBits - offLen 115 116 val tlbcontiguous = 8 117 val sectortlbwidth = log2Up(tlbcontiguous) 118 val sectorppnLen = ppnLen - sectortlbwidth 119 val sectorgvpnLen = gvpnLen - sectortlbwidth 120 val sectorvpnLen = vpnLen - sectortlbwidth 121 val sectorptePPNLen = ptePPNLen - sectortlbwidth 122 123 val loadfiltersize = 16 // 4*3(LduCnt:2 + HyuCnt:1) + 4(prefetch:1) 124 val storefiltersize = if (StorePipelineWidth >= 3) 16 else 8 125 val prefetchfiltersize = 8 126 127 val sramSinglePort = true 128 129 val timeOutThreshold = 100000 130 131 def noS2xlate = "b00".U 132 def allStage = "b11".U 133 def onlyStage1 = "b01".U 134 def onlyStage2 = "b10".U 135 136 def Sv39 = "h8".U 137 def Sv48 = "h9".U 138 139 def Sv39x4 = "h8".U 140 def Sv48x4 = "h9".U 141 142 def PMLEN7 = "b10".U 143 def PMLEN16 = "b11".U 144 def MaxMaskedWidth = 16 145 146 def get_pn(addr: UInt) = { 147 require(addr.getWidth > offLen) 148 addr(addr.getWidth-1, offLen) 149 } 150 def get_off(addr: UInt) = { 151 require(addr.getWidth > offLen) 152 addr(offLen-1, 0) 153 } 154 155 def get_set_idx(vpn: UInt, nSets: Int): UInt = { 156 require(nSets >= 1) 157 vpn(log2Up(nSets)-1, 0) 158 } 159 160 def drop_set_idx(vpn: UInt, nSets: Int): UInt = { 161 require(nSets >= 1) 162 require(vpn.getWidth > log2Ceil(nSets)) 163 vpn(vpn.getWidth-1, log2Ceil(nSets)) 164 } 165 166 def drop_set_equal(vpn1: UInt, vpn2: UInt, nSets: Int): Bool = { 167 require(nSets >= 1) 168 require(vpn1.getWidth == vpn2.getWidth) 169 if (vpn1.getWidth <= log2Ceil(nSets)) { 170 true.B 171 } else { 172 drop_set_idx(vpn1, nSets) === drop_set_idx(vpn2, nSets) 173 } 174 } 175 176 def replaceWrapper(v: UInt, lruIdx: UInt): UInt = { 177 val width = v.getWidth 178 val emptyIdx = ParallelPriorityMux((0 until width).map( i => (!v(i), i.U(log2Up(width).W)))) 179 val full = Cat(v).andR 180 Mux(full, lruIdx, emptyIdx) 181 } 182 183 def replaceWrapper(v: Seq[Bool], lruIdx: UInt): UInt = { 184 replaceWrapper(VecInit(v).asUInt, lruIdx) 185 } 186 187 import scala.language.implicitConversions 188 189 implicit def hptwresp_to_tlbperm(hptwResp: HptwResp): TlbPermBundle = { 190 val tp = Wire(new TlbPermBundle) 191 val ptePerm = hptwResp.entry.perm.get.asTypeOf(new PtePermBundle().cloneType) 192 tp.pf := hptwResp.gpf 193 tp.af := hptwResp.gaf 194 tp.v := DontCare 195 tp.d := ptePerm.d 196 tp.a := ptePerm.a 197 tp.g := ptePerm.g 198 tp.u := ptePerm.u 199 tp.x := ptePerm.x 200 tp.w := ptePerm.w 201 tp.r := ptePerm.r 202 tp 203 } 204 205 implicit def ptwresp_to_tlbperm(ptwResp: PtwSectorResp): TlbPermBundle = { 206 val tp = Wire(new TlbPermBundle) 207 val ptePerm = ptwResp.entry.perm.get.asTypeOf(new PtePermBundle().cloneType) 208 tp.pf := ptwResp.pf 209 tp.af := ptwResp.af 210 tp.v := ptwResp.entry.v 211 tp.d := ptePerm.d 212 tp.a := ptePerm.a 213 tp.g := ptePerm.g 214 tp.u := ptePerm.u 215 tp.x := ptePerm.x 216 tp.w := ptePerm.w 217 tp.r := ptePerm.r 218 tp 219 } 220} 221 222trait HasPtwConst extends HasTlbConst with MemoryOpConstants{ 223 val PtwWidth = 2 224 val sourceWidth = { if (l2tlbParams.enablePrefetch) PtwWidth + 1 else PtwWidth} 225 val prefetchID = PtwWidth 226 227 val blockBits = l2tlbParams.blockBytes * 8 228 229 val bPtwWidth = log2Up(PtwWidth) 230 val bSourceWidth = log2Up(sourceWidth) 231 // ptwl3: fully-associated 232 val PtwL3TagLen = if (EnableSv48) vpnnLen + extendVpnnBits else 0 233 // ptwl2: fully-associated 234 val PtwL2TagLen = if (EnableSv48) vpnnLen * 2 + extendVpnnBits else vpnnLen + extendVpnnBits 235 236 /* +-------+----------+-------------+ 237 * | Tag | SetIdx | SectorIdx | 238 * +-------+----------+-------------+ 239 */ 240 // ptwl1: 8-way group-associated 241 val PtwL1SetNum = l2tlbParams.l1nSets 242 val PtwL1SectorSize = blockBits / XLEN 243 val PtwL1IdxLen = log2Up(PtwL1SetNum * PtwL1SectorSize) 244 val PtwL1SectorIdxLen = log2Up(PtwL1SectorSize) 245 val PtwL1SetIdxLen = log2Up(PtwL1SetNum) 246 val PtwL1TagLen = if (EnableSv48) vpnnLen * 3 - PtwL1IdxLen + extendVpnnBits else vpnnLen * 2 - PtwL1IdxLen + extendVpnnBits 247 248 // ptwl0: 16-way group-associated 249 val PtwL0SetNum = l2tlbParams.l0nSets 250 val PtwL0SectorSize = blockBits / XLEN 251 val PtwL0IdxLen = log2Up(PtwL0SetNum * PtwL0SectorSize) 252 val PtwL0SectorIdxLen = log2Up(PtwL0SectorSize) 253 val PtwL0SetIdxLen = log2Up(PtwL0SetNum) 254 val PtwL0TagLen = if (EnableSv48) vpnnLen * 4 - PtwL0IdxLen + extendVpnnBits else vpnnLen * 3 - PtwL0IdxLen + extendVpnnBits 255 256 // super page, including 512GB, 1GB, 2MB page && Svnapot page 257 val SPTagLen = if (EnableSv48) vpnnLen * 4 + extendVpnnBits else vpnnLen * 3 + extendVpnnBits 258 259 // miss queue 260 val MissQueueSize = l2tlbParams.ifilterSize + l2tlbParams.dfilterSize 261 val MemReqWidth = if (HasBitmapCheck) 2 *(l2tlbParams.llptwsize + 1 + 1) else (l2tlbParams.llptwsize + 1 + 1) 262 val HptwReqId = l2tlbParams.llptwsize + 1 263 val FsmReqID = l2tlbParams.llptwsize 264 val bMemID = log2Up(MemReqWidth) 265 266 def ptwTranVec(flushMask: UInt): Vec[Bool] = { 267 val vec = Wire(Vec(tlbcontiguous, Bool())) 268 for (i <- 0 until tlbcontiguous) { 269 vec(i) := flushMask(i) 270 } 271 vec 272 } 273 274 def dupBitmapPPN(ppn1: UInt, ppn2: UInt) : Bool = { 275 ppn1(ppnLen-1, ppnLen-log2Up(XLEN)) === ppn2(ppnLen-1, ppnLen-log2Up(XLEN)) 276 } 277 278 def genPtwL1Idx(vpn: UInt) = { 279 (vpn(vpnLen - 1, vpnnLen))(PtwL1IdxLen - 1, 0) 280 } 281 282 def genPtwL1SectorIdx(vpn: UInt) = { 283 genPtwL1Idx(vpn)(PtwL1SectorIdxLen - 1, 0) 284 } 285 286 def genPtwL1SetIdx(vpn: UInt) = { 287 genPtwL1Idx(vpn)(PtwL1SetIdxLen + PtwL1SectorIdxLen - 1, PtwL1SectorIdxLen) 288 } 289 290 def genPtwL0Idx(vpn: UInt) = { 291 vpn(PtwL0IdxLen - 1, 0) 292 } 293 294 def genPtwL0SectorIdx(vpn: UInt) = { 295 genPtwL0Idx(vpn)(PtwL0SectorIdxLen - 1, 0) 296 } 297 298 def dropL0SectorBits(vpn: UInt) = { 299 vpn(vpn.getWidth-1, PtwL0SectorIdxLen) 300 } 301 302 def genPtwL0SetIdx(vpn: UInt) = { 303 genPtwL0Idx(vpn)(PtwL0SetIdxLen + PtwL0SectorIdxLen - 1, PtwL0SectorIdxLen) 304 } 305 306 def MakeAddr(ppn: UInt, off: UInt) = { 307 require(off.getWidth == 9) 308 Cat(ppn, off, 0.U(log2Up(XLEN/8).W)) 309 } 310 311 def MakeGPAddr(ppn: UInt, off: UInt) = { 312 require(off.getWidth == 9 || off.getWidth == 11) 313 (Cat(ppn, 0.U(offLen.W)) + Cat(off, 0.U(log2Up(XLEN / 8).W)))(GPAddrBits - 1, 0) 314 } 315 316 def getVpnn(vpn: UInt, idx: Int): UInt = { 317 vpn(vpnnLen*(idx+1)-1, vpnnLen*idx) 318 } 319 320 def getVpnn(vpn: UInt, idx: UInt): UInt = { 321 MuxLookup(idx, 0.U)(Seq( 322 0.U -> vpn(vpnnLen - 1, 0), 323 1.U -> vpn(vpnnLen * 2 - 1, vpnnLen), 324 2.U -> vpn(vpnnLen * 3 - 1, vpnnLen * 2), 325 3.U -> vpn(vpnnLen * 4 - 1, vpnnLen * 3)) 326 ) 327 } 328 329 def getGVpnn(vpn: UInt, idx: UInt, mode: UInt): UInt = { 330 MuxLookup(idx, 0.U)(Seq( 331 0.U -> vpn(vpnnLen - 1, 0), 332 1.U -> vpn(vpnnLen * 2 - 1, vpnnLen), 333 2.U -> Mux(mode === Sv48, vpn(vpnnLen * 3 - 1, vpnnLen * 2), vpn(vpnnLen * 3 + 1, vpnnLen * 2)), 334 3.U -> vpn(vpnnLen * 4 + 1, vpnnLen * 3)) 335 ) 336 } 337 338 def getVpnClip(vpn: UInt, level: Int) = { 339 // level 2 /* vpnn2 */ 340 // level 1 /* vpnn2 * vpnn1 */ 341 // level 0 /* vpnn2 * vpnn1 * vpnn0*/ 342 vpn(vpnLen - 1, level * vpnnLen) 343 } 344 345 def get_next_line(vpn: UInt) = { 346 Cat(dropL0SectorBits(vpn) + 1.U, 0.U(PtwL0SectorIdxLen.W)) 347 } 348 349 def same_l1entry(vpn1: UInt, vpn2: UInt) = { 350 vpn1(vpnLen-1, vpnnLen) === vpn2(vpnLen-1, vpnnLen) 351 } 352 353 def from_pre(source: UInt) = { 354 (source === prefetchID.U) 355 } 356 357 def sel_data(data: UInt, index: UInt): UInt = { 358 val inner_data = data.asTypeOf(Vec(data.getWidth / XLEN, UInt(XLEN.W))) 359 inner_data(index) 360 } 361 362 // vpn1 and vpn2 is at same cacheline 363 def dup(vpn1: UInt, vpn2: UInt): Bool = { 364 dropL0SectorBits(vpn1) === dropL0SectorBits(vpn2) 365 } 366 367 368 def printVec[T <: Data](x: Seq[T]): Printable = { 369 (0 until x.length).map(i => p"(${i.U})${x(i)} ").reduce(_+_) 370 } 371} 372