1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 24import utils._ 25import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 26import freechips.rocketchip.tilelink._ 27 28case class TLBParameters 29( 30 name: String = "none", 31 fetchi: Boolean = false, // TODO: remove it 32 useDmode: Boolean = true, 33 sameCycle: Boolean = false, 34 missSameCycle: Boolean = false, 35 normalNSets: Int = 1, // when da or sa 36 normalNWays: Int = 8, // when fa or sa 37 superNSets: Int = 1, 38 superNWays: Int = 2, 39 normalReplacer: Option[String] = Some("random"), 40 superReplacer: Option[String] = Some("plru"), 41 normalAssociative: String = "fa", // "fa", "sa", "da", "sa" is not supported 42 superAssociative: String = "fa", // must be fa 43 normalAsVictim: Boolean = false, // when get replace from fa, store it into sram 44 outReplace: Boolean = false, 45 shouldBlock: Boolean = false, // only for perf, not support for io 46 saveLevel: Boolean = false 47) 48 49case class L2TLBParameters 50( 51 name: String = "l2tlb", 52 // l1 53 l1Size: Int = 16, 54 l1Associative: String = "fa", 55 l1Replacer: Option[String] = Some("plru"), 56 // l2 57 l2nSets: Int = 32, 58 l2nWays: Int = 2, 59 l2Replacer: Option[String] = Some("setplru"), 60 // l3 61 l3nSets: Int = 128, 62 l3nWays: Int = 4, 63 l3Replacer: Option[String] = Some("setplru"), 64 // sp 65 spSize: Int = 16, 66 spReplacer: Option[String] = Some("plru"), 67 // dtlb filter 68 filterSize: Int = 8, 69 // miss queue, add more entries than 'must require' 70 // 0 for easier bug trigger, please set as big as u can, 8 maybe 71 missqueueExtendSize: Int = 0, 72 // way size 73 blockBytes: Int = 64, 74 // prefetch 75 enablePrefetch: Boolean = true, 76 // ecc 77 ecc: Option[String] = Some("secded") 78) 79 80trait HasTlbConst extends HasXSParameter { 81 val Level = 3 82 83 val offLen = 12 84 val ppnLen = PAddrBits - offLen 85 val vpnnLen = 9 86 val vpnLen = VAddrBits - offLen 87 val flagLen = 8 88 val pteResLen = XLEN - ppnLen - 2 - flagLen 89 90 val sramSinglePort = true 91 92 val timeOutThreshold = 5000 93 94 def get_set_idx(vpn: UInt, nSets: Int): UInt = { 95 require(nSets >= 1) 96 vpn(log2Up(nSets)-1, 0) 97 } 98 99 def drop_set_idx(vpn: UInt, nSets: Int): UInt = { 100 require(nSets >= 1) 101 require(vpn.getWidth > log2Ceil(nSets)) 102 vpn(vpn.getWidth-1, log2Ceil(nSets)) 103 } 104 105 def drop_set_equal(vpn1: UInt, vpn2: UInt, nSets: Int): Bool = { 106 require(nSets >= 1) 107 require(vpn1.getWidth == vpn2.getWidth) 108 if (vpn1.getWidth <= log2Ceil(nSets)) { 109 true.B 110 } else { 111 drop_set_idx(vpn1, nSets) === drop_set_idx(vpn2, nSets) 112 } 113 } 114 115 def replaceWrapper(v: UInt, lruIdx: UInt): UInt = { 116 val width = v.getWidth 117 val emptyIdx = ParallelPriorityMux((0 until width).map( i => (!v(i), i.U))) 118 val full = Cat(v).andR 119 Mux(full, lruIdx, emptyIdx) 120 } 121 122 def replaceWrapper(v: Seq[Bool], lruIdx: UInt): UInt = { 123 replaceWrapper(VecInit(v).asUInt, lruIdx) 124 } 125 126} 127 128trait HasPtwConst extends HasTlbConst with MemoryOpConstants{ 129 val PtwWidth = 2 130 val sourceWidth = { if (l2tlbParams.enablePrefetch) PtwWidth + 1 else PtwWidth} 131 val prefetchID = PtwWidth 132 val maxPrefetchNum = l2tlbParams.filterSize 133 134 val blockBits = l2tlbParams.blockBytes * 8 135 136 val bPtwWidth = log2Up(PtwWidth) 137 val bSourceWidth = log2Up(sourceWidth) 138 // ptwl1: fully-associated 139 val PtwL1TagLen = vpnnLen 140 141 /* +-------+----------+-------------+ 142 * | Tag | SetIdx | SectorIdx | 143 * +-------+----------+-------------+ 144 */ 145 // ptwl2: 8-way group-associated 146 val l2tlbParams.l2nWays = l2tlbParams.l2nWays 147 val PtwL2SetNum = l2tlbParams.l2nSets 148 val PtwL2SectorSize = blockBits /XLEN 149 val PtwL2IdxLen = log2Up(PtwL2SetNum * PtwL2SectorSize) 150 val PtwL2SectorIdxLen = log2Up(PtwL2SectorSize) 151 val PtwL2SetIdxLen = log2Up(PtwL2SetNum) 152 val PtwL2TagLen = vpnnLen * 2 - PtwL2IdxLen 153 154 // ptwl3: 16-way group-associated 155 val l2tlbParams.l3nWays = l2tlbParams.l3nWays 156 val PtwL3SetNum = l2tlbParams.l3nSets 157 val PtwL3SectorSize = blockBits / XLEN 158 val PtwL3IdxLen = log2Up(PtwL3SetNum * PtwL3SectorSize) 159 val PtwL3SectorIdxLen = log2Up(PtwL3SectorSize) 160 val PtwL3SetIdxLen = log2Up(PtwL3SetNum) 161 val PtwL3TagLen = vpnnLen * 3 - PtwL3IdxLen 162 163 // super page, including 1GB and 2MB page 164 val SPTagLen = vpnnLen * 2 165 166 // miss queue 167 val MSHRBaseSize = 1 + l2tlbParams.filterSize + l2tlbParams.missqueueExtendSize 168 val MSHRSize = { if (l2tlbParams.enablePrefetch) (MSHRBaseSize + 1) else MSHRBaseSize } 169 val MemReqWidth = MSHRSize + 1 170 val FsmReqID = MSHRSize 171 val bMemID = log2Up(MSHRSize + 1) 172 173 def genPtwL2Idx(vpn: UInt) = { 174 (vpn(vpnLen - 1, vpnnLen))(PtwL2IdxLen - 1, 0) 175 } 176 177 def genPtwL2SectorIdx(vpn: UInt) = { 178 genPtwL2Idx(vpn)(PtwL2SectorIdxLen - 1, 0) 179 } 180 181 def genPtwL2SetIdx(vpn: UInt) = { 182 genPtwL2Idx(vpn)(PtwL2SetIdxLen + PtwL2SectorIdxLen - 1, PtwL2SectorIdxLen) 183 } 184 185 def genPtwL3Idx(vpn: UInt) = { 186 vpn(PtwL3IdxLen - 1, 0) 187 } 188 189 def genPtwL3SectorIdx(vpn: UInt) = { 190 genPtwL3Idx(vpn)(PtwL3SectorIdxLen - 1, 0) 191 } 192 193 def dropL3SectorBits(vpn: UInt) = { 194 vpn(vpn.getWidth-1, PtwL3SectorIdxLen) 195 } 196 197 def genPtwL3SetIdx(vpn: UInt) = { 198 genPtwL3Idx(vpn)(PtwL3SetIdxLen + PtwL3SectorIdxLen - 1, PtwL3SectorIdxLen) 199 } 200 201 def MakeAddr(ppn: UInt, off: UInt) = { 202 require(off.getWidth == 9) 203 Cat(ppn, off, 0.U(log2Up(XLEN/8).W))(PAddrBits-1, 0) 204 } 205 206 def getVpnn(vpn: UInt, idx: Int): UInt = { 207 vpn(vpnnLen*(idx+1)-1, vpnnLen*idx) 208 } 209 210 def getVpnClip(vpn: UInt, level: Int) = { 211 // level 0 /* vpnn2 */ 212 // level 1 /* vpnn2 * vpnn1 */ 213 // level 2 /* vpnn2 * vpnn1 * vpnn0*/ 214 vpn(vpnLen - 1, (2 - level) * vpnnLen) 215 } 216 217 def get_next_line(vpn: UInt) = { 218 Cat(dropL3SectorBits(vpn) + 1.U, 0.U(PtwL3SectorIdxLen.W)) 219 } 220 221 def same_l2entry(vpn1: UInt, vpn2: UInt) = { 222 vpn1(vpnLen-1, vpnnLen) === vpn2(vpnLen-1, vpnnLen) 223 } 224 225 def from_pre(source: UInt) = { 226 (source === prefetchID.U) 227 } 228 229 def printVec[T <: Data](x: Seq[T]): Printable = { 230 (0 until x.length).map(i => p"(${i.U})${x(i)} ").reduce(_+_) 231 } 232} 233