1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import chisel3.internal.naming.chiselName 23import xiangshan._ 24import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 25import utils._ 26import utility._ 27import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 28import freechips.rocketchip.tilelink._ 29 30/** L2TLB Miss Queue 31 * delay slot for reqs that pde miss in page cache 32 * if pde hit in page cache, go to LLPTW instead. 33 */ 34class L2TlbMQBundle(implicit p: Parameters) extends L2TlbInnerBundle 35 36class L2TlbMQIO(implicit p: Parameters) extends MMUIOBaseBundle with HasPtwConst { 37 val in = Flipped(Decoupled(new L2TlbMQBundle())) 38 val out = Decoupled(new L2TlbMQBundle()) 39} 40 41class L2TlbMissQueue(implicit p: Parameters) extends XSModule with HasPtwConst { 42 require(MissQueueSize >= (l2tlbParams.ifilterSize + l2tlbParams.dfilterSize)) 43 val io = IO(new L2TlbMQIO()) 44 45 io.out <> Queue(io.in, MissQueueSize, flush = Some(io.sfence.valid || io.csr.satp.changed)) 46} 47