xref: /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/AsynchronousMetaArray.scala (revision 57bb43b5f11c3f1e89ac52f232fe73056b35d9bd) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.cache
18
19import freechips.rocketchip.tilelink.ClientMetadata
20import chipsalliance.rocketchip.config.Parameters
21import chisel3._
22import chisel3.util._
23import xiangshan.L1CacheErrorInfo
24import xiangshan.cache.CacheInstrucion._
25
26class Meta(implicit p: Parameters) extends DCacheBundle {
27  val coh = new ClientMetadata
28}
29
30object Meta {
31  def apply(meta: UInt)(implicit p: Parameters) = {
32    val m = Wire(new Meta)
33    m.coh := meta.asTypeOf(new ClientMetadata)
34    m
35  }
36}
37
38class MetaReadReq(implicit p: Parameters) extends DCacheBundle {
39  val idx = UInt(idxBits.W)
40  val way_en = UInt(nWays.W)
41}
42
43class MetaWriteReq(implicit p: Parameters) extends MetaReadReq {
44  val meta = new Meta
45}
46
47class ErrorWriteReq(implicit p: Parameters) extends MetaReadReq {
48  val error = Bool()
49}
50
51class AsynchronousMetaArray(readPorts: Int, writePorts: Int)(implicit p: Parameters) extends DCacheModule {
52  val io = IO(new Bundle() {
53    val read = Vec(readPorts, Flipped(DecoupledIO(new MetaReadReq)))
54    val resp = Output(Vec(readPorts, Vec(nWays, new Meta)))
55    val write = Vec(writePorts, Flipped(DecoupledIO(new MetaWriteReq)))
56  })
57
58  val meta_array = Reg(Vec(nSets, Vec(nWays, new Meta)))
59  when (reset.asBool()) {
60    meta_array := 0.U.asTypeOf(meta_array.cloneType)
61  }
62
63  (io.read.zip(io.resp)).zipWithIndex.foreach {
64    case ((read, resp), i) =>
65      read.ready := true.B
66      resp := RegEnable(meta_array(read.bits.idx), read.valid)
67  }
68
69  io.write.foreach {
70    case write =>
71      write.ready := true.B
72      write.bits.way_en.asBools.zipWithIndex.foreach {
73        case (wen, i) =>
74          when (write.valid && wen) {
75            meta_array(write.bits.idx)(i) := write.bits.meta
76          }
77      }
78  }
79}
80
81class ErrorArray(readPorts: Int, writePorts: Int)(implicit p: Parameters) extends DCacheModule {
82  val io = IO(new Bundle() {
83    val read = Vec(readPorts, Flipped(DecoupledIO(new MetaReadReq)))
84    val resp = Output(Vec(readPorts, Vec(nWays, Bool())))
85    val write = Vec(writePorts, Flipped(DecoupledIO(new ErrorWriteReq)))
86    // customized cache op port
87    // val cacheOp = Flipped(new L1CacheInnerOpIO)
88  })
89
90  val meta_array = Reg(Vec(nSets, Vec(nWays, Bool())))
91  when (reset.asBool()) {
92    meta_array := 0.U.asTypeOf(meta_array.cloneType)
93  }
94
95  io.read.zip(io.resp).foreach {
96    case (read, resp) =>
97      read.ready := true.B
98      resp := RegEnable(meta_array(read.bits.idx), read.valid)
99  }
100
101  io.write.foreach {
102    case write =>
103      write.ready := true.B
104      write.bits.way_en.asBools.zipWithIndex.foreach {
105        case (wen, i) =>
106          when (write.valid && wen) {
107            meta_array(write.bits.idx)(i) := write.bits.error
108          }
109      }
110  }
111}
112