1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils.XSDebug 23 24class AtomicsReplayEntry(implicit p: Parameters) extends DCacheModule 25{ 26 val io = IO(new Bundle { 27 val lsu = Flipped(new DCacheWordIOWithVaddr) 28 val pipe_req = Decoupled(new MainPipeReq) 29 val pipe_resp = Flipped(ValidIO(new MainPipeResp)) 30 31 val block_addr = Output(Valid(UInt())) 32 }) 33 34 val s_invalid :: s_pipe_req :: s_pipe_resp :: s_resp :: Nil = Enum(4) 35 val state = RegInit(s_invalid) 36 37 val req = Reg(new DCacheWordReqWithVaddr) 38 39 // assign default values to output signals 40 io.lsu.req.ready := state === s_invalid 41 io.lsu.resp.valid := false.B 42 io.lsu.resp.bits := DontCare 43 44 io.pipe_req.valid := false.B 45 io.pipe_req.bits := DontCare 46 47 io.block_addr.valid := state =/= s_invalid 48 io.block_addr.bits := req.addr 49 50 51 when (state =/= s_invalid) { 52 XSDebug("AtomicsReplayEntry: state: %d block_addr: %x\n", state, io.block_addr.bits) 53 } 54 55 // -------------------------------------------- 56 // s_invalid: receive requests 57 when (state === s_invalid) { 58 when (io.lsu.req.fire()) { 59 req := io.lsu.req.bits 60 state := s_pipe_req 61 } 62 } 63 64 // -------------------------------------------- 65 // replay 66 when (state === s_pipe_req) { 67 io.pipe_req.valid := true.B 68 69 val pipe_req = io.pipe_req.bits 70 pipe_req := DontCare 71 pipe_req.miss := false.B 72 pipe_req.probe := false.B 73 pipe_req.probe_need_data := false.B 74 pipe_req.source := AMO_SOURCE.U 75 pipe_req.cmd := req.cmd 76 pipe_req.addr := get_block_addr(req.addr) 77 pipe_req.vaddr := get_block_addr(req.vaddr) 78 pipe_req.word_idx := get_word(req.addr) 79 pipe_req.amo_data := req.data 80 pipe_req.amo_mask := req.mask 81 82 when (io.pipe_req.fire()) { 83 state := s_pipe_resp 84 assert(!io.pipe_req.bits.vaddr === 0.U) 85 } 86 } 87 88 val resp_data = Reg(UInt()) 89 val resp_id = Reg(UInt()) 90 when (state === s_pipe_resp) { 91 // when not miss 92 // everything is OK, simply send response back to sbuffer 93 // when miss and not replay 94 // wait for missQueue to handling miss and replaying our request 95 // when miss and replay 96 // req missed and fail to enter missQueue, manually replay it later 97 // TODO: add assertions: 98 // 1. add a replay delay counter? 99 // 2. when req gets into MissQueue, it should not miss any more 100 when (io.pipe_resp.fire()) { 101 when (io.pipe_resp.bits.miss) { 102 when (io.pipe_resp.bits.replay) { 103 state := s_pipe_req 104 } 105 } .otherwise { 106 resp_data := io.pipe_resp.bits.data 107 resp_id := io.pipe_resp.bits.id 108 state := s_resp 109 } 110 } 111 } 112 113 // -------------------------------------------- 114 when (state === s_resp) { 115 io.lsu.resp.valid := true.B 116 io.lsu.resp.bits := DontCare 117 io.lsu.resp.bits.data := resp_data 118 io.lsu.resp.bits.id := resp_id 119 120 when (io.lsu.resp.fire()) { 121 state := s_invalid 122 } 123 } 124 125 // debug output 126 when (io.lsu.req.fire()) { 127 io.lsu.req.bits.dump() 128 } 129 130 when (io.lsu.resp.fire()) { 131 io.lsu.resp.bits.dump() 132 } 133 134 when (io.pipe_req.fire()) { 135 io.pipe_req.bits.dump() 136 } 137 138 when (io.pipe_resp.fire()) { 139 io.pipe_resp.bits.dump() 140 } 141} 142