1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.tilelink.ClientMetadata 23import utils.{HasPerfEvents, XSDebug, XSPerfAccumulate} 24import xiangshan.L1CacheErrorInfo 25import xiangshan.cache.dcache.{DCacheWPU, IdealWPU} 26 27class LoadPipe(id: Int)(implicit p: Parameters) extends DCacheModule with HasPerfEvents { 28 val io = IO(new DCacheBundle { 29 // incoming requests 30 val lsu = Flipped(new DCacheLoadIO) 31 // req got nacked in stage 0? 32 val nack = Input(Bool()) 33 34 // meta and data array read port 35 val meta_read = DecoupledIO(new MetaReadReq) 36 val meta_resp = Input(Vec(nWays, new Meta)) 37 val extra_meta_resp = Input(Vec(nWays, new DCacheExtraMeta)) 38 39 val tag_read = DecoupledIO(new TagReadReq) 40 val tag_resp = Input(Vec(nWays, UInt(encTagBits.W))) 41 42 val banked_data_read = DecoupledIO(new L1BankedDataReadReq) 43 val banked_data_resp = Input(new L1BankedDataReadResult()) 44 val read_error_delayed = Input(Bool()) 45 46 // access bit update 47 val access_flag_write = DecoupledIO(new FlagMetaWriteReq) 48 49 // banked data read conflict 50 val bank_conflict_slow = Input(Bool()) 51 val bank_conflict_fast = Input(Bool()) 52 53 // send miss request to miss queue 54 val miss_req = DecoupledIO(new MissReq) 55 val miss_resp = Input(new MissResp) 56 57 // update state vec in replacement algo 58 val replace_access = ValidIO(new ReplacementAccessBundle) 59 // find the way to be replaced 60 val replace_way = new ReplacementWayReqIO 61 62 // load fast wakeup should be disabled when data read is not ready 63 val disable_ld_fast_wakeup = Input(Bool()) 64 65 // ecc error 66 val error = Output(new L1CacheErrorInfo()) 67 68 // // debug_ls_info 69 // val debug_s2_cache_miss = Bool() 70 }) 71 72 assert(RegNext(io.meta_read.ready)) 73 74 val s1_ready = Wire(Bool()) 75 val s2_ready = Wire(Bool()) 76 // LSU requests 77 // it you got nacked, you can directly passdown 78 val not_nacked_ready = io.meta_read.ready && io.tag_read.ready && s1_ready 79 val nacked_ready = true.B 80 81 // ready can wait for valid 82 io.lsu.req.ready := (!io.nack && not_nacked_ready) || (io.nack && nacked_ready) 83 io.meta_read.valid := io.lsu.req.fire() && !io.nack 84 io.tag_read.valid := io.lsu.req.fire() && !io.nack 85 86 val meta_read = io.meta_read.bits 87 val tag_read = io.tag_read.bits 88 89 // Tag read for new requests 90 meta_read.idx := get_idx(io.lsu.req.bits.addr) 91 meta_read.way_en := ~0.U(nWays.W) 92 // meta_read.tag := DontCare 93 94 tag_read.idx := get_idx(io.lsu.req.bits.addr) 95 tag_read.way_en := ~0.U(nWays.W) 96 97 // Pipeline 98 // -------------------------------------------------------------------------------- 99 // stage 0 100 // -------------------------------------------------------------------------------- 101 // read tag 102 103 val s0_valid = io.lsu.req.fire() 104 val s0_req = io.lsu.req.bits 105 val s0_fire = s0_valid && s1_ready 106 val s0_vaddr = s0_req.addr 107 val s0_replayCarry = s0_req.replayCarry 108 assert(RegNext(!(s0_valid && (s0_req.cmd =/= MemoryOpConstants.M_XRD && s0_req.cmd =/= MemoryOpConstants.M_PFR && s0_req.cmd =/= MemoryOpConstants.M_PFW))), "LoadPipe only accepts load req / softprefetch read or write!") 109 dump_pipeline_reqs("LoadPipe s0", s0_valid, s0_req) 110 111 // -------------------------------------------------------------------------------- 112 // stage 1 113 // -------------------------------------------------------------------------------- 114 // tag match, read data 115 116 val s1_valid = RegInit(false.B) 117 val s1_req = RegEnable(s0_req, s0_fire) 118 // in stage 1, load unit gets the physical address 119 val s1_paddr_dup_lsu = io.lsu.s1_paddr_dup_lsu 120 val s1_paddr_dup_dcache = io.lsu.s1_paddr_dup_dcache 121 // LSU may update the address from io.lsu.s1_paddr, which affects the bank read enable only. 122 val s1_vaddr = Cat(s1_req.addr(PAddrBits - 1, blockOffBits), io.lsu.s1_paddr_dup_lsu(blockOffBits - 1, 0)) 123 val s1_bank_oh = UIntToOH(addr_to_dcache_bank(s1_vaddr)) 124 val s1_nack = RegNext(io.nack) 125 val s1_nack_data = !io.banked_data_read.ready 126 val s1_fire = s1_valid && s2_ready 127 s1_ready := !s1_valid || s1_fire 128 129 when (s0_fire) { s1_valid := true.B } 130 .elsewhen (s1_fire) { s1_valid := false.B } 131 132 dump_pipeline_reqs("LoadPipe s1", s1_valid, s1_req) 133 134 // tag check 135 val meta_resp = io.meta_resp 136 val tag_resp = io.tag_resp.map(r => r(tagBits - 1, 0)) 137 def wayMap[T <: Data](f: Int => T) = VecInit((0 until nWays).map(f)) 138 139 // dcache side tag match 140 /* // just ideal situation 141 val idealWPU = Module(new IdealWPU) 142 val s1_vaddr_dup_dc = Wire(UInt(PAddrBits.W)) 143 s1_vaddr_dup_dc := RegEnable(s0_req.addr, s0_fire) 144 idealWPU.io.req.bits.vaddr := s1_vaddr_dup_dc 145 idealWPU.io.req.valid := true.B 146 idealWPU.io.idealIf.s1_tag_resp := tag_resp 147 idealWPU.io.idealIf.s1_meta_resp := meta_resp 148 idealWPU.io.idealIf.s1_real_tag := get_tag(s1_paddr_dup_dcache) 149 */ 150 // real wpu 151 val wpu = Module(new DCacheWPU) 152 // req in s0 153 wpu.io.req.bits.vaddr := s0_vaddr 154 wpu.io.req.bits.replayCarry := s0_replayCarry 155 wpu.io.req.valid := s0_valid 156 // check in s1 157 wpu.io.check.bits.s1_tag_resp := tag_resp 158 wpu.io.check.bits.s1_meta_resp := meta_resp 159 wpu.io.check.bits.s1_real_tag := get_tag(s1_paddr_dup_dcache) 160 wpu.io.check.valid := s1_valid 161 // correct in s2 162 val s2_wpu_pred_fail = wpu.io.s2_pred_fail 163 val s2_real_way_en = wpu.io.s2_real_way_en 164 165 // resp in s1 166 val s1_tag_match_way_dup_dc = Wire(UInt(nWays.W)) 167 val s1_tag_match_way_dup_lsu = Wire(UInt(nWays.W)) 168 when (wpu.io.resp.valid){ 169 s1_tag_match_way_dup_dc := wpu.io.resp.bits.predict_way_en 170 s1_tag_match_way_dup_lsu := wpu.io.resp.bits.predict_way_en 171 }.otherwise { 172 val s1_tag_eq_way_dup_dc = wayMap((w: Int) => tag_resp(w) === (get_tag(s1_paddr_dup_dcache))).asUInt 173 s1_tag_match_way_dup_dc := wayMap((w: Int) => s1_tag_eq_way_dup_dc(w) && meta_resp(w).coh.isValid()).asUInt 174 175 // lsu side tag match 176 val s1_tag_eq_way_dup_lsu = wayMap((w: Int) => tag_resp(w) === (get_tag(s1_paddr_dup_lsu))).asUInt 177 s1_tag_match_way_dup_lsu := wayMap((w: Int) => s1_tag_eq_way_dup_lsu(w) && meta_resp(w).coh.isValid()).asUInt 178 } 179 val s1_tag_match_dup_dc = s1_tag_match_way_dup_dc.orR 180 val s1_tag_match_dup_lsu = s1_tag_match_way_dup_lsu.orR 181 assert(RegNext(!s1_valid || PopCount(s1_tag_match_way_dup_dc) <= 1.U), "tag should not match with more than 1 way") 182 183 val s1_fake_meta = Wire(new Meta) 184// s1_fake_meta.tag := get_tag(s1_paddr_dup_dcache) 185 s1_fake_meta.coh := ClientMetadata.onReset 186 val s1_fake_tag = get_tag(s1_paddr_dup_dcache) 187 188 // when there are no tag match, we give it a Fake Meta 189 // this simplifies our logic in s2 stage 190 val s1_hit_meta = Mux(s1_tag_match_dup_dc, Mux1H(s1_tag_match_way_dup_dc, wayMap((w: Int) => meta_resp(w))), s1_fake_meta) 191 val s1_hit_coh = s1_hit_meta.coh 192 val s1_hit_error = Mux(s1_tag_match_dup_dc, Mux1H(s1_tag_match_way_dup_dc, wayMap((w: Int) => io.extra_meta_resp(w).error)), false.B) 193 val s1_hit_prefetch = Mux(s1_tag_match_dup_dc, Mux1H(s1_tag_match_way_dup_dc, wayMap((w: Int) => io.extra_meta_resp(w).prefetch)), false.B) 194 val s1_hit_access = Mux(s1_tag_match_dup_dc, Mux1H(s1_tag_match_way_dup_dc, wayMap((w: Int) => io.extra_meta_resp(w).access)), false.B) 195 196 io.replace_way.set.valid := RegNext(s0_fire) 197 io.replace_way.set.bits := get_idx(s1_vaddr) 198 val s1_repl_way_en = UIntToOH(io.replace_way.way) 199 val s1_repl_tag = Mux1H(s1_repl_way_en, wayMap(w => tag_resp(w))) 200 val s1_repl_coh = Mux1H(s1_repl_way_en, wayMap(w => meta_resp(w).coh)) 201 val s1_repl_extra_meta = Mux1H(s1_repl_way_en, wayMap(w => io.extra_meta_resp(w))) 202 203 val s1_need_replacement = !s1_tag_match_dup_dc 204 val s1_way_en = Mux(s1_need_replacement, s1_repl_way_en, s1_tag_match_way_dup_dc) 205 val s1_coh = Mux(s1_need_replacement, s1_repl_coh, s1_hit_coh) 206 val s1_tag = Mux(s1_need_replacement, s1_repl_tag, get_tag(s1_paddr_dup_dcache)) 207 208 // data read 209 io.banked_data_read.valid := s1_fire && !s1_nack 210 io.banked_data_read.bits.addr := s1_vaddr 211 io.banked_data_read.bits.way_en := s1_tag_match_way_dup_dc 212 213 // get s1_will_send_miss_req in lpad_s1 214 val s1_has_permission = s1_hit_coh.onAccess(s1_req.cmd)._1 215 val s1_new_hit_coh = s1_hit_coh.onAccess(s1_req.cmd)._3 216 val s1_hit = s1_tag_match_dup_dc && s1_has_permission && s1_hit_coh === s1_new_hit_coh 217 val s1_will_send_miss_req = s1_valid && !s1_nack && !s1_nack_data && !s1_hit 218 219 // check ecc error 220 val s1_encTag = Mux1H(s1_tag_match_way_dup_dc, wayMap((w: Int) => io.tag_resp(w))) 221 val s1_flag_error = Mux(s1_need_replacement, false.B, s1_hit_error) // error reported by exist dcache error bit 222 223 // -------------------------------------------------------------------------------- 224 // stage 2 225 // -------------------------------------------------------------------------------- 226 // return data 227 228 // val s2_valid = RegEnable(next = s1_valid && !io.lsu.s1_kill, init = false.B, enable = s1_fire) 229 val s2_valid = RegInit(false.B) 230 val s2_req = RegEnable(s1_req, s1_fire) 231 val s2_paddr = RegEnable(s1_paddr_dup_dcache, s1_fire) 232 val s2_vaddr = RegEnable(s1_vaddr, s1_fire) 233 val s2_bank_oh = RegEnable(s1_bank_oh, s1_fire) 234 val s2_bank_oh_dup_0 = RegEnable(s1_bank_oh, s1_fire) 235 s2_ready := true.B 236 237 val s2_fire = s2_valid 238 239 when (s1_fire) { s2_valid := !io.lsu.s1_kill } 240 .elsewhen(io.lsu.resp.fire()) { s2_valid := false.B } 241 242 dump_pipeline_reqs("LoadPipe s2", s2_valid, s2_req) 243 244 245 // hit, miss, nack, permission checking 246 // dcache side tag match 247 val s2_tag_match_way = RegEnable(s1_tag_match_way_dup_dc, s1_fire) 248 val s2_tag_match = RegEnable(s1_tag_match_dup_dc, s1_fire) 249 250 // lsu side tag match 251 val s2_hit_dup_lsu = RegNext(s1_tag_match_dup_lsu) 252 253 io.lsu.s2_hit := s2_hit_dup_lsu && !s2_wpu_pred_fail 254 255 val s2_hit_meta = RegEnable(s1_hit_meta, s1_fire) 256 val s2_hit_coh = RegEnable(s1_hit_coh, s1_fire) 257 val s2_has_permission = s2_hit_coh.onAccess(s2_req.cmd)._1 // for write prefetch 258 val s2_new_hit_coh = s2_hit_coh.onAccess(s2_req.cmd)._3 // for write prefetch 259 260 val s2_way_en = RegEnable(s1_way_en, s1_fire) 261 val s2_repl_coh = RegEnable(s1_repl_coh, s1_fire) 262 val s2_repl_tag = RegEnable(s1_repl_tag, s1_fire) 263 val s2_repl_extra_meta = RegEnable(s1_repl_extra_meta, s1_fire) // not used for now 264 val s2_encTag = RegEnable(s1_encTag, s1_fire) 265 266 // when req got nacked, upper levels should replay this request 267 // nacked or not 268 val s2_nack_hit = RegEnable(s1_nack, s1_fire) 269 // can no allocate mshr for load miss 270 val s2_nack_no_mshr = io.miss_req.valid && !io.miss_req.ready 271 // Bank conflict on data arrays 272 val s2_nack_data = RegEnable(!io.banked_data_read.ready, s1_fire) 273 val s2_nack = s2_nack_hit || s2_nack_no_mshr || s2_nack_data 274 275 val s2_bank_addr = addr_to_dcache_bank(s2_paddr) 276 dontTouch(s2_bank_addr) 277 278 val s2_instrtype = s2_req.instrtype 279 280 val s2_tag_error = dcacheParameters.tagCode.decode(s2_encTag).error // error reported by tag ecc check 281 val s2_flag_error = RegEnable(s1_flag_error, s1_fire) 282 283 val s2_hit_prefetch = RegEnable(s1_hit_prefetch, s1_fire) 284 val s2_hit_access = RegEnable(s1_hit_access, s1_fire) 285 286 val s2_hit = s2_tag_match && s2_has_permission && s2_hit_coh === s2_new_hit_coh && !s2_wpu_pred_fail 287 288 // only dump these signals when they are actually valid 289 dump_pipeline_valids("LoadPipe s2", "s2_hit", s2_valid && s2_hit) 290 dump_pipeline_valids("LoadPipe s2", "s2_nack", s2_valid && s2_nack) 291 dump_pipeline_valids("LoadPipe s2", "s2_nack_hit", s2_valid && s2_nack_hit) 292 dump_pipeline_valids("LoadPipe s2", "s2_nack_no_mshr", s2_valid && s2_nack_no_mshr) 293 294 val s2_can_send_miss_req = RegEnable(s1_will_send_miss_req, s1_fire) 295 296 // send load miss to miss queue 297 io.miss_req.valid := s2_valid && s2_can_send_miss_req && !s2_wpu_pred_fail 298 io.miss_req.bits := DontCare 299 io.miss_req.bits.source := s2_instrtype 300 io.miss_req.bits.cmd := s2_req.cmd 301 io.miss_req.bits.addr := get_block_addr(s2_paddr) 302 io.miss_req.bits.vaddr := s2_vaddr 303 io.miss_req.bits.way_en := s2_way_en 304 io.miss_req.bits.req_coh := s2_hit_coh 305 io.miss_req.bits.replace_coh := s2_repl_coh 306 io.miss_req.bits.replace_tag := s2_repl_tag 307 io.miss_req.bits.cancel := io.lsu.s2_kill || s2_tag_error 308 io.miss_req.bits.pc := io.lsu.s2_pc 309 310 // send back response 311 val resp = Wire(ValidIO(new DCacheWordResp)) 312 resp.valid := s2_valid 313 resp.bits := DontCare 314 // resp.bits.data := s2_word_decoded 315 // resp.bits.data := banked_data_resp_word.raw_data 316 // * on miss or nack, upper level should replay request 317 // but if we successfully sent the request to miss queue 318 // upper level does not need to replay request 319 // they can sit in load queue and wait for refill 320 // 321 // * report a miss if bank conflict is detected 322 val real_miss = Wire(Bool()) 323 when (wpu.io.resp.valid){ 324 real_miss := s2_real_way_en.orR 325 }.otherwise{ 326 real_miss := !s2_hit_dup_lsu 327 } 328 // io.debug_s2_cache_miss := real_miss 329 resp.bits.miss := real_miss || io.bank_conflict_slow || s2_wpu_pred_fail 330 // load pipe need replay when there is a bank conflict or wpu predict fail 331 resp.bits.replay := (resp.bits.miss && (!io.miss_req.fire() || s2_nack)) || io.bank_conflict_slow || s2_wpu_pred_fail 332 resp.bits.replayCarry.valid := resp.bits.miss 333 resp.bits.replayCarry.real_way_en := s2_real_way_en 334 resp.bits.meta_prefetch := s2_hit_prefetch 335 resp.bits.meta_access := s2_hit_access 336 resp.bits.tag_error := s2_tag_error // report tag_error in load s2 337 resp.bits.mshr_id := io.miss_resp.id 338 339 XSPerfAccumulate("wpu_pred_fail", s2_wpu_pred_fail && s2_valid) 340 XSPerfAccumulate("dcache_read_bank_conflict", io.bank_conflict_slow && s2_valid) 341 XSPerfAccumulate("dcache_read_from_prefetched_line", s2_valid && s2_hit_prefetch && !resp.bits.miss) 342 XSPerfAccumulate("dcache_first_read_from_prefetched_line", s2_valid && s2_hit_prefetch && !resp.bits.miss && !s2_hit_access) 343 344 io.lsu.resp.valid := resp.valid 345 io.lsu.resp.bits := resp.bits 346 assert(RegNext(!(resp.valid && !io.lsu.resp.ready)), "lsu should be ready in s2") 347 348 when (resp.valid) { 349 resp.bits.dump() 350 } 351 352 io.lsu.debug_s1_hit_way := s1_tag_match_way_dup_dc 353 io.lsu.s1_disable_fast_wakeup := io.disable_ld_fast_wakeup 354 io.lsu.s1_bank_conflict := io.bank_conflict_fast 355 assert(RegNext(s1_ready && s2_ready), "load pipeline should never be blocked") 356 357 // -------------------------------------------------------------------------------- 358 // stage 3 359 // -------------------------------------------------------------------------------- 360 // report ecc error and get selected dcache data 361 362 val s3_valid = RegNext(s2_valid) 363 val s3_vaddr = RegEnable(s2_vaddr, s2_fire) 364 val s3_paddr = RegEnable(s2_paddr, s2_fire) 365 val s3_hit = RegEnable(s2_hit, s2_fire) 366 val s3_tag_match_way = RegEnable(s2_tag_match_way, s2_fire) 367 368 val s3_banked_data_resp_word = io.banked_data_resp.raw_data 369 val s3_data_error = io.read_error_delayed && s3_hit // banked_data_resp_word.error && !bank_conflict 370 val s3_tag_error = RegEnable(s2_tag_error, s2_fire) 371 val s3_flag_error = RegEnable(s2_flag_error, s2_fire) 372 val s3_error = s3_tag_error || s3_flag_error || s3_data_error 373 374 // error_delayed signal will be used to update uop.exception 1 cycle after load writeback 375 resp.bits.error_delayed := s3_error && (s3_hit || s3_tag_error) && s3_valid 376 resp.bits.data_delayed := s3_banked_data_resp_word 377 378 // report tag / data / l2 error (with paddr) to bus error unit 379 io.error := 0.U.asTypeOf(new L1CacheErrorInfo()) 380 io.error.report_to_beu := (s3_tag_error || s3_data_error) && s3_valid 381 io.error.paddr := s3_paddr 382 io.error.source.tag := s3_tag_error 383 io.error.source.data := s3_data_error 384 io.error.source.l2 := s3_flag_error 385 io.error.opType.load := true.B 386 // report tag error / l2 corrupted to CACHE_ERROR csr 387 io.error.valid := s3_error && s3_valid 388 389 // update plru in s3 390 io.replace_access.valid := RegNext(RegNext(RegNext(io.meta_read.fire()) && s1_valid && !io.lsu.s1_kill) && !s2_nack_no_mshr) 391 io.replace_access.bits.set := RegNext(RegNext(get_idx(s1_req.addr))) 392 io.replace_access.bits.way := RegNext(RegNext(Mux(s1_tag_match_dup_dc, OHToUInt(s1_tag_match_way_dup_dc), io.replace_way.way))) 393 394 // update access bit 395 io.access_flag_write.valid := s3_valid && s3_hit 396 io.access_flag_write.bits.idx := get_idx(s3_vaddr) 397 io.access_flag_write.bits.way_en := s3_tag_match_way 398 io.access_flag_write.bits.flag := true.B 399 400 // -------------------------------------------------------------------------------- 401 // Debug logging functions 402 def dump_pipeline_reqs(pipeline_stage_name: String, valid: Bool, 403 req: DCacheWordReq ) = { 404 when (valid) { 405 XSDebug(s"$pipeline_stage_name: ") 406 req.dump() 407 } 408 } 409 410 def dump_pipeline_valids(pipeline_stage_name: String, signal_name: String, valid: Bool) = { 411 when (valid) { 412 XSDebug(s"$pipeline_stage_name $signal_name\n") 413 } 414 } 415 416 // performance counters 417 XSPerfAccumulate("load_req", io.lsu.req.fire()) 418 XSPerfAccumulate("load_s1_kill", s1_fire && io.lsu.s1_kill) 419 XSPerfAccumulate("load_hit_way", s1_fire && s1_tag_match_dup_dc) 420 XSPerfAccumulate("load_replay", io.lsu.resp.fire() && resp.bits.replay) 421 XSPerfAccumulate("load_replay_for_data_nack", io.lsu.resp.fire() && resp.bits.replay && s2_nack_data) 422 XSPerfAccumulate("load_replay_for_no_mshr", io.lsu.resp.fire() && resp.bits.replay && s2_nack_no_mshr) 423 XSPerfAccumulate("load_replay_for_conflict", io.lsu.resp.fire() && resp.bits.replay && io.bank_conflict_slow) 424 XSPerfAccumulate("load_hit", io.lsu.resp.fire() && !real_miss) 425 XSPerfAccumulate("load_miss", io.lsu.resp.fire() && real_miss) 426 XSPerfAccumulate("load_succeed", io.lsu.resp.fire() && !resp.bits.miss && !resp.bits.replay) 427 XSPerfAccumulate("load_miss_or_conflict", io.lsu.resp.fire() && resp.bits.miss) 428 XSPerfAccumulate("actual_ld_fast_wakeup", s1_fire && s1_tag_match_dup_dc && !io.disable_ld_fast_wakeup) 429 XSPerfAccumulate("ideal_ld_fast_wakeup", io.banked_data_read.fire() && s1_tag_match_dup_dc) 430 431 val perfEvents = Seq( 432 ("load_req ", io.lsu.req.fire() ), 433 ("load_replay ", io.lsu.resp.fire() && resp.bits.replay ), 434 ("load_replay_for_data_nack", io.lsu.resp.fire() && resp.bits.replay && s2_nack_data ), 435 ("load_replay_for_no_mshr ", io.lsu.resp.fire() && resp.bits.replay && s2_nack_no_mshr ), 436 ("load_replay_for_conflict ", io.lsu.resp.fire() && resp.bits.replay && io.bank_conflict_slow ), 437 ) 438 generatePerfEvent() 439} 440