1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.tilelink.ClientMetadata 23import utils.{HasPerfEvents, XSDebug, XSPerfAccumulate} 24import xiangshan.L1CacheErrorInfo 25 26class LoadPipe(id: Int)(implicit p: Parameters) extends DCacheModule with HasPerfEvents { 27 val io = IO(new DCacheBundle { 28 // incoming requests 29 val lsu = Flipped(new DCacheLoadIO) 30 // req got nacked in stage 0? 31 val nack = Input(Bool()) 32 33 // meta and data array read port 34 val meta_read = DecoupledIO(new MetaReadReq) 35 val meta_resp = Input(Vec(nWays, new Meta)) 36 val error_flag_resp = Input(Vec(nWays, Bool())) 37 38 val tag_read = DecoupledIO(new TagReadReq) 39 val tag_resp = Input(Vec(nWays, UInt(encTagBits.W))) 40 41 val banked_data_read = DecoupledIO(new L1BankedDataReadReq) 42 val banked_data_resp = Input(Vec(DCacheBanks, new L1BankedDataReadResult())) 43 val read_error_delayed = Input(Bool()) 44 45 // banked data read conflict 46 val bank_conflict_slow = Input(Bool()) 47 val bank_conflict_fast = Input(Bool()) 48 49 // send miss request to miss queue 50 val miss_req = DecoupledIO(new MissReq) 51 val miss_resp = Input(new MissResp) 52 53 // update state vec in replacement algo 54 val replace_access = ValidIO(new ReplacementAccessBundle) 55 // find the way to be replaced 56 val replace_way = new ReplacementWayReqIO 57 58 // load fast wakeup should be disabled when data read is not ready 59 val disable_ld_fast_wakeup = Input(Bool()) 60 61 // ecc error 62 val error = Output(new L1CacheErrorInfo()) 63 }) 64 65 assert(RegNext(io.meta_read.ready)) 66 67 val s1_ready = Wire(Bool()) 68 val s2_ready = Wire(Bool()) 69 // LSU requests 70 // it you got nacked, you can directly passdown 71 val not_nacked_ready = io.meta_read.ready && io.tag_read.ready && s1_ready 72 val nacked_ready = true.B 73 74 // ready can wait for valid 75 io.lsu.req.ready := (!io.nack && not_nacked_ready) || (io.nack && nacked_ready) 76 io.meta_read.valid := io.lsu.req.fire() && !io.nack 77 io.tag_read.valid := io.lsu.req.fire() && !io.nack 78 79 val meta_read = io.meta_read.bits 80 val tag_read = io.tag_read.bits 81 82 // Tag read for new requests 83 meta_read.idx := get_idx(io.lsu.req.bits.addr) 84 meta_read.way_en := ~0.U(nWays.W) 85 // meta_read.tag := DontCare 86 87 tag_read.idx := get_idx(io.lsu.req.bits.addr) 88 tag_read.way_en := ~0.U(nWays.W) 89 90 // Pipeline 91 // -------------------------------------------------------------------------------- 92 // stage 0 93 // -------------------------------------------------------------------------------- 94 // read tag 95 96 val s0_valid = io.lsu.req.fire() 97 val s0_req = io.lsu.req.bits 98 val s0_fire = s0_valid && s1_ready 99 100 assert(RegNext(!(s0_valid && (s0_req.cmd =/= MemoryOpConstants.M_XRD && s0_req.cmd =/= MemoryOpConstants.M_PFR && s0_req.cmd =/= MemoryOpConstants.M_PFW))), "LoadPipe only accepts load req / softprefetch read or write!") 101 dump_pipeline_reqs("LoadPipe s0", s0_valid, s0_req) 102 103 // -------------------------------------------------------------------------------- 104 // stage 1 105 // -------------------------------------------------------------------------------- 106 // tag match, read data 107 108 val s1_valid = RegInit(false.B) 109 val s1_req = RegEnable(s0_req, s0_fire) 110 // in stage 1, load unit gets the physical address 111 val s1_paddr_dup_lsu = io.lsu.s1_paddr_dup_lsu 112 val s1_paddr_dup_dcache = io.lsu.s1_paddr_dup_dcache 113 // LSU may update the address from io.lsu.s1_paddr, which affects the bank read enable only. 114 val s1_vaddr = Cat(s1_req.addr(PAddrBits - 1, blockOffBits), io.lsu.s1_paddr_dup_lsu(blockOffBits - 1, 0)) 115 val s1_bank_oh = UIntToOH(addr_to_dcache_bank(s1_vaddr)) 116 val s1_nack = RegNext(io.nack) 117 val s1_nack_data = !io.banked_data_read.ready 118 val s1_fire = s1_valid && s2_ready 119 s1_ready := !s1_valid || s1_fire 120 121 when (s0_fire) { s1_valid := true.B } 122 .elsewhen (s1_fire) { s1_valid := false.B } 123 124 dump_pipeline_reqs("LoadPipe s1", s1_valid, s1_req) 125 126 // tag check 127 val meta_resp = io.meta_resp 128 val tag_resp = io.tag_resp.map(r => r(tagBits - 1, 0)) 129 def wayMap[T <: Data](f: Int => T) = VecInit((0 until nWays).map(f)) 130 131 // dcache side tag match 132 val s1_tag_eq_way_dup_dc = wayMap((w: Int) => tag_resp(w) === (get_tag(s1_paddr_dup_dcache))).asUInt 133 val s1_tag_match_way_dup_dc = wayMap((w: Int) => s1_tag_eq_way_dup_dc(w) && meta_resp(w).coh.isValid()).asUInt 134 val s1_tag_match_dup_dc = s1_tag_match_way_dup_dc.orR 135 assert(RegNext(!s1_valid || PopCount(s1_tag_match_way_dup_dc) <= 1.U), "tag should not match with more than 1 way") 136 137 // lsu side tag match 138 val s1_tag_eq_way_dup_lsu = wayMap((w: Int) => tag_resp(w) === (get_tag(s1_paddr_dup_lsu))).asUInt 139 val s1_tag_match_way_dup_lsu = wayMap((w: Int) => s1_tag_eq_way_dup_lsu(w) && meta_resp(w).coh.isValid()).asUInt 140 val s1_tag_match_dup_lsu = s1_tag_match_way_dup_lsu.orR 141 142 val s1_fake_meta = Wire(new Meta) 143// s1_fake_meta.tag := get_tag(s1_paddr_dup_dcache) 144 s1_fake_meta.coh := ClientMetadata.onReset 145 val s1_fake_tag = get_tag(s1_paddr_dup_dcache) 146 147 // when there are no tag match, we give it a Fake Meta 148 // this simplifies our logic in s2 stage 149 val s1_hit_meta = Mux(s1_tag_match_dup_dc, Mux1H(s1_tag_match_way_dup_dc, wayMap((w: Int) => meta_resp(w))), s1_fake_meta) 150 val s1_hit_coh = s1_hit_meta.coh 151 val s1_hit_error = Mux(s1_tag_match_dup_dc, Mux1H(s1_tag_match_way_dup_dc, wayMap((w: Int) => io.error_flag_resp(w))), false.B) 152 153 io.replace_way.set.valid := RegNext(s0_fire) 154 io.replace_way.set.bits := get_idx(s1_vaddr) 155 val s1_repl_way_en = UIntToOH(io.replace_way.way) 156 val s1_repl_tag = Mux1H(s1_repl_way_en, wayMap(w => tag_resp(w))) 157 val s1_repl_coh = Mux1H(s1_repl_way_en, wayMap(w => meta_resp(w).coh)) 158 159 val s1_need_replacement = !s1_tag_match_dup_dc 160 val s1_way_en = Mux(s1_need_replacement, s1_repl_way_en, s1_tag_match_way_dup_dc) 161 val s1_coh = Mux(s1_need_replacement, s1_repl_coh, s1_hit_coh) 162 val s1_tag = Mux(s1_need_replacement, s1_repl_tag, get_tag(s1_paddr_dup_dcache)) 163 164 // data read 165 io.banked_data_read.valid := s1_fire && !s1_nack 166 io.banked_data_read.bits.addr := s1_vaddr 167 io.banked_data_read.bits.way_en := s1_tag_match_way_dup_dc 168 169 // get s1_will_send_miss_req in lpad_s1 170 val s1_has_permission = s1_hit_coh.onAccess(s1_req.cmd)._1 171 val s1_new_hit_coh = s1_hit_coh.onAccess(s1_req.cmd)._3 172 val s1_hit = s1_tag_match_dup_dc && s1_has_permission && s1_hit_coh === s1_new_hit_coh 173 val s1_will_send_miss_req = s1_valid && !s1_nack && !s1_nack_data && !s1_hit 174 175 // check ecc error 176 val s1_encTag = Mux1H(s1_tag_match_way_dup_dc, wayMap((w: Int) => io.tag_resp(w))) 177 val s1_flag_error = Mux(s1_need_replacement, false.B, s1_hit_error) // error reported by exist dcache error bit 178 179 // -------------------------------------------------------------------------------- 180 // stage 2 181 // -------------------------------------------------------------------------------- 182 // return data 183 184 // val s2_valid = RegEnable(next = s1_valid && !io.lsu.s1_kill, init = false.B, enable = s1_fire) 185 val s2_valid = RegInit(false.B) 186 val s2_req = RegEnable(s1_req, s1_fire) 187 val s2_paddr = RegEnable(s1_paddr_dup_dcache, s1_fire) 188 val s2_vaddr = RegEnable(s1_vaddr, s1_fire) 189 val s2_bank_oh = RegEnable(s1_bank_oh, s1_fire) 190 val s2_bank_oh_dup_0 = RegEnable(s1_bank_oh, s1_fire) 191 s2_ready := true.B 192 193 val s2_fire = s2_valid 194 195 when (s1_fire) { s2_valid := !io.lsu.s1_kill } 196 .elsewhen(io.lsu.resp.fire()) { s2_valid := false.B } 197 198 dump_pipeline_reqs("LoadPipe s2", s2_valid, s2_req) 199 200 // hit, miss, nack, permission checking 201 // dcache side tag match 202 val s2_tag_match_way = RegEnable(s1_tag_match_way_dup_dc, s1_fire) 203 val s2_tag_match = RegEnable(s1_tag_match_dup_dc, s1_fire) 204 205 // lsu side tag match 206 val s2_hit_dup_lsu = RegNext(s1_tag_match_dup_lsu) 207 208 io.lsu.s2_hit := s2_hit_dup_lsu 209 210 val s2_hit_meta = RegEnable(s1_hit_meta, s1_fire) 211 val s2_hit_coh = RegEnable(s1_hit_coh, s1_fire) 212 val s2_has_permission = s2_hit_coh.onAccess(s2_req.cmd)._1 // redundant 213 val s2_new_hit_coh = s2_hit_coh.onAccess(s2_req.cmd)._3 // redundant 214 215 val s2_way_en = RegEnable(s1_way_en, s1_fire) 216 val s2_repl_coh = RegEnable(s1_repl_coh, s1_fire) 217 val s2_repl_tag = RegEnable(s1_repl_tag, s1_fire) 218 val s2_encTag = RegEnable(s1_encTag, s1_fire) 219 220 // when req got nacked, upper levels should replay this request 221 // nacked or not 222 val s2_nack_hit = RegEnable(s1_nack, s1_fire) 223 // can no allocate mshr for load miss 224 val s2_nack_no_mshr = io.miss_req.valid && !io.miss_req.ready 225 // Bank conflict on data arrays 226 val s2_nack_data = RegEnable(!io.banked_data_read.ready, s1_fire) 227 val s2_nack = s2_nack_hit || s2_nack_no_mshr || s2_nack_data 228 229 val banked_data_resp = io.banked_data_resp 230 val s2_bank_addr = addr_to_dcache_bank(s2_paddr) 231 dontTouch(s2_bank_addr) 232 233 val s2_instrtype = s2_req.instrtype 234 235 val s2_tag_error = dcacheParameters.tagCode.decode(s2_encTag).error // error reported by tag ecc check 236 val s2_flag_error = RegEnable(s1_flag_error, s1_fire) 237 238 val s2_hit = s2_tag_match && s2_has_permission && s2_hit_coh === s2_new_hit_coh 239 assert(!RegNext(s2_valid && (s2_tag_match && !s2_hit))) 240 assert(!RegNext(s2_valid && (s2_hit_dup_lsu =/= s2_hit))) 241 242 // only dump these signals when they are actually valid 243 dump_pipeline_valids("LoadPipe s2", "s2_hit", s2_valid && s2_hit) 244 dump_pipeline_valids("LoadPipe s2", "s2_nack", s2_valid && s2_nack) 245 dump_pipeline_valids("LoadPipe s2", "s2_nack_hit", s2_valid && s2_nack_hit) 246 dump_pipeline_valids("LoadPipe s2", "s2_nack_no_mshr", s2_valid && s2_nack_no_mshr) 247 248 val s2_can_send_miss_req = RegEnable(s1_will_send_miss_req, s1_fire) 249 250 // send load miss to miss queue 251 io.miss_req.valid := s2_valid && s2_can_send_miss_req 252 io.miss_req.bits := DontCare 253 io.miss_req.bits.source := s2_instrtype 254 io.miss_req.bits.cmd := s2_req.cmd 255 io.miss_req.bits.addr := get_block_addr(s2_paddr) 256 io.miss_req.bits.vaddr := s2_vaddr 257 io.miss_req.bits.way_en := s2_way_en 258 io.miss_req.bits.req_coh := s2_hit_coh 259 io.miss_req.bits.replace_coh := s2_repl_coh 260 io.miss_req.bits.replace_tag := s2_repl_tag 261 io.miss_req.bits.cancel := io.lsu.s2_kill || s2_tag_error 262 263 // send back response 264 val resp = Wire(ValidIO(new BankedDCacheWordResp)) 265 resp.valid := s2_valid 266 resp.bits := DontCare 267 resp.bits.bank_data := VecInit(banked_data_resp.map(i => i.raw_data)) 268 resp.bits.bank_oh := s2_bank_oh 269 // * on miss or nack, upper level should replay request 270 // but if we successfully sent the request to miss queue 271 // upper level does not need to replay request 272 // they can sit in load queue and wait for refill 273 // 274 // * report a miss if bank conflict is detected 275 val real_miss = !s2_hit_dup_lsu 276 resp.bits.miss := real_miss || io.bank_conflict_slow 277 // load pipe need replay when there is a bank conflict 278 resp.bits.replay := resp.bits.miss && (!io.miss_req.fire() || s2_nack) || io.bank_conflict_slow 279 resp.bits.tag_error := s2_tag_error // report tag_error in load s2 280 resp.bits.mshr_id := io.miss_resp.id 281 282 XSPerfAccumulate("dcache_read_bank_conflict", io.bank_conflict_slow && s2_valid) 283 284 io.lsu.resp.valid := resp.valid 285 io.lsu.resp.bits := resp.bits 286 assert(RegNext(!(resp.valid && !io.lsu.resp.ready)), "lsu should be ready in s2") 287 288 when (resp.valid) { 289 resp.bits.dump() 290 } 291 292 io.lsu.debug_s1_hit_way := s1_tag_match_way_dup_dc 293 io.lsu.s1_disable_fast_wakeup := io.disable_ld_fast_wakeup 294 io.lsu.s1_bank_conflict := io.bank_conflict_fast 295 assert(RegNext(s1_ready && s2_ready), "load pipeline should never be blocked") 296 297 // -------------------------------------------------------------------------------- 298 // stage 3 299 // -------------------------------------------------------------------------------- 300 // report ecc error 301 302 val s3_valid = RegNext(s2_valid) 303 val s3_paddr = RegEnable(s2_paddr, s2_fire) 304 val s3_hit = RegEnable(s2_hit, s2_fire) 305 306 val s3_data_error = io.read_error_delayed // banked_data_resp_word.error && !bank_conflict 307 val s3_tag_error = RegEnable(s2_tag_error, s2_fire) 308 val s3_flag_error = RegEnable(s2_flag_error, s2_fire) 309 val s3_error = s3_tag_error || s3_flag_error || s3_data_error 310 311 // error_delayed signal will be used to update uop.exception 1 cycle after load writeback 312 resp.bits.error_delayed := s3_error && (s3_hit || s3_tag_error) && s3_valid 313 314 // report tag / data / l2 error (with paddr) to bus error unit 315 io.error := 0.U.asTypeOf(new L1CacheErrorInfo()) 316 io.error.report_to_beu := (s3_tag_error || s3_data_error) && s3_valid 317 io.error.paddr := s3_paddr 318 io.error.source.tag := s3_tag_error 319 io.error.source.data := s3_data_error 320 io.error.source.l2 := s3_flag_error 321 io.error.opType.load := true.B 322 // report tag error / l2 corrupted to CACHE_ERROR csr 323 io.error.valid := s3_error && s3_valid 324 325 // update plru, report error in s3 326 327 io.replace_access.valid := RegNext(RegNext(RegNext(io.meta_read.fire()) && s1_valid && !io.lsu.s1_kill) && !s2_nack_no_mshr) 328 io.replace_access.bits.set := RegNext(RegNext(get_idx(s1_req.addr))) 329 io.replace_access.bits.way := RegNext(RegNext(Mux(s1_tag_match_dup_dc, OHToUInt(s1_tag_match_way_dup_dc), io.replace_way.way))) 330 331 // -------------------------------------------------------------------------------- 332 // Debug logging functions 333 def dump_pipeline_reqs(pipeline_stage_name: String, valid: Bool, 334 req: DCacheWordReq ) = { 335 when (valid) { 336 XSDebug(s"$pipeline_stage_name: ") 337 req.dump() 338 } 339 } 340 341 def dump_pipeline_valids(pipeline_stage_name: String, signal_name: String, valid: Bool) = { 342 when (valid) { 343 XSDebug(s"$pipeline_stage_name $signal_name\n") 344 } 345 } 346 347 // performance counters 348 XSPerfAccumulate("load_req", io.lsu.req.fire()) 349 XSPerfAccumulate("load_s1_kill", s1_fire && io.lsu.s1_kill) 350 XSPerfAccumulate("load_hit_way", s1_fire && s1_tag_match_dup_dc) 351 XSPerfAccumulate("load_replay", io.lsu.resp.fire() && resp.bits.replay) 352 XSPerfAccumulate("load_replay_for_data_nack", io.lsu.resp.fire() && resp.bits.replay && s2_nack_data) 353 XSPerfAccumulate("load_replay_for_no_mshr", io.lsu.resp.fire() && resp.bits.replay && s2_nack_no_mshr) 354 XSPerfAccumulate("load_replay_for_conflict", io.lsu.resp.fire() && resp.bits.replay && io.bank_conflict_slow) 355 XSPerfAccumulate("load_hit", io.lsu.resp.fire() && !real_miss) 356 XSPerfAccumulate("load_miss", io.lsu.resp.fire() && real_miss) 357 XSPerfAccumulate("load_succeed", io.lsu.resp.fire() && !resp.bits.miss && !resp.bits.replay) 358 XSPerfAccumulate("load_miss_or_conflict", io.lsu.resp.fire() && resp.bits.miss) 359 XSPerfAccumulate("actual_ld_fast_wakeup", s1_fire && s1_tag_match_dup_dc && !io.disable_ld_fast_wakeup) 360 XSPerfAccumulate("ideal_ld_fast_wakeup", io.banked_data_read.fire() && s1_tag_match_dup_dc) 361 362 val perfEvents = Seq( 363 ("load_req ", io.lsu.req.fire() ), 364 ("load_replay ", io.lsu.resp.fire() && resp.bits.replay ), 365 ("load_replay_for_data_nack", io.lsu.resp.fire() && resp.bits.replay && s2_nack_data ), 366 ("load_replay_for_no_mshr ", io.lsu.resp.fire() && resp.bits.replay && s2_nack_no_mshr ), 367 ("load_replay_for_conflict ", io.lsu.resp.fire() && resp.bits.replay && io.bank_conflict_slow ), 368 ) 369 generatePerfEvent() 370} 371