1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.tilelink.{ClientMetadata, TLClientParameters, TLEdgeOut} 23import utility.{Code, ParallelOR, ReplacementPolicy, SRAMTemplate} 24import utils.XSDebug 25import xiangshan.L1CacheErrorInfo 26 27import scala.math.max 28 29 30class L1DataReadReq(implicit p: Parameters) extends DCacheBundle { 31 // you can choose which bank to read to save power 32 val rmask = Bits(blockRows.W) 33 val way_en = Bits(nWays.W) 34 val addr = Bits(untagBits.W) 35} 36 37// Now, we can write a cache-block in a single cycle 38class L1DataWriteReq(implicit p: Parameters) extends L1DataReadReq { 39 val wmask = Bits(blockRows.W) 40 val data = Vec(blockRows, Bits(rowBits.W)) 41} 42 43abstract class AbstractDataArray(implicit p: Parameters) extends DCacheModule { 44 val io = IO(new DCacheBundle { 45 val read = Vec(3, Flipped(DecoupledIO(new L1DataReadReq))) 46 val write = Flipped(DecoupledIO(new L1DataWriteReq)) 47 val resp = Output(Vec(3, Vec(blockRows, Bits(encRowBits.W)))) 48 val nacks = Output(Vec(3, Bool())) 49 val errors = Output(Vec(3, new L1CacheErrorInfo)) 50 }) 51 52 def pipeMap[T <: Data](f: Int => T) = VecInit((0 until 3).map(f)) 53 54 def dumpRead() = { 55 (0 until 3) map { w => 56 when(io.read(w).valid) { 57 XSDebug(s"DataArray Read channel: $w valid way_en: %x addr: %x\n", 58 io.read(w).bits.way_en, io.read(w).bits.addr) 59 } 60 } 61 } 62 63 def dumpWrite() = { 64 when(io.write.valid) { 65 XSDebug(s"DataArray Write valid way_en: %x addr: %x\n", 66 io.write.bits.way_en, io.write.bits.addr) 67 68 (0 until blockRows) map { r => 69 XSDebug(s"cycle: $r data: %x wmask: %x\n", 70 io.write.bits.data(r), io.write.bits.wmask(r)) 71 } 72 } 73 } 74 75 def dumpResp() = { 76 (0 until 3) map { w => 77 XSDebug(s"DataArray ReadResp channel: $w\n") 78 (0 until blockRows) map { r => 79 XSDebug(s"cycle: $r data: %x\n", io.resp(w)(r)) 80 } 81 } 82 } 83 84 def dumpNack() = { 85 (0 until 3) map { w => 86 when(io.nacks(w)) { 87 XSDebug(s"DataArray NACK channel: $w\n") 88 } 89 } 90 } 91 92 def dump() = { 93 dumpRead 94 dumpWrite 95 dumpNack 96 dumpResp 97 } 98} 99