1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17// See LICENSE.SiFive for license details. 18 19package xiangshan.cache 20 21import chipsalliance.rocketchip.config.Parameters 22import chisel3._ 23import chisel3.util._ 24import xiangshan.{HasXSParameter, XSBundle, XSModule} 25 26// this file contains common building blocks that can be shared by ICache and DCache 27// this is the common parameter base for L1 ICache and L1 DCache 28trait L1CacheParameters { 29 def nSets: Int 30 def nWays: Int 31 def rowBits: Int 32 def blockBytes: Int 33} 34 35trait HasL1CacheParameters extends HasXSParameter 36 with MemoryOpConstants { 37 val cacheParams: L1CacheParameters 38 39 def nSets = cacheParams.nSets 40 def nWays = cacheParams.nWays 41 def blockBytes = cacheParams.blockBytes 42 def refillBytes = l1BusDataWidth / 8 43 def blockBits = blockBytes * 8 44 45 def idxBits = log2Up(cacheParams.nSets) 46 def wayBits = log2Up(nWays) 47 def blockOffBits = log2Up(cacheParams.blockBytes) 48 def refillOffBits = log2Up(l1BusDataWidth / 8) 49 50 def untagBits = blockOffBits + idxBits 51 // 4K page 52 def pgIdxBits = 12 53 def pgUntagBits = untagBits min pgIdxBits 54 def tagBits = PAddrBits - pgUntagBits 55 56 // the basic unit at which we store contents 57 // SRAM bank width 58 def rowBits = cacheParams.rowBits 59 def rowBytes = rowBits/8 60 def rowOffBits = log2Up(rowBytes) 61 // the number of rows in a block 62 def blockRows = blockBytes / rowBytes 63 64 // outer bus width 65 def beatBits = l1BusDataWidth 66 def beatBytes = beatBits / 8 67 def refillCycles = blockBytes / beatBytes 68 def beatOffBits = log2Up(beatBytes) 69 70 // inner bus width(determined by XLEN) 71 def wordBits = DataBits 72 def wordBytes = wordBits / 8 73 def wordOffBits = log2Up(wordBytes) 74 // the number of words in a block 75 def blockWords = blockBytes / wordBytes 76 def refillWords = refillBytes / wordBytes 77 78 def idxMSB = untagBits-1 79 def idxLSB = blockOffBits 80 def offsetmsb = idxLSB-1 81 def offsetlsb = wordOffBits 82 83 def get_tag(addr: UInt) = (addr >> untagBits).asUInt() 84 def get_phy_tag(paddr: UInt) = (paddr >> pgUntagBits).asUInt() 85 def get_idx(addr: UInt) = addr(untagBits-1, blockOffBits) 86 def get_block(addr: UInt) = addr >> blockOffBits 87 def get_block_addr(addr: UInt) = (addr >> blockOffBits) << blockOffBits 88 def get_refill_addr(addr: UInt) = (addr >> refillOffBits) << refillOffBits 89 90 def get_beat(addr: UInt) = addr(blockOffBits - 1, beatOffBits) 91 def get_row(addr: UInt) = addr(blockOffBits - 1, rowOffBits) 92 def get_word(addr: UInt) = addr(blockOffBits - 1, wordOffBits) 93 94 def beatRows = beatBits/rowBits 95 def rowWords = rowBits/wordBits 96 def blockBeats = blockBytes / beatBytes 97 98 def full_divide(a: Int, b: Int) = a >= b && isPow2(a / b) 99} 100 101abstract class L1CacheModule(implicit p: Parameters) extends XSModule 102 with HasL1CacheParameters 103 104abstract class L1CacheBundle(implicit p: Parameters) extends XSBundle 105 with HasL1CacheParameters 106