1package xiangshan.backend.rename 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import utils.XSInfo 7 8class RenameBypassInfo extends XSBundle { 9 val lsrc1_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 10 val lsrc2_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 11 val lsrc3_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 12 val ldest_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 13} 14 15class Rename extends XSModule { 16 val io = IO(new Bundle() { 17 val redirect = Flipped(ValidIO(new Redirect)) 18 val roqCommits = Flipped(new RoqCommitIO) 19 // from decode buffer 20 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 21 // to dispatch1 22 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 23 val renameBypass = Output(new RenameBypassInfo) 24 }) 25 26 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 27 XSInfo( 28 in.valid && in.ready, 29 p"pc:${Hexadecimal(in.bits.cf.pc)} in v:${in.valid} in rdy:${in.ready} " + 30 p"lsrc1:${in.bits.ctrl.lsrc1} -> psrc1:${out.bits.psrc1} " + 31 p"lsrc2:${in.bits.ctrl.lsrc2} -> psrc2:${out.bits.psrc2} " + 32 p"lsrc3:${in.bits.ctrl.lsrc3} -> psrc3:${out.bits.psrc3} " + 33 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 34 p"old_pdest:${out.bits.old_pdest} " + 35 p"out v:${out.valid} r:${out.ready}\n" 36 ) 37 } 38 39 for((x,y) <- io.in.zip(io.out)){ 40 printRenameInfo(x, y) 41 } 42 43 val intFreeList, fpFreeList = Module(new FreeList).io 44 val intRat = Module(new RenameTable(float = false)).io 45 val fpRat = Module(new RenameTable(float = true)).io 46 val allPhyResource = Seq((intRat, intFreeList, false), (fpRat, fpFreeList, true)) 47 48 allPhyResource.map{ case (rat, freelist, _) => 49 rat.redirect := io.redirect 50 rat.walkWen := io.roqCommits.isWalk 51 freelist.redirect := io.redirect 52 freelist.walk.valid := io.roqCommits.isWalk 53 } 54 55 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 56 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 57 } 58 def needDestRegCommit[T <: RoqCommitInfo](fp: Boolean, x: T): Bool = { 59 {if(fp) x.fpWen else x.rfWen && (x.ldest =/= 0.U)} 60 } 61 fpFreeList.walk.bits := PopCount(io.roqCommits.valid.zip(io.roqCommits.info).map{case (v, i) => v && needDestRegCommit(true, i)}) 62 intFreeList.walk.bits := PopCount(io.roqCommits.valid.zip(io.roqCommits.info).map{case (v, i) => v && needDestRegCommit(false, i)}) 63 // walk has higher priority than allocation and thus we don't use isWalk here 64 fpFreeList.req.doAlloc := intFreeList.req.canAlloc && io.out(0).ready 65 intFreeList.req.doAlloc := fpFreeList.req.canAlloc && io.out(0).ready 66 67 /** 68 * Rename: allocate free physical register and update rename table 69 */ 70 val uops = Wire(Vec(RenameWidth, new MicroOp)) 71 72 uops.foreach( uop => { 73// uop.brMask := DontCare 74// uop.brTag := DontCare 75 uop.src1State := DontCare 76 uop.src2State := DontCare 77 uop.src3State := DontCare 78 uop.roqIdx := DontCare 79 uop.diffTestDebugLrScValid := DontCare 80 uop.lqIdx := DontCare 81 uop.sqIdx := DontCare 82 }) 83 84 val needFpDest = Wire(Vec(RenameWidth, Bool())) 85 val needIntDest = Wire(Vec(RenameWidth, Bool())) 86 val hasValid = Cat(io.in.map(_.valid)).orR 87 val canOut = io.out(0).ready && fpFreeList.req.canAlloc && intFreeList.req.canAlloc && !io.roqCommits.isWalk 88 for (i <- 0 until RenameWidth) { 89 uops(i).cf := io.in(i).bits.cf 90 uops(i).ctrl := io.in(i).bits.ctrl 91 uops(i).brTag := io.in(i).bits.brTag 92 93 val inValid = io.in(i).valid 94 95 // alloc a new phy reg 96 needFpDest(i) := inValid && needDestReg(fp = true, io.in(i).bits) 97 needIntDest(i) := inValid && needDestReg(fp = false, io.in(i).bits) 98 fpFreeList.req.allocReqs(i) := needFpDest(i) 99 intFreeList.req.allocReqs(i) := needIntDest(i) 100 101 io.in(i).ready := !hasValid || canOut 102 103 // do checkpoints when a branch inst come 104 // for(fl <- Seq(fpFreeList, intFreeList)){ 105 // fl.cpReqs(i).valid := inValid 106 // fl.cpReqs(i).bits := io.in(i).bits.brTag 107 // } 108 109 uops(i).pdest := Mux(needIntDest(i), 110 intFreeList.req.pdests(i), 111 Mux( 112 uops(i).ctrl.ldest===0.U && uops(i).ctrl.rfWen, 113 0.U, fpFreeList.req.pdests(i) 114 ) 115 ) 116 117 io.out(i).valid := io.in(i).valid && intFreeList.req.canAlloc && fpFreeList.req.canAlloc && !io.roqCommits.isWalk 118 io.out(i).bits := uops(i) 119 120 // write speculative rename table 121 allPhyResource.map{ case (rat, freelist, _) => 122 val specWen = freelist.req.allocReqs(i) && freelist.req.canAlloc && freelist.req.doAlloc && !io.roqCommits.isWalk 123 124 rat.specWritePorts(i).wen := specWen 125 rat.specWritePorts(i).addr := uops(i).ctrl.ldest 126 rat.specWritePorts(i).wdata := freelist.req.pdests(i) 127 128 freelist.deallocReqs(i) := specWen 129 } 130 131 // read rename table 132 def readRat(lsrcList: List[UInt], ldest: UInt, fp: Boolean) = { 133 val rat = if(fp) fpRat else intRat 134 val srcCnt = lsrcList.size 135 val psrcVec = Wire(Vec(srcCnt, UInt(PhyRegIdxWidth.W))) 136 val old_pdest = Wire(UInt(PhyRegIdxWidth.W)) 137 for(k <- 0 until srcCnt+1){ 138 val rportIdx = i * (srcCnt+1) + k 139 if(k != srcCnt){ 140 rat.readPorts(rportIdx).addr := lsrcList(k) 141 psrcVec(k) := rat.readPorts(rportIdx).rdata 142 } else { 143 rat.readPorts(rportIdx).addr := ldest 144 old_pdest := rat.readPorts(rportIdx).rdata 145 } 146 } 147 (psrcVec, old_pdest) 148 } 149 val lsrcList = List(uops(i).ctrl.lsrc1, uops(i).ctrl.lsrc2, uops(i).ctrl.lsrc3) 150 val ldest = uops(i).ctrl.ldest 151 val (intPhySrcVec, intOldPdest) = readRat(lsrcList.take(2), ldest, fp = false) 152 val (fpPhySrcVec, fpOldPdest) = readRat(lsrcList, ldest, fp = true) 153 uops(i).psrc1 := Mux(uops(i).ctrl.src1Type === SrcType.reg, intPhySrcVec(0), fpPhySrcVec(0)) 154 uops(i).psrc2 := Mux(uops(i).ctrl.src2Type === SrcType.reg, intPhySrcVec(1), fpPhySrcVec(1)) 155 uops(i).psrc3 := fpPhySrcVec(2) 156 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, intOldPdest, fpOldPdest) 157 } 158 159 // We don't bypass the old_pdest from valid instructions with the same ldest currently in rename stage. 160 // Instead, we determine whether there're some dependences between the valid instructions. 161 for (i <- 1 until RenameWidth) { 162 io.renameBypass.lsrc1_bypass(i-1) := Cat((0 until i).map(j => { 163 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src1Type === SrcType.fp 164 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src1Type === SrcType.reg 165 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc1 166 }).reverse) 167 io.renameBypass.lsrc2_bypass(i-1) := Cat((0 until i).map(j => { 168 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src2Type === SrcType.fp 169 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src2Type === SrcType.reg 170 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc2 171 }).reverse) 172 io.renameBypass.lsrc3_bypass(i-1) := Cat((0 until i).map(j => { 173 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src3Type === SrcType.fp 174 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src3Type === SrcType.reg 175 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc3 176 }).reverse) 177 io.renameBypass.ldest_bypass(i-1) := Cat((0 until i).map(j => { 178 val fpMatch = needFpDest(j) && needFpDest(i) 179 val intMatch = needIntDest(j) && needIntDest(i) 180 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.ldest 181 }).reverse) 182 } 183 184 /** 185 * Instructions commit: update freelist and rename table 186 */ 187 for (i <- 0 until CommitWidth) { 188 if (i >= RenameWidth) { 189 allPhyResource.map{ case (rat, _, _) => 190 rat.specWritePorts(i).wen := false.B 191 rat.specWritePorts(i).addr := DontCare 192 rat.specWritePorts(i).wdata := DontCare 193 } 194 } 195 196 allPhyResource.map{ case (rat, freelist, fp) => 197 // walk back write 198 val commitDestValid = io.roqCommits.valid(i) && needDestRegCommit(fp, io.roqCommits.info(i)) 199 200 when (commitDestValid && io.roqCommits.isWalk) { 201 rat.specWritePorts(i).wen := true.B 202 rat.specWritePorts(i).addr := io.roqCommits.info(i).ldest 203 rat.specWritePorts(i).wdata := io.roqCommits.info(i).old_pdest 204 XSInfo({if(fp) p"fp" else p"int "} + p"walk: " + 205 p" ldest:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n") 206 } 207 208 rat.archWritePorts(i).wen := commitDestValid && !io.roqCommits.isWalk 209 rat.archWritePorts(i).addr := io.roqCommits.info(i).ldest 210 rat.archWritePorts(i).wdata := io.roqCommits.info(i).pdest 211 212 XSInfo(rat.archWritePorts(i).wen, 213 {if(fp) p"fp" else p"int "} + p" rat arch: ldest:${rat.archWritePorts(i).addr}" + 214 p" pdest:${rat.archWritePorts(i).wdata}\n" 215 ) 216 217 freelist.deallocReqs(i) := rat.archWritePorts(i).wen 218 freelist.deallocPregs(i) := io.roqCommits.info(i).old_pdest 219 } 220 } 221} 222