1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import utils._ 24import xiangshan.backend.roq.RoqPtr 25import xiangshan.backend.dispatch.PreDispatchInfo 26 27class RenameBypassInfo(implicit p: Parameters) extends XSBundle { 28 val lsrc1_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 29 val lsrc2_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 30 val lsrc3_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 31 val ldest_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 32} 33 34class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper { 35 val io = IO(new Bundle() { 36 val redirect = Flipped(ValidIO(new Redirect)) 37 val flush = Input(Bool()) 38 val roqCommits = Flipped(new RoqCommitIO) 39 // from decode buffer 40 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 41 // to dispatch1 42 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 43 val renameBypass = Output(new RenameBypassInfo) 44 val dispatchInfo = Output(new PreDispatchInfo) 45 // for debug printing 46 val debug_int_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 47 val debug_fp_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 48 }) 49 50 // create free list and rat 51 val intFreeList = Module(new AlternativeFreeList) 52 val fpFreeList = Module(new FreeList) 53 54 val intRat = Module(new RenameTable(float = false)) 55 val fpRat = Module(new RenameTable(float = true)) 56 57 // connect flush and redirect ports for rat 58 Seq(intRat, fpRat) foreach { case rat => 59 rat.io.redirect := io.redirect.valid 60 rat.io.flush := io.flush 61 rat.io.walkWen := io.roqCommits.isWalk 62 } 63 64 // connect flush and redirect ports for __float point__ free list 65 fpFreeList.io.flush := io.flush 66 fpFreeList.io.redirect := io.redirect.valid 67 fpFreeList.io.walk.valid := io.roqCommits.isWalk 68 69 // connect flush and redirect ports for __integer__ free list *(walk) is handled by dec 70 intFreeList.io.flush := io.flush 71 intFreeList.io.redirect := io.redirect.valid 72 intFreeList.io.walk := io.roqCommits.isWalk 73 74 // dispatch1 ready ++ float point free list ready ++ int free list ready ++ not walk 75 val canOut = io.out(0).ready && fpFreeList.io.req.canAlloc && intFreeList.io.inc.canInc && !io.roqCommits.isWalk 76 77 // decide if given instruction needs allocating a new physical register (CfCtrl: from decode; RoqCommitInfo: from roq) 78 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 79 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 80 } 81 def needDestRegCommit[T <: RoqCommitInfo](fp: Boolean, x: T): Bool = { 82 {if(fp) x.fpWen else x.rfWen && (x.ldest =/= 0.U)} 83 } 84 85 // when roqCommits.isWalk, use walk.bits to restore head pointer of free list 86 fpFreeList.io.walk.bits := PopCount(io.roqCommits.valid.zip(io.roqCommits.info).map{case (v, i) => v && needDestRegCommit(true, i)}) 87 88 89 // walk has higher priority than allocation and thus we don't use isWalk here 90 // only when both fp and int free list and dispatch1 has enough space can we do allocation 91 fpFreeList.io.req.doAlloc := intFreeList.io.inc.canInc && io.out(0).ready 92 intFreeList.io.inc.doInc := fpFreeList.io.req.canAlloc && io.out(0).ready 93 94 95 96 // speculatively assign the instruction with an roqIdx 97 val validCount = PopCount(io.in.map(_.valid)) // number of instructions waiting to enter roq (from decode) 98 val roqIdxHead = RegInit(0.U.asTypeOf(new RoqPtr)) 99 val lastCycleMisprediction = RegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 100 val roqIdxHeadNext = Mux(io.flush, 0.U.asTypeOf(new RoqPtr), // flush: clear roq 101 Mux(io.redirect.valid, io.redirect.bits.roqIdx, // redirect: move ptr to given roq index (flush itself) 102 Mux(lastCycleMisprediction, roqIdxHead + 1.U, // mis-predict: not flush roqIdx itself 103 Mux(canOut, roqIdxHead + validCount, // instructions successfully entered next stage: increase roqIdx 104 /* default */ roqIdxHead)))) // no instructions passed by this cycle: stick to old value 105 roqIdxHead := roqIdxHeadNext 106 107 108 /** 109 * Rename: allocate free physical register and update rename table 110 */ 111 val uops = Wire(Vec(RenameWidth, new MicroOp)) 112 uops.foreach( uop => { 113 uop.srcState(0) := DontCare 114 uop.srcState(1) := DontCare 115 uop.srcState(2) := DontCare 116 uop.roqIdx := DontCare 117 uop.diffTestDebugLrScValid := DontCare 118 uop.debugInfo := DontCare 119 uop.lqIdx := DontCare 120 uop.sqIdx := DontCare 121 }) 122 123 val needFpDest = Wire(Vec(RenameWidth, Bool())) 124 val needIntDest = Wire(Vec(RenameWidth, Bool())) 125 val hasValid = Cat(io.in.map(_.valid)).orR 126 127 val isMove = io.in.map(_.bits.ctrl.isMove) 128 val isMax = intFreeList.io.maxVec 129 val meEnable = WireInit(VecInit(Seq.fill(RenameWidth)(false.B))) 130 val psrc_cmp = Wire(MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W)))) 131 132 val intSpecWen = Wire(Vec(RenameWidth, Bool())) 133 val fpSpecWen = Wire(Vec(RenameWidth, Bool())) 134 135 // uop calculation 136 for (i <- 0 until RenameWidth) { 137 uops(i).cf := io.in(i).bits.cf 138 uops(i).ctrl := io.in(i).bits.ctrl 139 140 val inValid = io.in(i).valid 141 142 // alloc a new phy reg 143 needFpDest(i) := inValid && needDestReg(fp = true, io.in(i).bits) 144 needIntDest(i) := inValid && needDestReg(fp = false, io.in(i).bits) 145 fpFreeList.io.req.allocReqs(i) := needFpDest(i) 146 intFreeList.io.inc.req(i) := needIntDest(i) 147 148 // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready 149 io.in(i).ready := !hasValid || canOut 150 151 // do checkpoints when a branch inst come 152 // for(fl <- Seq(fpFreeList, intFreeList)){ 153 // fl.cpReqs(i).valid := inValid 154 // fl.cpReqs(i).bits := io.in(i).bits.brTag 155 // } 156 157 158 uops(i).roqIdx := roqIdxHead + i.U 159 160 io.out(i).valid := io.in(i).valid && intFreeList.io.inc.canInc && fpFreeList.io.req.canAlloc && !io.roqCommits.isWalk 161 io.out(i).bits := uops(i) 162 163 164 // read rename table 165 def readRat(lsrcList: List[UInt], ldest: UInt, fp: Boolean) = { 166 val rat = if(fp) fpRat else intRat 167 val srcCnt = lsrcList.size 168 val psrcVec = Wire(Vec(srcCnt, UInt(PhyRegIdxWidth.W))) 169 val old_pdest = Wire(UInt(PhyRegIdxWidth.W)) 170 for(k <- 0 until srcCnt+1){ 171 val rportIdx = i * (srcCnt+1) + k 172 if(k != srcCnt){ 173 rat.io.readPorts(rportIdx).addr := lsrcList(k) 174 psrcVec(k) := rat.io.readPorts(rportIdx).rdata 175 } else { 176 rat.io.readPorts(rportIdx).addr := ldest 177 old_pdest := rat.io.readPorts(rportIdx).rdata 178 } 179 } 180 (psrcVec, old_pdest) 181 } 182 val lsrcList = List(uops(i).ctrl.lsrc(0), uops(i).ctrl.lsrc(1), uops(i).ctrl.lsrc(2)) 183 val ldest = uops(i).ctrl.ldest 184 val (intPhySrcVec, intOldPdest) = readRat(lsrcList.take(2), ldest, fp = false) 185 val (fpPhySrcVec, fpOldPdest) = readRat(lsrcList, ldest, fp = true) 186 uops(i).psrc(0) := Mux(uops(i).ctrl.srcType(0) === SrcType.reg, intPhySrcVec(0), fpPhySrcVec(0)) 187 uops(i).psrc(1) := Mux(uops(i).ctrl.srcType(1) === SrcType.reg, intPhySrcVec(1), fpPhySrcVec(1)) 188 uops(i).psrc(2) := fpPhySrcVec(2) 189 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, intOldPdest, fpOldPdest) 190 191 if (i == 0) { 192 // calculate meEnable 193 meEnable(i) := isMove(i) && !isMax(uops(i).psrc(0)) 194 } else { 195 // compare psrc0 196 psrc_cmp(i-1) := Cat((0 until i).map(j => { 197 uops(i).psrc(0) === uops(j).psrc(0) && io.in(i).bits.ctrl.isMove && io.in(j).bits.ctrl.isMove 198 }) /* reverse is not necessary here */) 199 200 // calculate meEnable 201 meEnable(i) := isMove(i) && !(io.renameBypass.lsrc1_bypass(i-1).orR | psrc_cmp(i-1).orR | isMax(uops(i).psrc(0))) 202 } 203 uops(i).eliminatedMove := meEnable(i) 204 205 // send psrc of eliminated move instructions to free list and label them as eliminated 206 when (meEnable(i)) { 207 intFreeList.io.inc.psrcOfMove(i).valid := true.B 208 intFreeList.io.inc.psrcOfMove(i).bits := uops(i).psrc(0) 209 XSInfo(io.in(i).valid && io.out(i).valid, p"Move instruction ${Hexadecimal(io.in(i).bits.cf.pc)} eliminated successfully! psrc:${uops(i).psrc(0)}\n") 210 } .otherwise { 211 intFreeList.io.inc.psrcOfMove(i).valid := false.B 212 intFreeList.io.inc.psrcOfMove(i).bits := DontCare 213 XSInfo(io.in(i).valid && io.out(i).valid && isMove(i), p"Move instruction ${Hexadecimal(io.in(i).bits.cf.pc)} failed to be eliminated! psrc:${uops(i).psrc(0)}\n") 214 } 215 216 // update pdest 217 uops(i).pdest := Mux(meEnable(i), uops(i).psrc(0), // move eliminated 218 Mux(needIntDest(i), intFreeList.io.inc.pdests(i), // normal int inst 219 Mux(uops(i).ctrl.ldest===0.U && uops(i).ctrl.rfWen, 0.U // int inst with dst=r0 220 /* default */, fpFreeList.io.req.pdests(i)))) // normal fp inst 221 222 // write speculative rename table 223 intSpecWen(i) := intFreeList.io.inc.req(i) && intFreeList.io.inc.canInc && intFreeList.io.inc.doInc && !io.roqCommits.isWalk 224 // intRat.io.specWritePorts(i).wen := intSpecWen 225 // intRat.io.specWritePorts(i).addr := uops(i).ctrl.ldest 226 // intRat.io.specWritePorts(i).wdata := Mux(meEnable(i), uops(i).psrc(0), intFreeList.io.inc.pdests(i)) 227 228 fpSpecWen(i) := fpFreeList.io.req.allocReqs(i) && fpFreeList.io.req.canAlloc && fpFreeList.io.req.doAlloc && !io.roqCommits.isWalk 229 // fpRat.io.specWritePorts(i).wen := fpSpecWen 230 // fpRat.io.specWritePorts(i).addr := uops(i).ctrl.ldest 231 // fpRat.io.specWritePorts(i).wdata := fpFreeList.io.req.pdests(i) 232 } 233 234 // We don't bypass the old_pdest from valid instructions with the same ldest currently in rename stage. 235 // Instead, we determine whether there're some dependencies between the valid instructions. 236 for (i <- 1 until RenameWidth) { 237 io.renameBypass.lsrc1_bypass(i-1) := Cat((0 until i).map(j => { 238 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.srcType(0) === SrcType.fp 239 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.srcType(0) === SrcType.reg 240 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc(0) 241 }).reverse) 242 io.renameBypass.lsrc2_bypass(i-1) := Cat((0 until i).map(j => { 243 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.srcType(1) === SrcType.fp 244 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.srcType(1) === SrcType.reg 245 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc(1) 246 }).reverse) 247 io.renameBypass.lsrc3_bypass(i-1) := Cat((0 until i).map(j => { 248 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.srcType(2) === SrcType.fp 249 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.srcType(2) === SrcType.reg 250 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc(2) 251 }).reverse) 252 io.renameBypass.ldest_bypass(i-1) := Cat((0 until i).map(j => { 253 val fpMatch = needFpDest(j) && needFpDest(i) 254 val intMatch = needIntDest(j) && needIntDest(i) 255 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.ldest 256 }).reverse) 257 } 258 259 // calculate lsq space requirement 260 val isLs = VecInit(uops.map(uop => FuType.isLoadStore(uop.ctrl.fuType))) 261 val isStore = VecInit(uops.map(uop => FuType.isStoreExu(uop.ctrl.fuType))) 262 val isAMO = VecInit(uops.map(uop => FuType.isAMO(uop.ctrl.fuType))) 263 io.dispatchInfo.lsqNeedAlloc := VecInit((0 until RenameWidth).map(i => 264 Mux(isLs(i), Mux(isStore(i) && !isAMO(i), 2.U, 1.U), 0.U))) 265 266 /** 267 * Instructions commit: update freelist and rename table 268 */ 269 for (i <- 0 until CommitWidth) { 270 // when RenameWidth <= CommitWidth, there will be more write ports than read ports, which must be initialized 271 // normally, they are initialized in 'normal write' section 272 if (i >= RenameWidth) { 273 Seq(intRat, fpRat) foreach { case rat => 274 rat.io.specWritePorts(i).wen := false.B 275 rat.io.specWritePorts(i).addr := DontCare 276 rat.io.specWritePorts(i).wdata := DontCare 277 } 278 } 279 280 Seq((intRat, false), (fpRat, true)) foreach { case (rat, fp) => 281 // is valid commit req and given instruction has destination register 282 val commitDestValid = io.roqCommits.valid(i) && needDestRegCommit(fp, io.roqCommits.info(i)) 283 XSDebug(p"isFp[${fp}]index[$i]-commitDestValid:$commitDestValid,isWalk:${io.roqCommits.isWalk}\n") 284 285 /* 286 I. RAT Update 287 */ 288 289 // walk back write - restore spec state : ldest => old_pdest 290 if (fp && i < RenameWidth) { 291 rat.io.specWritePorts(i).wen := (commitDestValid && io.roqCommits.isWalk) || fpSpecWen(i) 292 rat.io.specWritePorts(i).addr := Mux(fpSpecWen(i), uops(i).ctrl.ldest, io.roqCommits.info(i).ldest) 293 rat.io.specWritePorts(i).wdata := Mux(fpSpecWen(i), fpFreeList.io.req.pdests(i), io.roqCommits.info(i).old_pdest) 294 } else if (!fp && i < RenameWidth) { 295 rat.io.specWritePorts(i).wen := (commitDestValid && io.roqCommits.isWalk) || intSpecWen(i) 296 rat.io.specWritePorts(i).addr := Mux(intSpecWen(i), uops(i).ctrl.ldest, io.roqCommits.info(i).ldest) 297 rat.io.specWritePorts(i).wdata := Mux(intSpecWen(i), Mux(meEnable(i), uops(i).psrc(0), intFreeList.io.inc.pdests(i)), io.roqCommits.info(i).old_pdest) 298 } else if (fp && i >= RenameWidth) { 299 rat.io.specWritePorts(i).wen := commitDestValid && io.roqCommits.isWalk 300 rat.io.specWritePorts(i).addr := io.roqCommits.info(i).ldest 301 rat.io.specWritePorts(i).wdata := io.roqCommits.info(i).old_pdest 302 } else if (!fp && i >= RenameWidth) { 303 rat.io.specWritePorts(i).wen := commitDestValid && io.roqCommits.isWalk 304 rat.io.specWritePorts(i).addr := io.roqCommits.info(i).ldest 305 rat.io.specWritePorts(i).wdata := io.roqCommits.info(i).old_pdest 306 } 307 308 when (commitDestValid && io.roqCommits.isWalk) { 309 XSInfo({if(fp) p"[fp" else p"[int"} + p" walk] " + 310 p"ldest:${rat.io.specWritePorts(i).addr} -> old_pdest:${rat.io.specWritePorts(i).wdata}\n") 311 } 312 313 // normal write - update arch state (serve as initialization) 314 rat.io.archWritePorts(i).wen := commitDestValid && !io.roqCommits.isWalk 315 rat.io.archWritePorts(i).addr := io.roqCommits.info(i).ldest 316 rat.io.archWritePorts(i).wdata := io.roqCommits.info(i).pdest 317 318 XSInfo(rat.io.archWritePorts(i).wen, 319 {if(fp) p"[fp" else p"[int"} + p" arch rat update] ldest:${rat.io.archWritePorts(i).addr} ->" + 320 p" pdest:${rat.io.archWritePorts(i).wdata}\n" 321 ) 322 323 324 /* 325 II. Free List Update 326 */ 327 328 if (fp) { // Float Point free list 329 fpFreeList.io.deallocReqs(i) := commitDestValid && !io.roqCommits.isWalk 330 fpFreeList.io.deallocPregs(i) := io.roqCommits.info(i).old_pdest 331 } else { // Integer free list 332 333 // during walk process: 334 // 1. for normal inst, free pdest + revert rat from ldest->pdest to ldest->old_pdest 335 // 2. for ME inst, free pdest(commit counter++) + revert rat 336 337 // conclusion: 338 // a. rat recovery has nothing to do with ME or not 339 // b. treat walk as normal commit except replace old_pdests with pdests and set io.walk to true 340 // c. ignore pdests port when walking 341 342 intFreeList.io.dec.req(i) := commitDestValid // walk or not walk 343 intFreeList.io.dec.old_pdests(i) := Mux(io.roqCommits.isWalk, io.roqCommits.info(i).pdest, io.roqCommits.info(i).old_pdest) 344 intFreeList.io.dec.eliminatedMove(i) := io.roqCommits.info(i).eliminatedMove 345 intFreeList.io.dec.pdests(i) := io.roqCommits.info(i).pdest 346 } 347 } 348 } 349 350 351 /* 352 Debug and performance counter 353 */ 354 355 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 356 XSInfo( 357 in.valid && in.ready, 358 p"pc:${Hexadecimal(in.bits.cf.pc)} in v:${in.valid} in rdy:${in.ready} " + 359 p"lsrc(0):${in.bits.ctrl.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 360 p"lsrc(1):${in.bits.ctrl.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 361 p"lsrc(2):${in.bits.ctrl.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 362 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 363 p"old_pdest:${out.bits.old_pdest} " + 364 p"out v:${out.valid} r:${out.ready}\n" 365 ) 366 } 367 368 for((x,y) <- io.in.zip(io.out)){ 369 printRenameInfo(x, y) 370 } 371 372 XSDebug(io.roqCommits.isWalk, p"Walk Recovery Enabled\n") 373 XSDebug(io.roqCommits.isWalk, p"validVec:${Binary(io.roqCommits.valid.asUInt)}\n") 374 for (i <- 0 until CommitWidth) { 375 val info = io.roqCommits.info(i) 376 XSDebug(io.roqCommits.isWalk && io.roqCommits.valid(i), p"[#$i walk info] pc:${Hexadecimal(info.pc)} " + 377 p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} eliminatedMove:${info.eliminatedMove} " + 378 p"pdest:${info.pdest} old_pdest:${info.old_pdest}\n") 379 } 380 381 XSDebug(p"inValidVec: ${Binary(Cat(io.in.map(_.valid)))}\n") 382 XSInfo(!canOut, p"stall at rename, hasValid:${hasValid}, fpCanAlloc:${fpFreeList.io.req.canAlloc}, intCanAlloc:${intFreeList.io.inc.canInc} dispatch1ready:${io.out(0).ready}, isWalk:${io.roqCommits.isWalk}\n") 383 XSInfo(meEnable.asUInt().orR(), p"meEnableVec:${Binary(meEnable.asUInt)}\n") 384 385 intRat.io.debug_rdata <> io.debug_int_rat 386 fpRat.io.debug_rdata <> io.debug_fp_rat 387 388 XSDebug(p"Arch Int RAT:" + io.debug_int_rat.zipWithIndex.map{ case (r, i) => p"#$i:$r " }.reduceLeft(_ + _) + p"\n") 389 390 XSPerfAccumulate("in", Mux(RegNext(io.in(0).ready), PopCount(io.in.map(_.valid)), 0.U)) 391 XSPerfAccumulate("utilization", PopCount(io.in.map(_.valid))) 392 XSPerfAccumulate("waitInstr", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready))) 393 XSPerfAccumulate("stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.io.req.canAlloc && intFreeList.io.inc.canInc && !io.roqCommits.isWalk) 394 XSPerfAccumulate("stall_cycle_fp", hasValid && io.out(0).ready && !fpFreeList.io.req.canAlloc && intFreeList.io.inc.canInc && !io.roqCommits.isWalk) 395 XSPerfAccumulate("stall_cycle_int", hasValid && io.out(0).ready && fpFreeList.io.req.canAlloc && !intFreeList.io.inc.canInc && !io.roqCommits.isWalk) 396 XSPerfAccumulate("stall_cycle_walk", hasValid && io.out(0).ready && fpFreeList.io.req.canAlloc && intFreeList.io.inc.canInc && io.roqCommits.isWalk) 397 if (!env.FPGAPlatform) { 398 ExcitingUtils.addSource(io.roqCommits.isWalk, "TMA_backendiswalk") 399 } 400 XSPerfAccumulate("move_instr_count", PopCount(Seq.tabulate(RenameWidth)(i => io.out(i).fire() && io.in(i).bits.ctrl.isMove))) 401 XSPerfAccumulate("move_elim_enabled", PopCount(Seq.tabulate(RenameWidth)(i => io.out(i).fire() && meEnable(i)))) 402 XSPerfAccumulate("move_elim_cancelled", PopCount(Seq.tabulate(RenameWidth)(i => io.out(i).fire() && io.in(i).bits.ctrl.isMove && !meEnable(i)))) 403 XSPerfAccumulate("move_elim_cancelled_psrc_bypass", PopCount(Seq.tabulate(RenameWidth)(i => io.out(i).fire() && io.in(i).bits.ctrl.isMove && !meEnable(i) && { if (i == 0) false.B else io.renameBypass.lsrc1_bypass(i-1).orR }))) 404 XSPerfAccumulate("move_elim_cancelled_cnt_limit", PopCount(Seq.tabulate(RenameWidth)(i => io.out(i).fire() && io.in(i).bits.ctrl.isMove && !meEnable(i) && isMax(io.out(i).bits.psrc(0))))) 405 XSPerfAccumulate("move_elim_cancelled_inc_more_than_one", PopCount(Seq.tabulate(RenameWidth)(i => io.out(i).fire() && io.in(i).bits.ctrl.isMove && !meEnable(i) && { if (i == 0) false.B else psrc_cmp(i-1).orR }))) 406 407 // to make sure meEnable functions as expected 408 for (i <- 0 until RenameWidth) { 409 XSDebug(io.out(i).fire() && io.in(i).bits.ctrl.isMove && !meEnable(i) && isMax(io.out(i).bits.psrc(0)), 410 p"ME_CANCELLED: ref counter hits max value (pc:0x${Hexadecimal(io.in(i).bits.cf.pc)})\n") 411 XSDebug(io.out(i).fire() && io.in(i).bits.ctrl.isMove && !meEnable(i) && { if (i == 0) false.B else io.renameBypass.lsrc1_bypass(i-1).orR }, 412 p"ME_CANCELLED: RAW dependency (pc:0x${Hexadecimal(io.in(i).bits.cf.pc)})\n") 413 XSDebug(io.out(i).fire() && io.in(i).bits.ctrl.isMove && !meEnable(i) && { if (i == 0) false.B else psrc_cmp(i-1).orR }, 414 p"ME_CANCELLED: psrc duplicates with former instruction (pc:0x${Hexadecimal(io.in(i).bits.cf.pc)})\n") 415 } 416 XSDebug(VecInit(Seq.tabulate(RenameWidth)(i => io.out(i).fire() && io.in(i).bits.ctrl.isMove && !meEnable(i))).asUInt().orR, 417 p"ME_CANCELLED: pc group [ " + (0 until RenameWidth).map(i => p"fire:${io.out(i).fire()},pc:0x${Hexadecimal(io.in(i).bits.cf.pc)} ").reduceLeft(_ + _) + p"]\n") 418} 419